Showing papers in "IEEE Transactions on Electron Devices in 2016"

Demonstration of L-Shaped Tunnel Field-Effect Transistors

Abstract: An L-shaped tunnel FET (TFET), which features band-to-band tunneling (BTBT) perpendicular to the channel direction, is experimentally demonstrated for the first time. It is more scalable than other vertical-BTBT-based TFET designs and provides more than $1000\times $ higher ON-current ( $I_{{\mathrm{\scriptscriptstyle ON}}}$ ) than a conventional planar TFET with the same gate overdrive ( $V_{\mathrm{ov}}$ ) of 0.8 V, due to improved subthreshold swing ( $S$ ) and larger tunnel junction area. Its temperature dependence, constant $S$ , and nonlinear output characteristics are discussed.

Charge-Trapping Phenomena in HfO 2 -Based FeFET-Type Nonvolatile Memories

Abstract: Ferroelectric field effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2) thin films show high potential for future embedded nonvolatile memory applications. However, HfO2 films besides their recently discovered ferroelectric behavior are also prone to undesired charge trapping effects. Therefore, the scope of this paper is to verify the possibility of the charge trapping during standard operation of the HfO2-based FeFET memories. The kinetics of the charge trapping and its interplay with the ferroelectric polarization switching are analyzed in detail using the single-pulse $I_{D}$ – $V_{G}$ technique. Furthermore, the impact of the charge trapping on the important memory characteristics such as retention and endurance is investigated.

Neuromorphic Learning and Recognition With One-Transistor-One-Resistor Synapses and Bistable Metal Oxide RRAM

Abstract: Resistive switching memory (RRAM) has been proposed as an artificial synapse in neuromorphic circuits due to its tunable resistance, low power operation, and scalability. For the development of high-density neuromorphic circuits, it is essential to validate the state-of-the-art bistable RRAM and to introduce small-area building blocks serving as artificial synapses. This paper introduces a new synaptic circuit consisting of a one-transistor/one-resistor structure, where the resistive element is a HfO2 RRAM with bipolar switching. The spike-timing-dependent plasticity is demonstrated in both the deterministic and stochastic regimes of the RRAM. Finally, a fully connected neuromorphic network is simulated showing online unsupervised pattern learning and recognition for various voltages of the POST spike. The results support bistable RRAM for high-performance artificial synapses in neuromorphic circuits.

A Compact Model for Metal–Oxide Resistive Random Access Memory With Experiment Verification

Abstract: A dynamic Verilog-A resistive random access memory (RRAM) compact model, including cycle-to-cycle variation, is developed for circuit/system explorations. The model not only captures dc and ac behavior, but also includes intrinsic random fluctuations and variations. A methodology to systematically calibrate the model parameters with experiments is presented and illustrated with a broad set of experimental data, including multilayer RRAM. The physical meanings of the various model parameters are discussed. An example of applying the RRAM cell model to a ternary content-addressable-memory (TCAM) macro is provided. Tradeoffs on the design of RRAM devices for the TCAM macro are discussed in the context of the energy consumption and worst case latency of the memory array.

Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics

Abstract: We study the effects of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs (NCFETs). Based on this, we propose the concept of conservative design of NCFETs, where any unintentional yet reasonable and simultaneous variation ( $\sim \pm 3$ %) in ferroelectric parameters does not result in the emergence of hysteresis and causes only a reasonable variation in the ON-current (≤5%) and, within these constraints, the enhancement of ON-current due to the addition of the ferroelectric gate oxide, which is is maximized.

A Mini Review of Neuromorphic Architectures and Implementations

Abstract: Neuromorphic architectures are hardware systems that aim to use the principles of neural function for their basis of operation. Their goal is to harness biologically inspired concepts such as weighted connections, activation thresholds, short-and long-term potentiation, and inhibition to solve problems in distributed computation. Compared with today’s methods of emulating neural function in software on conventional von Neumann hardware, neuromorphic systems provide the promise of inherently low power and fault-tolerant operation directly implemented into hardware, for application in distributed and embedded computing tasks, where the vast scaling of today’s architectures does not provide a long-term solution. This mini review is intended for a general engineering audience not currently familiar with this exciting research area. It provides descriptions of some of the recent advances, including supercomputer and single-device implementations, approaches based on spiking and nonspiking neurons, machine learning hardware accelerators, and those utilizing memristive devices. Hardware implementations utilizing both conventional electronic materials and organic electronic materials are reviewed.

Compact Model of Dielectric Breakdown in Spin-Transfer Torque Magnetic Tunnel Junction

Abstract: Spin-transfer torque magnetic tunnel junction (MTJ) is a promising candidate for nonvolatile memories thanks to its high speed, low power, infinite endurance, and easy integration with CMOS circuits. However, a relatively high current flowing through an MTJ is always required by most of the switching mechanisms, which results in a high electric field in the MTJ and a significant self-heating effect. This may lead to the dielectric breakdown of the ultrathin ( $\sim 1$ nm) oxide barrier in the MTJ and cause functional errors of hybrid CMOS/MTJ circuits. This paper analyzes the physical mechanisms of time-dependent dielectric breakdown (TDDB) in an oxide barrier and proposes an SPICE-compact model of the MTJ. The simulation results show great consistency with the experimental measurements. This model can be used to execute a more realistic design according to the constraints obtained from simulation. The users can estimate the lifetime, the operation voltage margin, and the failure probability caused by TDDB in the MTJ-based circuits.

Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance—Part I: Model Description

Abstract: We present an accurate and computationally efficient physics-based compact model to quantitatively analyze negative capacitance FET (NCFET) for real circuit design applications. Our model is based on the Landau–Khalatnikov equation coupled to the standard BSIM6 MOSFET model and implemented in Verilog-A. It includes transient and temperature effects, and accurately captures different aspects of NCFET. A comprehensive quasi-static analysis of NCFET in its different regions of operation is also performed using a simpler loadline approach. We also analyze the impact of ferroelectric and gate oxide thicknesses on the performance gain of NCFET over MOSFET.

A Compact 2-D Analytical Model for Electrical Characteristics of Double-Gate Tunnel Field-Effect Transistors With a SiO 2 /High- $k$ Stacked Gate-Oxide Structure

Abstract: A compact 2-D analytical model for electrical characteristics such as surface potential, drain current, and threshold voltage of double-gate tunnel FET (DG TFETs) with a SiO2/High- ${k}$ stacked gate-oxide structure is proposed in this paper. Poisson’s equation has been solved using parabolic approximation method to model the channel potential. The band-to-band tunneling generation rate has been expressed as a function of channel electric field derived from the channel potential and then integrated analytically over the channel thickness to derive the drain current of the stacked-gate DG TFETs using the shortest tunneling path $(L_{t}^{\min } )$ concept. The effect of source/drain depletion regions has been included for the better accuracy of the proposed model. The maximum transconductance method has finally been used to extract the threshold voltage from the drain current of the device. The effects of various device parameters on the channel potential, drain current, and threshold voltage have been investigated. The model results have been compared with the simulation data obtained using the commercially available ATLAS 2-D device simulator from SILVACO for the validity of the proposed model.

Study and Analysis of the Effects of SiGe Source and Pocket-Doped Channel on Sensing Performance of Dielectrically Modulated Tunnel FET-Based Biosensors

Abstract: Dielectrically modulated tunnel FET (DMTFET)-based biosensors show higher sensitivity but lower subthreshold current compared with their dielectrically modulated FET counterpart. In this context, the effect of use of silicon–germanium (SiGe) source and n+-pocket-doped channel is investigated with the help of extensive device-level simulations. This paper explores the underlying physics of germanium composition variation in the source region, and doping concentration variation in n+-pocket region, from the perspective of biomolecule conjugation. The effects of source bandgap and tunneling length over the band-to-band tunneling component have been analyzed, and, subsequently, the sensing performance of DMTFETs has been estimated. The results show that SiGe-source DMTFET has significant superiority over n+-pocket DMTFET for attaining higher subthreshold current level while retaining acceptable sensitivity. Such sensitivity-current optimization has been studied for different gate and drain biases, and the suitable biasing range of operation has been indicated. In addition, the relative efficiency of SiGe source and n+-pocket-doped channel has been studied under different biomolecule sample specifications. Finally, the influence of trap-assisted tunneling on DMTFET sensing performance has been analyzed, and the comparative role of SiGe source and n+ pocket has also been indicated in this context.

Time-Dependent Failure of GaN-on-Si Power HEMTs With p-GaN Gate

Abstract: This paper reports an experimental demonstration of the time-dependent failure of GaN-on-Si power high-electron-mobility transistors with p-GaN gate, submitted to a forward gate stress. By means of combined dc, optical analysis, and 2-D simulations, we demonstrate the following original results: 1) when submitted to a positive voltage stress (in the range of 7–9 V), the transistors show a time-dependent failure, which leads to a sudden increase in the gate current; 2) the time-to-failure (TTF) is exponentially dependent on the stress voltage and Weibull-distributed; 3) the TTF depends on the initial gate leakage current, i.e., on the initial defectiveness of the devices; 4) during/after stress, the devices show a localized luminescence signal (hot spots); the spectral investigation mainly reveals a peak corresponding to yellow luminescence and a broadband related to bremsstrahlung radiation; and 5) 2-D simulations were carried out to clarify the origin of the degradation process. The results support the hypothesis that the electric field in the AlGaN has a negligible impact on the device failure; on the contrary, the electric field in the SiN and in the p-GaN gate can play an important role in favoring the failure, which is possibly due to a defect generation/percolation process.

Review on Thermionic Energy Converters

Abstract: Thermionic energy converter (TEC) is a heat engine that generates electricity directly using heat as its source of energy and electron as its working fluid. Despite having a huge potential as an efficient direct energy conversion device, the progress in vacuum-based thermionic energy converter development has always been hindered by the space charge problem and the unavailability of materials with low work function. It is only recently that researchers have started to look back into this technology as recent advances in manufacturing technology techniques have made it possible to solve these problems, making TECs a viable option in replacing current energy production systems. The focus of this paper is to review the challenges of producing efficient and practical TECs, along with recent findings and developments in mitigating these challenges. Furthermore, this paper looked into potential applications of TECs, based on recent works and technologies, and found that, with certain improvements, it can be applied in many sectors.

Performance Enhancement of Novel InAs/Si Hetero Double-Gate Tunnel FET Using Gaussian Doping

Abstract: In this paper, for the first time, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications. For this purpose, the suitability of the device for low-power applications is investigated by extracting the threshold voltage of the device using a transconductance change method and a constant current method. Furthermore, the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths. A highly doped layer is placed in the channel near the source–channel junction, and this decreases the width of the depletion region, which improves the ON-current ( ${I_{\rm{\scriptscriptstyle ON}}}$ ) and the RF performance. Furthermore, the circuit-level performance assessment is done by implementing a common source amplifier using the H-DGTFET; a 3-dB roll-off frequency of 230.11 GHz and a unity-gain frequency of 5.4 THz were achieved.

Performance of NUV-HD Silicon Photomultiplier Technology

Abstract: In this paper, we present the full characterization of a new high-density (HD) cell silicon photomultiplier (SiPM) technology for ultraviolet (UV) and blue light detection, named near UV HD SiPM. Thanks to an optimized border region around each cell, we were able to develop devices having a very high detection efficiency and, at the same time, a high dynamic range. We produced SiPMs with a square cell pitch of 15, 20, 25, and 30 $\mu \text{m}$ featuring a peak efficiency in the violet region ranging from 40% to 55%, according to the cell size. We tested this technology for time-of-flight positron emission tomography. Using two $4\times 4$ mm2 SiPMs with a $25 \,\, \times \,\, 25~\mu \text{m}^{2}$ cell pitch coupled to $3\times 3\times 5$ mm3 LYSO scintillators, we reached for the first time 100-ps full-width at half-maximum coincidence time resolution. This result was independent of the temperature in a range from 20 °C to −20 °C. At the same time, thanks to the high dynamic range and low correlated noise, we obtained an energy resolution lower than 9% for 511-keV $\gamma $ -rays.

A SPAD-Based QVGA Image Sensor for Single-Photon Counting and Quanta Imaging

Abstract: A CMOS single-photon avalanche diode (SPAD)-based quarter video graphics array image sensor with 8- $\mu \text{m}$ pixel pitch and 26.8% fill factor (FF) is presented. The combination of analog pixel electronics and scalable shared-well SPAD devices facilitates high-resolution, high-FF SPAD imaging arrays exhibiting photon shot-noise-limited statistics. The SPAD has 47 counts/s dark count rate at 1.5 V excess bias (EB), 39.5% photon detection probability (PDP) at 480 nm, and a minimum of 1.1 ns dead time at 1 V EB. Analog single-photon counting imaging is demonstrated with maximum 14.2-mV/SPAD event sensitivity and 0.06e− minimum equivalent read noise. Binary quanta image sensor (QIS) 16-kframes/s real-time oversampling is shown, verifying single-photon QIS theory with $4.6\times $ overexposure latitude and 0.168e− read noise.

Negative Capacitance Behavior in a Leaky Ferroelectric

Abstract: We present a simulation study of the negative capacitance effect incorporating leakage through the ferroelectric (FE) negative capacitor. The dynamics of the FE is modeled using the Landau–Khalatnikov equation. When an FE and a dielectric are simply connected in series without a metal contact between them, the stabilization of negative capacitance remains unchanged irrespective of leakage. However, when a metal is used, any finite leakage through the FE makes it impossible to stabilize negative capacitance at the steady state. Nonetheless, when a voltage is applied, the series configuration enters the negative capacitance state and as long as the gate voltage is cycled faster than the time needed by the leakage current to discharge all the capacitors, the transistor shows improved subthreshold swing. These results are expected to provide insight into understanding and analyzing recent experimental results on negative capacitance.

Probabilistic Deep Spiking Neural Systems Enabled by Magnetic Tunnel Junction

Abstract: Deep spiking neural networks are becoming increasingly powerful tools for cognitive computing platforms. However, most of the existing studies on such computing models are developed with limited insights on the underlying hardware implementation, resulting in area and power expensive designs. Although several neuromimetic devices emulating neural operations have been proposed recently, their functionality has been limited to very simple neural models that may prove to be inefficient at complex recognition tasks. In this paper, we venture into the relatively unexplored area of utilizing the inherent device stochasticity of such neuromimetic devices to model complex neural functionalities in a probabilistic framework in the time domain. We consider the implementation of a deep spiking neural network capable of performing high-accuracy and low-latency classification tasks, where the neural computing unit is enabled by the stochastic switching behavior of a magnetic tunnel junction. The simulation studies indicate an energy improvement of $20 \times $ over a baseline CMOS design in 45-nm technology.

2-D Analytical Modeling of Threshold Voltage for Graded-Channel Dual-Material Double-Gate MOSFETs

Abstract: A 2-D analytical model for the surface potential and threshold voltage of graded-channel dual-material double-gate (GCDMDG) MOSFETs obtained by intermixing the concepts of graded doping in channel and dual material in gate engineering has been proposed. The parabolic approximation method has been explored for determining the potential distribution function of the device by solving Poisson’s equation with suitable boundary conditions. The threshold voltage roll-off, drain-induced barrier lowering and lateral electric field have also been examined. The effects of different device parameters on device performance have been evaluated to check its figure-of-merit over the graded-channel double-gate (GCDG) and dual-material double-gate (DMDG) structures. For validation of the proposed model, the results have been compared with the numerical simulation data obtained by ATLAS™, a 2-D device simulator from SILVACO.

Drain Work Function Engineered Doping-Less Charge Plasma TFET for Ambipolar Suppression and RF Performance Improvement: A Proposal, Design, and Investigation

Abstract: A novel device configuration is presented for doping-less charge plasma tunnel FET (TFET) for suppression of ambipolar nature with improved high-frequency figures of merit. For this, the drain electrode, which is used to induce n+ drain region, is separated into two sections of high and low work functions. The work function of the drain electrode section near to channel is considered relatively higher than other part for restricting the tunneling of holes at drain/channel interface for negative gate bias. This concept creates asymmetrical charge carrier concentration in the drain region, which increases the tunneling width at the drain/channel interface. Therefore, the proposed device offers better performance in terms of ambipolar current, parasitic capacitance, and RF parameters. In this regard, a comparative study of the proposed device is performed with conventional and dual-metal gate doping-less TFETs. Furthermore, the optimization of the length and higher work function of the drain electrode near to channel is discussed in detail for the proposed device. Apart from above-mentioned advantages, the doping-less nature of the proposed device provides fabrication simplicity and immunity against random dopant fluctuations in comparison with the physically doped TFET.

Physical Unbiased Generation of Random Numbers With Coupled Resistive Switching Devices

Abstract: The resistive-switching memory (RRAM) is currently under consideration for fast nonvolatile memory thanks to its relatively low cost and high performance. A key concern for RRAM reliability is stochastic switching, which impacts the operation of the digital memory due to distribution broadening. On the other hand, stochastic behaviors are enabling mechanisms for some computing tasks, such as physical unclonable function (PUF) and random number generation (RNG). Here, we present new circuit blocks for physical RNG, based on the coupling of two RRAM devices. The two-resistance scheme allows to overcome the need of probability tracking, where the operation voltage must be tuned to adjust the generation probabilities of 0 and 1. Probability tests are proved successful for one of the three proposed schemes.

Vertical GaN Power Diodes With a Bilayer Edge Termination

Abstract: Vertical GaN power diodes with a bilayer edge termination (ET) are demonstrated. The GaN p-n junction is formed on a low threading dislocation defect density ( $10^{4}-10^{5}$ cm $^{-2}$ ) GaN substrate, and has a 15- $\mu \text{m}$ -thick n-type drift layer with a free carrier concentration of $5\times 10^{15}$ cm $^{-3}$ . The ET structure is formed by $N$ implantation into the p+-GaN epilayer just outside the p-type contact to create compensating defects. The implant defect profile may be approximated by a bilayer structure consisting of a fully compensated layer near the surface, followed by a 90% compensated (p) layer near the n-type drift region. These devices exhibit avalanche breakdown as high as 2.6 kV at room temperature. Simulations show that the ET created by implantation is an effective way to laterally distribute the electric field over a large area. This increases the voltage at which impact ionization occurs and leads to the observed higher breakdown voltages.

Studies on High-Voltage GaN-on-Si MIS-HEMTs Using LPCVD Si 3 N 4 as Gate Dielectric and Passivation Layer

Abstract: This paper investigates the performance of AlGaN/gallium nitride (GaN) MIS high electron mobility transistors (MIS-HEMTs). The gate dielectric layer and the surface passivation layer are formed by the low-pressure chemical vapor deposition (LPCVD) Si3N4. The LPCVD-Si3N4 MIS-HEMTs exhibit a high breakdown voltage (BV) of 1162 V at $I_{\mathrm{ DS}}= 1~\mu \text{A}$ /mm, a low OFF-state leakage of $7.7 \times 10^{-12}$ A/mm, and an excellent ON/OFF-current ratio of $\sim 10^{11}$ . Compared with the static ON-resistance of 2.88 $\text{m}\Omega \cdot \textrm {cm}^{2}$ , the dynamic ON-resistance after high OFF-state drain bias stress at 600 V only increases to 4.89 $\text{m}\Omega \cdot \textrm {cm}^{2}$ . The power device figure of ${\mathrm{ merit}} = \textrm {BV}^{{\vphantom {R^{l}}{2}}}/R_{{{\mathrm{\scriptscriptstyle ON}.{\mathrm{ sp}}}}}$ is calculated to be 469 $\textrm {MW}\cdot \textrm {cm}^{-2}$ . The LPCVD-Si3N4/GaN interface state density is in the range of (1.4–5.3) $\times 10^{{\vphantom {R^{l}}{13}}}$ eV $^{-1}$ cm $^{-2}$ extracted by the conventional conductance method. Finally, the gate insulator degradation of GaN-based MIS-HEMTs is analyzed by time-dependent dielectric breakdown test. The lifetime is extrapolated to 0.01% of failures after ten years at 300 K by fitting the data with a power law to a gate voltage of 10.1 V.

Nano-CNC Machining of Sub-THz Vacuum Electron Devices

Abstract: Nano-computer numerical control (CNC) machining technology is employed for the fabrication of sub-THz (100–1000 GHz) vacuum electron devices. Submicron feature tolerances and placement accuracy have been achieved and surface roughness of a few tens of nanometers has been demonstrated providing high-quality radio frequency (RF) transmission and reflection parameters on the tested circuit structures. Details of the manufacturing approach are reported for the following devices: W-band sheet beam (SB) klystron, two designs of a 220-GHz SB double-staggered grating traveling wave tube (TWT), 263-GHz SB TWT amplifier for an electron paramagnetic resonance spectrometer, 346-GHz SB backward wave oscillator for fusion plasma diagnostics, 346-GHz pencil beam backward wave oscillator, and 270-GHz pencil beam folded waveguide TWT self-driving amplifier. Application of the nano-CNC machining to nanocomposite scandate tungsten cathodes as well as to passive RF components is also discussed.

X-Ray Detector-on-Plastic With High Sensitivity Using Low Cost, Solution-Processed Organic Photodiodes

Abstract: We made and characterized an X-ray detector on a 25- $\mu \text{m}$ -thick plastic substrate that is capable of medical-grade performance. As an indirect conversion flat panel detector, it combined a standard scintillator with an organic photodetector (OPD) layer and oxide thin-film transistor backplane. Using solution-processed organic bulk heterojunction photodiode rather than the usual amorphous silicon, process temperature is reduced to be compatible with plastic film substrates, and a number of costly lithography steps are eliminated, opening the door to lower production costs. With dark currents as low as 1 pA/mm $^{2}$ and sensitivity of 0.2 A/W the OPD also meets functional requirements: the proof-of-concept detector delivers high-resolution, dynamic images at 10 frames/s, and 200 pixels/in using X-ray doses as low as $3~\mu $ Gy/frame.

HfO 2 -Based RRAM: Electrode Effects, Ti/HfO 2 Interface, Charge Injection, and Oxygen (O) Defects Diffusion Through Experiment and Ab Initio Calculations

Abstract: We investigate in detail the effects of metal electrodes on the switching performance and conductive filament (CF) stability of HfO2-based RRAM. The current–voltage characteristics of the devices exhibit different electrode-dependent RESET profiles which we attempt to clarify. With the insight from the experimental data, we employ first-principles calculations to have a better microscopic understanding of the devices. We study the charge injection, formation of Frenkel pairs, and diffusion of oxygen defects (oxygen vacancies $V_{o}$ and oxygen interstitials O i ) that are important in the CF creation and stability during the device operation. Since the presence of Ti in RRAM has been associated with the creation of substoichiometric TiO y region at the Ti/HfO2 interface, we also explore different Ti and Hf suboxides to understand the possible composition of that interface. Our calculations suggest that the composition of the interface would be Ti2O/Hf2O3 from thermodynamic perspective. By combining the experimental and calculations results, we show that the concentration of oxygen interstitial (O i ) ions in the oxide after CF formation is larger for RRAM devices with inert electrodes (like Pt) compared with O reactive electrodes (like Ti) which results in degraded device performance. The lower O i concentration in HfO2 layer with Ti electrodes results in improved CF thermal stability and device variability.

Armchair Graphene Nanoribbon Resonant Tunneling Diodes Using Antidote and BN Doping

Abstract: Band gap size of armchair graphene nanoribbons (AGNRs) can be tuned by implementing topological antidotes or boron/nitride (BN) atoms at the middle of ribbons. By imposing such modulated patterns on certain regions of AGNRs, double barrier quantum well structures can be produced. According to this procedure, this paper proposes a new method for constructing resonant tunneling diodes (RTDs) by using AGNRs while the widths of the ribbons remain constant. Different structures of modulated AGNR-RTDs are constructed by introducing hexagonal antidotes, hexagonal BN doping atoms, and the combination of antidotes and BN doping atoms at the middle of pristine AGNRs. It is found that in general, antidote AGNR-RTDs present negative differential resistance with better performance in comparison with other modulated AGNR-RTDs. In addition, the effects of dimensional parameters such as the length of channel, the length of barrier, and the distance between antidotes on the performance of antidote AGNR-RTDs are investigated. It is extracted that the peak to valley ratio, power dissipation, and other properties can be modified by tuning the dimensional parameters to appropriate values. Numerical tight-binding model along with nonequilibrium Green’s function formalism is applied to study the electronic properties of devices.

Normally OFF GaN-on-Si MIS-HEMTs Fabricated With LPCVD-SiN x Passivation and High-Temperature Gate Recess

Abstract: Low-current-collapse normally OFF GaN-on-Si MIS high-electron-mobility transistors (MIS-HEMTs) are fabricated with low-pressure chemical-vapor-deposited SiN x (LPCVD-SiN x ) passivation and high-temperature low-damage gate-recess technique. The high-thermal-stability LPCVD-SiN x enables a passivation-prior-to-ohmic process strategy and effectively suppresses deep states at the passivation/HEMT interface. The fabricated MIS-HEMTs feature a high $V_{\rm {TH}} $ of +0.85 V at the drain current of 1 $\mu $ A/mm and a remarkable ON/OFF current ratio of 1010 while reduced dynamic ON-resistance as compared to plasma-enhanced chemical-vapor-deposited SiO2 passivation. High field-effect channel mobility of 180 cm $^{2}/ \text{V} \cdot \text{s} $ is achieved, leading to a high maximum drain current density of 663 mA/mm.

Impact of Wire Geometry on Interconnect RC and Circuit Delay

Abstract: We investigate the impact of wire geometry on the resistance, capacitance, and RC delay of Cu/low- $k$ damascene interconnects for fixed line-to-line pitch. The resistance is computed by applying a semiempirical resistivity model, calibrated to Cu damascene wires, integrated with a Ru-based liner, currently investigated for the 7 nm logic technology node. The capacitance is simulated by means of a 2D field solver (Raphael) by Synopsys. The impact of line dimensions is analyzed for the case of 32 nm pitch interconnects, which are representative of the 7 nm logic technology node. We show that for aspect ratios greater than 1, the resistance is more sensitive to variations of the line width rather than of the line height, because of the higher surface scattering induced by the sidewall interfaces, which are closer to each other compared with the top and bottom interfaces. For capacitance, low- $k$ sidewall damage exacerbates capacitance sensitivity to line dimensions and, for typical interconnect schemes, the impact of line width variations dominates over variations of the line height. We demonstrate that for a given pitch and dielectric stack height, the RC delay can be significantly reduced by targeting wider and deeper damascene trenches, that is, by trading capacitance for resistance, and that an optimal wire geometry for RC delay minimization exists. In addition, we show that a given RC delay can be achieved with several geometries and, therefore, $R$ and $C$ pairs, which represents a useful degree of freedom for designers to optimize system-level performance. As an application, we analyze a possible 7 nm technology scenario and show that wide and deep damascene trenches can mitigate the impact of the increased wire resistance on circuit delay.

Trap Assisted Tunneling and Its Effect on Subthreshold Swing of Tunnel FETs

Abstract: We provide a detailed study of the oxide–semiconductor interface trap assisted tunneling (TAT) mechanism in tunnel FETs to show how it contributes a major leakage current path before the band-to-band tunneling (BTBT) is initiated. With a modified Shockley–Read–Hall formalism, we show that at room temperature, the phonon assisted TAT current always dominates and obscures the steep turn ON of the BTBT current for common densities of traps. Our results are applicable to top gate, double gate, and gate-all-around structures, where the traps are positioned between the source-channel tunneling regions. Since the TAT has strong dependence on electric field, any effort to increase the BTBT current by enhancing local electric field also increases the leakage current. Unless the BTBT current can be increased separately, calculations show that the trap density $D_{\mathrm {it}}$ has to be decreased by 40–100 times compared with the state of the art in order for the steep turn ON (for III–V materials) to be clearly observable at room temperature. We find that the combination of the intrinsic sharpness of the band edges (Urbach tail) and the surface trap density determines the subthreshold swing.

Insight into Lateral Band-to-Band-Tunneling in Nanowire Junctionless FETs

Abstract: In this paper, we investigate the nature of lateral band-to-band-tunneling (L-BTBT) component of gate-induced drain leakage (GIDL) in different nanowire junctionless FET (NWJLFET) configurations for the first time. Although the NW junctionless accumulation mode (JAM) FET has a larger ON-state current compared with the NWJLFETs, we demonstrate that the L-BTBT GIDL is larger in the NWJAMFET compared with the NWJLFET. Furthermore, we explore for the first time the application of a dual-material gate (DMG) in the NWJAMFET to suppress the L-BTBT GIDL. Using calibrated 3-D simulations, we show that the OFF-state current in the DMG NWJAMFET is reduced significantly by six orders of magnitude leading to a considerable ON-state to OFF-state current ratio ( $I/I_{{\mathrm{\scriptscriptstyle OFF}}})$ of $\sim 10^{10}$ . Furthermore, the DMG NWJAMFET offers: 1) an enhanced ON-state current and 2) a significantly reduced OFF-state current compared with the NWJLFETs. Furthermore, we also demonstrate that the DMG NWJAMFET exhibits a higher transconductance than the single material gate NWJAMFET in the saturation region. In addition, we also show that there is a tradeoff between the off-state current and the intrinsic delay and the cut-off frequency in the DMG NWJAMFET. Therefore, we provide the design guidelines for appropriately choosing the work functions of the dual gates and the ratio of the length of the dual gates to the total gate length.