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Showing papers in "IEEE Transactions on Electron Devices in 2017"


Journal ArticleDOI
TL;DR: Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented and the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated.
Abstract: In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use.

922 citations


Journal ArticleDOI
TL;DR: The history of phase-transforming chalcogenides leading up to the current understanding of PCM as either a storage-type SCM, with high-density and better than NAND flash endurance, write speeds, and retention, or a memory-types memory, with fast read/write times to function as a nonvolatile DRAM.
Abstract: Phase-change memory (PCM) has undergone significant academic and industrial research in the last 15 years After much development, it is now poised to enter the market as a storage-class memory (SCM), with performance and cost between that of NAND flash and DRAM In this paper, we review the history of phase-transforming chalcogenides leading up to our current understanding of PCM as either a storage-type SCM, with high-density and better than NAND flash endurance, write speeds, and retention, or a memory-type SCM, with fast read/write times to function as a nonvolatile DRAM Several of the key findings from the community relating to device dimensional scaling, cell design, thermal engineering, material exploration, and storing multiple levels per cell will be discussed These areas have dramatically impacted the course of development and understanding of PCM We will highlight the performance gains attained and the future prospects, which will help drive PCM to be as ubiquitous as NAND flash in the upcoming decade

272 citations


Journal ArticleDOI
TL;DR: The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations.
Abstract: Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs).

244 citations


Journal ArticleDOI
TL;DR: This paper provides a comprehensive review of the current status of OTFT technologies ranging from material, device, process, and integration, to design and system applications, and clarifies the real challenges behind to be addressed.
Abstract: Attributed to its advantages of super mechanical flexibility, very low-temperature processing, and compatibility with low cost and high throughput manufacturing, organic thin-film transistor (OTFT) technology is able to bring electrical, mechanical, and industrial benefits to a wide range of new applications by activating nonflat surfaces with flexible displays, sensors, and other electronic functions. Despite both strong application demand and these significant technological advances, there is still a gap to be filled for OTFT technology to be widely commercially adopted. This paper provides a comprehensive review of the current status of OTFT technologies ranging from material, device, process, and integration, to design and system applications, and clarifies the real challenges behind to be addressed.

204 citations


Journal ArticleDOI
TL;DR: An overview on the history of the development of insulated gate bipolar transistors (IGBTs) as one key component in today's power electronic systems is given; the state-of-the-art device concepts are explained as well as an detailed outlook about ongoing and foreseeable development steps is shown as discussed by the authors.
Abstract: An overview on the history of the development of insulated gate bipolar transistors (IGBTs) as one key component in today’s power electronic systems is given; the state-of-the-art device concepts are explained as well as an detailed outlook about ongoing and foreseeable development steps is shown. All these measures will result on the one hand in ongoing power density and efficiency increase as important contributors for worldwide energy saving and environmental protection efforts. On the other hand, the exciting competition of more maturing Si IGBT technology with the wide bandgap successors of GaN and SiC switches will go on.

201 citations


Journal ArticleDOI
TL;DR: In this paper, the historical and technological development of the ubiquitous trench power MOSFET (or vertical trench VDMOS) is described, and the recent adaptation of trench gates in wide bandgap unipolar devices is also described.
Abstract: The historical and technological development of the ubiquitous trench power MOSFET (or vertical trench VDMOS) is described. Overcoming the deficiencies of VMOS and planar VDMOS, trench VDMOS innovations include pioneering efforts in reactive ion etching and oxidation of the silicon trench gate, polysilicon fill and recessed etchback, unit cell and distributed voltage clamping to protect the trench gate, and scaling active cells to high densities using deep submicron fabrication. Thereafter, gate–drain engineered trench VDMOS improved high-frequency switching capability with lower gate charge utilizing nonuniform gate oxides, field shaping, and charge balancing (superjunction, RSO) methods. The recent adaptation of trench gates in wide bandgap unipolar devices is also described.

174 citations


Journal ArticleDOI
TL;DR: In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFET and nanowire transistors for sub-7-nm node.
Abstract: In this paper, lateral gate-all-around nano-sheet transistors (NSH-FETs) are explored from intrinsic performance to dc and ring oscillator (RO) benchmark compared with FinFETs and nanowire transistors (NW-FETs) for sub-7-nm node. The band structure calculated technology computer aided design results show comparable intrinsic performance to FinFETs at same channel cross section. On top of that, dc and RO are evaluated by taking into account electrostatics, parasitic components, and layout configurations. The NSH-FETs show an advantage in drive current with the NSH width but their RO performance is limited by the device capacitance. The multiple narrow NSH-FET shows ~5% higher drive current compared to the NW-FET at similar subthreshold swing, allowing heavier capacitive loaded circuit. In addition, NSH-FETs can provide the device design freedom from aggressive fin pitch scaling.

173 citations


Journal ArticleDOI
TL;DR: In this article, a review of recent developments in structure designs for highly durable flexible OLEDs, ranging from alternative transparent electrodes to thin-film encapsulation layers, in which solution concepts for the existing critical issues of flexible OLED displays are addressed.
Abstract: Organic light-emitting diodes (OLEDs) are remarkably promising display devices that can function in mechanically flexible configurations on a plastic substrate due to various compelling properties, including organic constituents, ultrathin and simple structure, and low-temperature fabrication. In spite of successful demonstrations of flexible OLEDs, some technical issues of containing relatively thick transparent electrodes made of ceramic materials and an unstable flexible encapsulation system have impeded reaching high levels of reliability and durability toward full commercialization. This review covers recent developments in structure designs for highly durable flexible OLEDs, ranging from alternative transparent electrodes to thin-film encapsulation layers, in which solution concepts for the existing critical issues of flexible OLEDs are addressed. Emerging unusual substrates and their application strategies are additionally introduced to find intimations of future display technologies and hence to disclose nonclassic flexible OLEDs.

172 citations


Journal ArticleDOI
TL;DR: The integrated crosspoint memristors are optimized for analog computing applications allowing successful forming and switching of all 200 devices in the demonstrated crossbar circuit, and, most importantly, precise tuning of the devices' conductance values within the dynamic range of operation.
Abstract: We report a monolithically integrated 3-D metal-oxide memristor crossbar circuit suitable for analog, and in particular, neuromorphic computing applications. The demonstrated crossbar is based on Pt/Al2O3/TiO2– x /TiN/Pt memristors and consists of a stack of two passive $10\times10$ crossbars with shared middle electrodes. The fabrication process has a low, less than 175 °C, temperature budget and includes a planarization step performed before the deposition of the second crossbar layer. These features greatly improve yield and uniformity of the crosspoint devices and allows for utilizing such a fabrication process for integration with CMOS circuits as well as for stacking of multiple crossbar layers. Furthermore, the integrated crosspoint memristors are optimized for analog computing applications allowing successful forming and switching of all 200 devices in the demonstrated crossbar circuit, and, most importantly, precise tuning of the devices’ conductance values within the dynamic range of operation. We believe that the demonstrated work is an important milestone toward the implementation of analog artificial neural networks, specifically, those based on 3-D CMOL circuits.

168 citations


Journal ArticleDOI
TL;DR: In this paper, a physics-based 2D analytical model for surface potential, electric field, drain current, subthreshold swing (SS) and threshold voltage of dual-material (DM) double-gate tunnel FETs with SiO2/HfO2 stacked gate-oxide structure has been developed.
Abstract: A physics-based 2-D analytical model for surface potential, electric field, drain current, subthreshold swing (SS) and threshold voltage of dual-material (DM) double-gate tunnel FETs (DG TFETs) with SiO2/HfO2 stacked gate-oxide structure has been developed in this paper. The parabolic-approximationtechnique, with suitable boundary conditions, has been used to solve Poisson’s equation in the channel region. Channel potential model is used to develop electric field expression. The drain current expression is extracted by analytically integrating the band-to-band tunneling generation rate over the channel thickness. Threshold voltage has been extracted by maximum transconductance method. The proposed model also demonstrates that the proper choice of work function for both the latterly contacting gate electrode (near the source and drain) materials which can give better results in terms of input-output characteristics, SS, and ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ than the conventional TFET devices. Although the proposed model has been primarily developed for Si-channel-based DM DG TFET devices, however, the model has also been shown to be applicable for other materials like SiGe (indirect bandgap) and InAs channel-based TFET structures. The results of the proposed model have been validated against the TCAD simulation results obtained by using SILVACO ATLAS device simulation software.

145 citations


Journal ArticleDOI
TL;DR: In this article, the authors identify the causes of dynamic dispersion using substrate bias ramps to isolate the leakage paths and trapping locations in the epitaxy and simulation to identify their impact on the device characteristics.
Abstract: GaN-on-Si power switching transistors that use carbon-doped epitaxy are highly vulnerable to dynamic $\text{R}_{ON}$ dispersion, leading to reduced switching efficiency. In this paper, we identify the causes of this dispersion using substrate bias ramps to isolate the leakage paths and trapping locations in the epitaxy and simulation to identify their impact on the device characteristics. It is shown that leakage can occur both vertically and laterally, and we suggest that this is associated not only with bulk transport, but also with extended defects as well as hole gases at heterojunctions. For exactly the same epitaxial design, it is shown using a “leaky dielectric” model that depending on the leakage paths, dynamic $\text{R}_{ON}$ dispersion can vary between insignificant and infinite. An optimum leakage configuration is identified to minimize dispersion requiring a resistivity which increases with depth in the buffer stack. It is demonstrated that leakage through the undoped GaN channel is required over the entire gate to drain gap, and not just under the contacts, in order to fully suppress dispersion.

Journal ArticleDOI
TL;DR: In this article, a charge-plasma concept is introduced for the first time to implement a dielectric-modulated junctionless tunnel field effect transistor (DM-JLTFET) for biosensor label-free detection.
Abstract: To reduce the fabrication complexity and cost of the nanoscale devices, a charge-plasma concept is introduced for the first time to implement a dielectric-modulated junctionless tunnel field-effect transistor (DM-JLTFET) for biosensor label-free detection. The formation of p+ source and n+ drain regions in DM-JLTFET is done by the deposition of platinum (work function = 5.93 eV) and hafnium (work function = 3.9 eV) materials, respectively, over the silicon body. Furthermore, a nanogap cavity embedded within the gate dielectric is created by etching the portion of gate oxide layer toward the source end for sensing biomolecules. For this, the sensing capability of DM-JLTFET has been investigated in terms of variation in dielectric constant, charge density, length, and thickness of the cavity at different bias conditions. Finally, a comparative study between DM-JLTFET and MOSFET biosensor is investigated. The implementation of proposed device and all the simulations have been performed by using ATLAS device simulator.

Journal ArticleDOI
TL;DR: In this article, the authors report on hot test measurements of a wide-bandwidth, 220-GHz sheet beam traveling wave tube amplifier developed under the Defense advanced research projects agency (DARPA) HiFIVE program.
Abstract: We report on hot test measurements of a wide-bandwidth, 220-GHz sheet beam traveling wave tube amplifier developed under the Defense advanced research projects agency (DARPA) HiFIVE program. Nano-computer numerical control (CNC) milling techniques were employed for the precision fabrication of double vane, half-period staggered interaction structures achieving submicrometer tolerances and nanoscale surface roughness. A multilayer diffusion bonding technique was implemented to complete the structure demonstrating wide bandwidth (>50 GHz) with an insertion loss of about −5 dB achieved during transmission measurements of the circuit. The sheet beam electron gun utilized nanocomposite scandate tungsten cathodes that provided over 438-A/cm2 current density in the 12.5:1 ratio sheet beam. An InP HBT-based monolithic microwave integrated circuit preamplifier was employed for TWT gain measurements in the stable amplifier operation region. In the wide-bandwidth operation mode (for gun voltage of 20.9 kV), a gain of over 24 dB was measured over the frequency range of 207–221 GHz. In the high-gain operation mode (for gun voltage of 21.8 kV), over 30 dB of gain was measured over the frequency range of 197–202 GHz. High-power tests were conducted employing an extended interaction klystron.

Journal ArticleDOI
TL;DR: In this article, a vertical dielectrically modulated tunnel field effect transistor (V-DMTFET) was used as a label-free biosensor for the first time and compared with lateral DMTFET using underlap concept and gate work function engineering.
Abstract: A vertical dielectrically modulated tunnel field-effect transistor (V-DMTFET) as a label-free biosensor has been investigated in this paper for the first time and compared with lateral DMTFET (L-DMTFET) using underlap concept and gate work function engineering. To improve the performance of lateral biosensor (LB), a heavily doped front gate ${n}^{+}$ -pocket and gate-to-source overlap is introduced in the vertical biosensor (VB). The integrated effect of lateral tunneling as well as vertical tunneling in VB leads to enhanced ON-state current and decrease the subthreshold swing. To evaluate sensing ability of these devices, charged and charged neutral biomolecules are immobilized in nanogap cavity independently. A deep analysis has been performed to show the effect of variation in dielectric constant ( $k$ ), charge density ( $\rho $ ), ${x}$ -composition of Ge, % volume filling of ${t}_{\textsf {cavity}}$ , length and thickness of a ${n}^{+}$ -pocket and sensitivity of electrical parameters is also incorporated. Dual-pocket (front and back gate pocket) VB is studied and compared with the LB and VB in the tabular form. Noise characteristic of dielectrically modulated field-effect transistor, L-DMTFET, and V-DMTFET is also evaluated.

Journal ArticleDOI
TL;DR: In this article, the performance and potential of GaAs and of wide and extreme bandgap semiconductors (SiC, GaN, Ga2O3, and diamond), relative to silicon, for power electronics applications are evaluated and compared.
Abstract: We evaluate and compare the performance and potential of GaAs and of wide and extreme bandgap semiconductors (SiC, GaN, Ga2O3, and diamond), relative to silicon, for power electronics applications. We examine their device structures and associated materials/process technologies and selectively review the recent experimental demonstrations of high voltage power devices and IC structures of these semiconductors. We discuss the technical obstacles that still need to be addressed and overcome before large-scale commercialization commences.

Journal ArticleDOI
TL;DR: In this paper, the role of metal and semiconductor workfunctions, energy bandgap, and applied electric field and the interplay between them for the induced ED is discussed, and the effect of interface traps on the induced charge is also addressed.
Abstract: To overcome the limitations of chemical doping in nanometer-scale semiconductor devices, electrostatic doping (ED) is emerging as a broadly investigated alternative to provide regions with a high electron or hole density in a semiconductor device. In this paper, we review various reported ED approaches and related device architectures in different material systems. We highlight the role of metal and semiconductor workfunctions, energy bandgap, and applied electric field and the interplay between them for the induced ED. The effect of interface traps on the induced charge is also addressed. In addition, we discuss the performance benefits of ED devices and the major roadblocks of these approaches for potential future CMOS technology.

Journal ArticleDOI
TL;DR: A novel design of DL TFET is proposed, wherein a metallic layer has been placed in the oxide region at the space present between gate and source electrode of conventional dopingless n-TFET to overcome the issue of low on-state current.
Abstract: Formation of abrupt tunneling junction for the sub-nanometer tunnel FET (TFET) is crucial for achieving better electrical behavior. This task is more challenging in the case of dopingless TFETs (DL TFETs). In this concern, we propose a novel design of DL TFET, wherein a metallic layer has been placed in the oxide region at the space present between gate and source electrode (used for inducing p+ region) of conventional dopingless n-TFET to overcome the issue of low on-state current ( $\text{I}_{\mathrm{on}}$ ) due to presence of tunneling barrier. Proposed modification is helpful for achieving steeper tunneling junction at the source/channel interface, which enables higher tunneling generation rate of charge carriers at this interface. The optimization for work function of the metal layer (ML) has been performed for improving $\text {I}_{\mathrm{on}}$ , point subthreshold swing and threshold voltage ( $\text {V}_{\text {th}}$ ). Finally, the impact of the ML misalignment from the gate/source terminal and optimization of its length is also presented.

Journal ArticleDOI
TL;DR: In this paper, a Z-shaped (ZS)-TFET was proposed to suppress the ambipolar behavior and improve RF performance in tunnel field effect transistors (TFETs), and the proposed ZS-TFET is more scalable than other vertical band-to-band-based TFETs.
Abstract: To suppress the ambipolar behavior and improve RF performance in tunnel field-effect transistors (TFETs), a Z-shaped (ZS)-TFET is proposed. The proposed ZS-TFET is more scalable than other vertical band-to-band-based TFETs and provides higher ON-state current ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}$ ), larger ON/OFF current ratio ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}/{I} _{ {\mathrm{\scriptscriptstyle OFF}}}$ ) and lower subthreshold swing compared to conventional TFETs. These advantages stem from the tunneling junction in the ZS-TFET being perpendicular to the channel direction, which facilitates the formation of a relatively large tunneling junction area. The ZS body makes use of both vertical and horizontal fields while suppressing the lateral parasitic tunneling current. In addition, by using a ZS gate in the proposed device, the energy band diagram near the source is modulated to create an N+ source pocket which creates a downward band bending of the potential, similar to PNPN-like structures. Finally, the proposed structure significantly improves the analog/RF figure-of-merit.

Journal ArticleDOI
TL;DR: In this paper, the development of application specific VDMOS and lateral trench power MOSFETs is described, which include all implant quasi-vertical, lateral trench, and charge balanced devices.
Abstract: The technological development of application specific VDMOS and lateral trench power MOSFETs is described. Unlike general-purpose trench vertical DMOS, application specific trench DMOS comprise devices merged or optimized for a specific function or characteristic. Examples include the bidirectional lithium ion battery disconnect switch, the airbag squib driver with safety redundancy, the antilock breaking systems solenoid driver with repeated avalanche operation, and various forms of synchronous rectifiers (including integrated Schottky and pseudo-Schottky operation). Trench lateral DMOS include all implant quasi-vertical, lateral trench, and lateral trench charge balanced devices. Trench power MOSFET packaging addresses multichip surface mount, DrMOS, low inductance, and clip lead packages.

Journal ArticleDOI
TL;DR: The tunneling width at the channel-drain interface and the source-to-channel barrier height are considerably increased in the NT JLFET due to the presence of the core gate, leading to a significantly high on-state to off-state current ratio of ~107 even for a channel length of 7 nm.
Abstract: In this paper, we propose a nanotube (NT) JLFET for significantly improved performance in the sub-10-nm regime. We show that the tunneling width at the channel-drain interface and the source-to-channel barrier height are considerably increased in the NT JLFET due to the presence of the core gate. Therefore, the lateral band-to-band-tunneling-induced parasitic bipolar junction transistor action is diminished in the off-state of NT JLFET, leading to a significantly high on-state to off-state current ratio of ~107 even for a channel length of 7 nm. Furthermore, we demonstrate that the spacer length and dielectric constant and the core gate diameter can be used as design parameters to further improve the performance of the NT JLFETs. Therefore, we also provide the necessary design guidelines for NT JLFETs.

Journal ArticleDOI
TL;DR: CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.
Abstract: State-of-the-art silicon interposer technology of chip-on-wafer-on-substrate (CoWoS) containing the second-generation high bandwidth memory (HBM) has been applied for the first time in fabricating high-performance wafer-level system-in-package. An ultralarge Si interposer up to 1200mm2 made by a two-mask stitching process is used to form the basis of the second-generation CoWoS (CoWoS-2) to accommodate chips of logic and memory and achieve the highest possible performance. Yield challenges associated with the high warpage of such a large heterogeneous system are resolved to achieve high package yield. Compared to alternative interposer integration approaches such as chip-on-substrate, CoWoS offers more competitive design rule which results in better power consumption, transmission loss, and eye diagram. CoWoS-2 has positioned itself as a flexible 3-D IC platform for logic-memory heterogeneous integration between logic system-on-chip and HBM for various high-performance computing applications.

Journal ArticleDOI
TL;DR: In this article, a physics-based compact model for a ferroelectric negative capacitance FET with a metal-ferroelectric-insulator-semiconductor (MFIS) structure is presented.
Abstract: We present a physics-based compact model for a ferroelectric negative capacitance FET (NCFET) with a metal–ferroelectric–insulator–semiconductor (MFIS) structure. The model is computationally efficient, and it accurately calculates the gate charge density as a function of the applied voltages. For the first time, an explicit expression for the channel current in bulk NCFET is also deduced taking into account the spatial variation of ferroelectric polarization in the longitudinal direction. Using current continuity condition in the channel, we find that different regions of the ferroelectric may operate in a positive or a negative capacitance state depending on the external biases. The model captures the impact of ferroelectric thickness scaling and variation in the ferroelectric material parameters, and has been validated against the implicit approach involving full numerical computations as well as experimental data. We also compare the device characteristics of the MFIS structure with those of the metal–ferroelectric–metal–insulator–semiconductor structure.

Journal ArticleDOI
TL;DR: The synaptic behavior of a Ag/AgInSbTe/Ta (AIST)-based memristor is experimentally demonstrated, and a neural architecture using one AIST Memristor as a synapse is proposed, where both the plus and minus weights of the neural synapses are realized in a single memristive array.
Abstract: The memristor, a promising candidate for synaptic interconnections in artificial neural network, has gained significant attention for application to neuromorphic systems. One common method is using two memristors as one synapse to represent the positive and negative weights. In this paper, the synaptic behavior of a Ag/AgInSbTe/Ta (AIST)-based memristor is experimentally demonstrated. In addition, a neural architecture using one AIST memristor as a synapse is proposed, where both the plus and minus weights of the neural synapses are realized in a single memristive array. Moreover, the memristor-based neural network is extended to a multilayer architecture, and modified memristor-based backpropagation learning rules are implemented on-chip to achieve pattern recognition. The effects of device variations and input noise on the performance of a memristor-based multilayer neural network (MNN) are also described. The proposed MNN is capable of pattern recognition with high success rates and exhibits several advantages, such as good accuracy, high robustness, and noise immunity.

Journal ArticleDOI
TL;DR: A nonquasi-static RF model is adopted to analyze the behavior of the proposed ED-TFET in high frequency region and the modeled result shows excellentmatching with the Y-parameters upto 500 GHz.
Abstract: In this paper, we investigate a polarity controlled electrically doped tunnel FET (ED-TFET) based on the bandgap engineering for analog/RF applications. The proposed device exhibits a heavily doped n-type Si-channel with two distinctive gate: 1) control gate (CG) and 2) polarity gate (PG). First, the work function of 4.72 eV is considered for CG and PG to convert the layer beneath CG and PG of intrinsic type. Further, a bias of −1.2 V is applied at PG terminal to induce a p+ region, so that, it follows the similar trend as like a n+-i-p+ gated structure of conventional TFET. To improve the ON-state current of the proposed device, we investigate an interfacing of III–V with IV group material for heterojunction. It shows higher ON-state current in the order of $10^{-4}$ A/ $\mu \text{m}$ , ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio (in the order of $10^{12}$ ) at ${V}_{\sf DS} = 0.7$ V. Further, its higher transconductance ${g} _{m}\approx 1.02$ mS and different RF performance parameters in the range of terahertz, enables its potential for analog/RF applications. However, linearity parameters are analyzed to give the assurance of the device for high-frequency applications. Moreover, a nonquasi-static RF model is adopted to analyze the behavior of the proposed ED-TFET in high frequency region. Based on this, the small-signal parameters were extracted and verified upto 500 GHz. The modeled result shows excellentmatching with the Y-parameters upto 500 GHz.

Journal ArticleDOI
TL;DR: The results demonstrate that the analyzed devices do not suffer from dynamic ON-resistance problems, and the impact of hard switching on dynamic becomes weaker at high-temperature levels, as the average energy of hot electrons decreases due to the increase scattering with the lattice.
Abstract: This paper reports on the impact of soft- and hard-switching conditions on the dynamic ON-resistance of AlGaN/GaN high-electron mobility transistors. For this study, we used a special double pulse setup, which controls the overlapping of the drain and gate waveforms (thus inducing soft and hard switching), while measuring the corresponding impact on the ON-resistance, drain current, and electroluminescence (EL). The results demonstrate that the analyzed devices do not suffer from dynamic ${R}_{ {\mathrm{\scriptscriptstyle ON}}}$ increase when they are submitted to soft switching up to ${V}_{{\text {DS}}}= 600$ V. On the contrary, hard-switching conditions lead to a measurable increase in the dynamic ON-resistance (dynamic- ${R}_{ \mathrm{\scriptscriptstyle ON}})$ . The increase in dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ induced by hard switching is ascribed to hot-electrons effects: during each switching event, the electrons in the channel are accelerated by the high electric field and subsequently trapped in the AlGaN/GaN heterostructure or at the surface. This hypothesis is supported by the following results: 1) the increase in ${R}_{ \mathrm{\scriptscriptstyle ON}}$ is correlated with the EL signal measured under hard-switching conditions and 2) the impact of hard switching on dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ becomes weaker at high-temperature levels, as the average energy of hot electrons decreases due to the increase scattering with the lattice.

Journal ArticleDOI
TL;DR: A realization of stateful reconfigurable logic functions via a single three-terminal magnetic tunnel junction (MTJ) device within a spintronic memory by exploiting the novel voltage-gated spin Hall-effect driven magnetization switching mechanism is reported.
Abstract: Stateful in-memory logic (IML) is a promising paradigm to realize the unity of data storage and processing in the same die, exhibiting great feasibility to break the bottleneck of the conventional von Neumann architecture. On the roadmap toward developing such a logic platform, a critical step is the effective and efficient realization of a complete set of logic functions within a memory. In this paper, we report a realization of stateful reconfigurable logic functions via a single three-terminal magnetic tunnel junction (MTJ) device within a spintronic memory by exploiting the novel voltage-gated spin Hall-effect driven magnetization switching mechanism. This proposed reconfigurable IML methodology can be implemented within either a typical memory array or a cross-point array architecture. The feasibility of the proposed approach is successfully demonstrated with hybrid MTJ/CMOS circuit simulations. We believe our work may promote the research and development of the revolutionary IML for future non-von Neumann architectures.

Journal ArticleDOI
Junbeom Seo1, Jaehyun Lee1, Mincheol Shin1
TL;DR: In this paper, the performance of hysteresis-free short-channel negative-capacitance FETs was investigated by combining quantum-mechanical calculations with the Landau-Khalatnikov equation.
Abstract: We investigate the performance of hysteresis-free short-channel negative-capacitance FETs (NCFETs) by combining quantum-mechanical calculations with the Landau–Khalatnikov equation. When the subthreshold swing (SS) becomes smaller than 60 mV/dec, a negative value of drain-induced barrier lowering is obtained. This behavior, drain-induced barrier rising (DIBR), causes negative differential resistance in the output characteristics of the NCFETs. We also examine the performance of an inverter composed of hysteresis-free NCFETs to assess the effects of DIBR at the circuit level. Contrary to our expectation, although hysteresis-free NCFETs are used, hysteresis behavior is observed in the transfer properties of the inverter. Furthermore, it is expected that the NCFET inverter with hysteresis behavior can be used as a Schmitt trigger inverter.

Journal ArticleDOI
TL;DR: In this article, the impact of the thickness of the ferroelectric (FE) layer on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances is analyzed.
Abstract: Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer ( $T_{\textsf {FE}})$ is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of $T_{\textsf {FE}}$ on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing $T_{\textsf {FE}}$ yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as $T_{\textsf {FE}}$ is increased. Depending on the attributes of the underlying transistor, increasing $T_{\textsf {FE}}$ beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of $T_{\textsf {FE}}$ on the circuit energy–delay. Our analysis shows that for high $T_{\textsf {FE}}$ , the delay of the circuit may increase with an increase in supply voltage. However, for voltages <0.25 V, FEFINFETs show an immense promise yielding 25% lower energy at iso-delay.

Journal ArticleDOI
TL;DR: In this paper, the authors present a comprehensive validation of high endurance of deeply scaled perpendicular magnetic tunnel junctions (pMTJs) in light of various potential spin-transfer torque magnetoresistive random-access memory (STT-MRAM) use cases.
Abstract: Magnetic tunnel junctions integrated for spin-transfer torque magnetoresistive random-access memory are by far the only known solid-state memory element that can realize a combination of fast read/write speed and high endurance. This paper presents a comprehensive validation of high endurance of deeply scaled perpendicular magnetic tunnel junctions (pMTJs) in light of various potential spin-transfer torque magnetoresistive random-access memory (STT-MRAM) use cases. A statistical study is conducted on the time-dependent dielectric breakdown (TDDB) properties and the dependence of the pMTJ lifetime on voltage, polarity, pulsewidth, duty cycle, and temperature. The experimental results coupled with TDDB models project $> 10^{15}$ write cycles. Furthermore, this work reports system-level workload characterizations to understand the practical endurance requirements for realistic memory applications. The results suggest that the cycling endurance of STT-MRAM is “practically unlimited,” which exceeds the requirements of various memory use cases, including high-performance applications such as CPU level-2 and level-3 caches.

Journal ArticleDOI
TL;DR: In this paper, a normally OFF trench current aperture vertical electron transistor (CAVET) was designed and successfully fabricated with Mg-doped p-GaN current blocking layers.
Abstract: A normally OFF trench current aperture vertical electron transistor (CAVET) was designed and successfully fabricated with Mg-doped p-GaN current blocking layers. The buried Mg-doped GaN was activated using a postregrowth annealing process. The source-to-drain body diode showed an excellent p-n junction characteristics, blocking over 1 kV, sustaining a maximum blocking electric field of 3.8 MV/cm. Three-terminal breakdown voltages of trench-CAVETs, measured up to 225 V, were limited by dielectric breakdown. This paper highlights the achievement of the well-behaved buried p-n junction that has been a formidable challenge in the success of vertical GaN devices.