Showing papers in "IEEE Transactions on Electron Devices in 2018"

Critical Role of Interlayer in Hf 0.5 Zr 0.5 O 2 Ferroelectric FET Nonvolatile Memory Performance

Abstract: We fabricate, characterize, and establish the critical design criteria of Hf0.5Zr0.5O2 (HZO)-based ferroelectric field effect transistor (FeFET) for nonvolatile memory application. We quantify ${V}_{\textsf {TH}}$ shift from electron (hole) trapping in the vicinity of ferroelectric (FE)/interlayer (IL) interface, induced by erase (program) pulse, and ${V}_{\textsf {TH}}$ shift from polarization switching to determine true memory window (MW). The devices exhibit extrapolated retention up to 10 years at 85 °C and endurance up to $5\times 10^{6}$ cycles initiated by the IL breakdown. Endurance up to 1012 cycles of partial polarization switching is shown in metal–FE–metal capacitor, in the absence of IL. A comprehensive metal–FE–insulator–semiconductor FeFET model is developed to quantify the electric field distribution in the gate-stack, and an IL design guideline is established to markedly enhance MW, retention characteristics, and cycling endurance.

High Endurance Ferroelectric Hafnium Oxide-Based FeFET Memory Without Retention Penalty

Abstract: We report the integration of a ferroelectric (FE) silicon-doped hafnium oxide material in ferroelectric field-effect transistor (FeFET) devices fabricated with an optimized interfacial layer in a gate-first scheme. The effect of increasing the permittivity (k) value of the interface layer on the performance of the metal–ferroelectric–insulator–semiconductor (MFIS)-FE-HfO2 FeFET is studied in terms of its switching characteristics, endurance, and retention. In contrast to the previous work, the FE Si:HfO2-integrated FeFET devices show a low-power operation capability as well as an improved endurance characteristics without jeopardizing high-temperature retention. The utilization of an optimized SiON interface layer for MFIS-HfO2 FeFET stack is discussed, and the improvements are outlined with reference to a standard low-k SiO2 interface.

Threshold Voltage Instability in p-GaN Gate AlGaN/GaN HFETs

Abstract: We investigate the impact of the gate contact on the threshold voltage stability in p-GaN gate AlGaN/GaN heterojunction field-effect transistors with double pulse measurements on the p-GaN gate devices and device simulations. We find that, under gate stress, in the case of high-leakage Schottky contact, a negative threshold voltage shift results from hole accumulation in the p-GaN region. Conversely, in the case of low-leakage Schottky contact, hole depletion in the p-GaN region gives rise to a positive threshold voltage shift. More generally, we show that an imbalance between the hole tunneling current through the Schottky barrier and the thermionic current across the AlGaN barrier results in a variation of the total charge stored in the p-GaN region, which in turn is responsible for the observed threshold voltage shift. Finally, we present a simplified equivalent circuit model for the p-GaN gate module.

Demonstration of Constant 8 W/mm Power Density at 10, 30, and 94 GHz in State-of-the-Art Millimeter-Wave N-Polar GaN MISHEMTs

Abstract: This paper reports on state-of-the-art millimeter-wave power performance of N-polar GaN-based metal–insulator–semiconductor high-electron-mobility transistors at 30 and 94 GHz. The performance is enabled by our N-polar deep recess structure, whereby a GaN cap layer is added in the access regions of the transistor to simultaneously enhance the access region conductivity while mitigating dc-to-RF dispersion. The impact of lateral scaling of the drain access region length is examined using the tradeoff between breakdown voltage and small-signal gain. Load-pull measurements are presented at 94 GHz, corresponding to the target device operating frequency in W-band, where the device demonstrated a peak power-added efficiency (PAE) of 28.8% at 16 V and record-high maximum output power density of 8 W/mm at 20 V. Additional load-pull measurements at 30 and 10 GHz demonstrate the viability of this device across a wide frequency range where the peak power remained constant at 8 W/mm and with peak PAEs of 56% and 58%, respectively.

Cryogenic MOS Transistor Model

Abstract: This paper presents a physics-based analytical model for the MOS transistor operating continuously from room temperature down to liquid-helium temperature (4.2 K) from depletion to strong inversion and in the linear and saturation regimes. The model is developed relying on the 1-D Poisson equation and the drift-diffusion transport mechanism. The validity of the Maxwell–Boltzmann approximation is demonstrated in the limit to 0 K as a result of dopant freezeout in cryogenic equilibrium. Explicit MOS transistor expressions are then derived, including incomplete dopant ionization, bandgap widening, mobility reduction, and interface charge traps. The temperature dependence of the interface trapping process explains the discrepancy between the measured value of the subthreshold swing and the thermal limit at deep-cryogenic temperatures. The accuracy of the developed model is validated by experimental results on long devices of a commercial 28-nm bulk CMOS process. The proposed model provides the core expressions for the development of physically accurate compact models dedicated to low-temperature CMOS circuit simulation.

Numerical Investigation of Short-Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Above-Threshold Behavior

Abstract: In this paper, we analyze the impact of length scaling on the ON-state operation of the two classes of double-gate negative capacitance transistors: metal–ferroelectric–metal–insulator–semiconductor (MFMIS) and metal–ferroelectric–insulator–semiconductor (MFIS). We show that for long-channel structures, MFMIS configuration shows a higher ON current than the MFIS due to a lower drain saturation voltage of the latter. For short-channel cases, we compare these negative capacitance field effect transistors (NCFETs) under two scenarios: equal flat band voltages (iso- ${V}_{\textsf {FB}}$ ) and equal OFF currents (iso- ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ). In iso- ${V}_{\textsf {FB}}$ condition, a higher negative differential conductance (NDC) effect in the MFMIS suppresses its ON current below that of the MFIS. However, the MFMIS provides a higher ON current than the MFIS for all the channel lengths under iso- ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ condition. We further investigate the influence of quantum mechanical effects and velocity saturation of carriers on the electrical characteristics of short-channel NCFETs. We also explore the impact of inner and outer spacer fringings in NCFETs. We find that the ferroelectric voltage gain in NCFETs with spacers increases with the channel length scaling, which provides a further improvement in the ON current contrary to those without spacers. Moreover, increase in the spacer permittivity also boosts both the ON current and the NDC.

Physical Insights on Negative Capacitance Transistors in Nonhysteresis and Hysteresis Regimes: MFMIS Versus MFIS Structures

Abstract: We present a comprehensive comparison of the two different types of ferroelectric negative capacitance FET (NCFET) structures: metal-ferroelectric-metal-insulator-semiconductor (MFMIS) and metal-ferroelectric-insulator-semiconductor (MFIS). A new segmentation approach is proposed to simulate MFIS NCFET, which correctly takes care of the nonuniformity in potential and horizontal electric field at the ferroelectric–oxide interface. We show that MFMIS NCFET provides a higher ON-current than MFIS NCFET except for the ferroelectrics with very low remnant polarization ( ${P}_{r}$ ) in the high operating voltage regime. We find that this behavior is caused by a reduction or enhancement of the longitudinal electric field in the channel of MFIS structure depending upon ${P}_{r}$ of the ferroelectric and the operating voltage. Moreover, there exists an optimum ${P}_{r}$ which provides maximum ON-current for both the devices. We also find that MFIS NCFET is more prone to hysteresis and starts showing a hysteretic behavior at a lower ferroelectric thickness compared with MFMIS NCFET.

BTI Analysis Tool—Modeling of NBTI DC, AC Stress and Recovery Time Kinetics, Nitrogen Impact, and EOL Estimation

Abstract: A comprehensive modeling framework is presented to predict the time kinetics of negative bias temperature instability stress and recovery during and after dc and ac stresses and also during mixed dc–ac stress. The model uses uncorrelated contributions from the generation of interface and bulk traps and hole trapping in preexisting bulk traps. Ultrafast measured data at different stresses and recovery biases, temperature, duty cycle and frequency, as well as arbitrary time segments with dynamically varying voltage, frequency, and activity are predicted. The role of nitrogen in the gate insulator is explained. End-of-life degradation is determined under dc and ac use conditions.

Improved Switching Stability and the Effect of an Internal Series Resistor in HfO 2 /TiO x Bilayer ReRAM Cells

Abstract: Bipolar redox-based resistive random-access memory cells are intensively studied for new storage class memory and beyond von Neumann computing applications However, the considerable variability of the resistance values in ON and OFF state as well as of the SET voltage remains challenging In this paper, we discuss the physical origin of the significant reduction in the switching variability of HfO2-based devices achieved by the insertion of a thin TiO x layer between the HfO2 layer and the oxygen exchange metal layer Typically, HfO2 single layer cells exhibit an abrupt SET process, which is difficult to control In contrast, self-compliance effects in the HfO2/TiO x bilayer devices lead to an increased stability of SET voltages and OFF-state resistances The SET process is gradual and the RESET becomes abrupt for higher switching currents Comparison of the experimental data with simulation results achieved from a physics-based compact model for the full description of the switching behavior of the single layer and bilayer devices clearly reveal three major effects The TiO x layer affects the temperature distribution during switching (by modifying the heat dissipation), forms an additional series resistance and changes the current conduction mechanism in the OFF state of the bilayer device compared to the single layer device

Ultrathin-Barrier AlGaN/GaN Heterostructure: A Recess-Free Technology for Manufacturing High-Performance GaN-on-Si Power Devices

Abstract: (Al)GaN recess-free normally OFF technology is developed for fabrication of high-yield lateral GaN-based power devices. The recess-free process is achieved by an ultrathin-barrier (UTB) AlGaN/GaN heterostructure that features a natural pinched-off 2-D electron gas channel. The top–down manufacturing technique overcomes the challenges in etching of AlGaN barrier with well-controlled depth and uniformity, which is especially attractive for fabrication of normally OFF GaN-based high-electron-mobility transistors (HEMTs) and metal–insulator–semiconductor HEMTs (MIS-HEMTs) on large-size Si substrate. With SiNx passivation grown by low-pressure chemical-vapor deposition, on-resistance of the UTB-AlGaN/GaN-based power devices can be significantly reduced. High-uniformity low-hysteresis normally OFF HEMTs and Al2O3/AlGaN/GaN MIS-HEMTs are successfully demonstrated on the UTB AlGaN/GaN-on-Si platform. It is also a compelling technology platform for manufacturing high-performance GaN-based lateral power diodes, and normally OFF p-(Al)GaN heterojunction field-effect transistors.

A $256\times256$ , 100-kfps, 61% Fill-Factor SPAD Image Sensor for Time-Resolved Microscopy Applications

Abstract: A $256\times256$ single-photon avalanche diode image sensor operating at 100 kfps with fill factor of 61% and pixel pitch of $16~\mu \text{m}$ is reported. An all-nMOS 7T pixel allows gated operation down to 4 ns and ~600-ps fall time with on-chip delay generation. The sensor operates with 0.996 temporal aperture ratio in rolling shutter. Gating and cooling allow the suppression of dark noise, which, in combination with the high fill factor, enables competitive low-light performance with electron multiplying charge-coupled devices while offering time-resolved imaging modes.

Compressed Sensing With Approximate Message Passing Using In-Memory Computing

Abstract: In-memory computing is a promising non-von Neumann approach where certain computational tasks are performed within resistive memory units by exploiting their physical attributes In this paper, we propose a new method for fast and robust compressed sensing (CS) of sparse signals with approximate message passing recovery using in-memory computing The measurement matrix for CS is encoded in the conductance states of resistive memory devices organized in a crossbar array In this way, the matrix-vector multiplications associated with both the compression and recovery tasks can be performed by the same crossbar array without intermediate data movements at potential ${O}{(}{1}{)}$ time complexity For a signal of size ${N}$ , the proposed method achieves a potential ${O}{(}{N}{)}$ -fold recovery complexity reduction compared with a standard software approach We show the array-level robustness of the scheme through large-scale experimental demonstrations using more than 256k phase-change memory devices

PBTI in GaN-HEMTs With p-Type Gate: Role of the Aluminum Content on $\Delta V_{\mathrm {TH}}$ and Underlying Degradation Mechanisms

Abstract: In this paper, we present an experimental analysis of the degradation induced by positive bias temperature instability stress in GaN-based power high electron mobility transistors with p-type gate, controlled by a Schottky metal/p-GaN junction. In particular, the role of the aluminum content (Al%) in the AlGaN barrier layer on the threshold voltage degradation is investigated by means of constant voltage stress measurements. This has been performed for different process conditions with varying Al content. Main results in this paper demonstrate that when a relatively large positive bias is applied on the gate, two competing trapping mechanisms take place in the AlGaN barrier layer or at the p-GaN/AlGaN interface causing ${V}_{\text {TH}}$ instability. First, an aluminum independent hole trapping mechanism, caused by elastic tunneling from p-GaN valence band (2-D hole gas), leads to a relatively short-time and recoverable negative ${V}_{\text {TH}}$ shift. In the second step, defect creation occurs. These additional defects are filled with electrons and cause a permanent or slowly recoverable positive ${V}_{\text {TH}}$ degradation. The amount of defect creation was dependent on the Al% in the barrier.

2-D Layered Materials for Next-Generation Electronics: Opportunities and Challenges

Abstract: Since the discovery of graphene in 2004, which proved the existence of 2-D crystals in nature, layered materials also known as van der Waals solids have received extensive reexamination, especially in the single-layer and multilayer forms because of their van der Waals type structure and unique properties that not only benefit many existing electronic components but also enable novel device concepts and design architectures. Numerous research efforts have been invested in these materials, and enormous quantities of results have been generated during the past 14 years. This paper provides an overview of the key physics and technology issues along with the most promising nanoelectronic applications of these materials and also identifies the challenges in this rapidly evolving field.

Engineering Negative Differential Resistance in NCFETs for Analog Applications

Abstract: In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper.

Terahertz Large-Orbit High-Harmonic Gyrotrons at IAP RAS: Recent Experiments and New Designs

Abstract: We describe new versions of high-harmonic gyrotrons with axis-encircling electron beams developed on the basis of two (80-keV pulsed and 30-keV continuous wave) experimental setups. Selective operation at the second (0.267 THz) and at the third (0.394 THz) cyclotron harmonics was observed in the 30-keV gyrotron. Cavities with periodic phase correctors, where a far-from-cutoff axial mode with a decreased diffraction Q-factor is excited in a gyrotron-like regime, are designed to improve the operation at the third harmonic, as well as to achieve the fourth-harmonic operation at frequencies up to 0.65 THz. At the pulsed gyrotron setup, a sectioned cavity with a decreased diffraction Q-factor was experimentally tested.

Analytical Model for the Threshold Voltage of ${p}$ -(Al)GaN High-Electron-Mobility Transistors

Abstract: An analytical model for the calculation of the threshold voltage for enhancement-mode (E-mode) ${p}$ -(Al)GaN high-electron-mobility transistors (HEMTs) is presented. The ON-state behavior (at low output voltages) of both ${p}$ -GaN HEMTs and ${p}$ -AlGaN HEMTs—including the gate injection transistor—are discussed in detail, and closed expressions for the threshold voltage ${V}_{T}$ of both devices are deduced. It is found that the threshold voltage values for both devices are close to one another, and that there is an ideal upper limit when the ${p}$ -type doping in the AlGaN gate is perfectly tailored, yielding more positive threshold voltages. This ideal case might be difficult to realize technologically, but can serve as a benchmark for the ${V}_{T}$ of ${p}$ -(Al)GaN HEMTs.

Enhancement of Breakdown Voltage in AlGaN/GaN HEMTs: Field Plate Plus High- ${k}$ Passivation Layer and High Acceptor Density in Buffer Layer

Abstract: We make a 2-D analysis of breakdown characteristics of field-plate AlGaN/GaN HEMTs with a high- ${k}$ passivation layer, and the results are compared with those having a normal SiN passivation layer. As a result, it is found that the breakdown voltage is enhanced particularly in the cases with relatively short field plates because the reduction in the electric field at the drain edge of gate effectively improves the breakdown voltage in the case with the high- ${k}$ passivation layer. In the case with the moderate-length field plate, the enhancement of breakdown voltage due to the high- ${k}$ passivation layer occurs because the electric field profiles between the field-plate edge and the drain become more uniform. It is also studied how the breakdown voltage depends on a deep-acceptor density in the Fe-doped semi-insulating buffer layer when a high- ${k}$ passivation layer is used. It is shown that the breakdown voltage increases with increasing the relative permittivity of the passivation layer $\varepsilon _{\text{r}}$ and with increasing the deep-acceptor density NDA. When $\varepsilon _{\text{r}} = 60$ and $N_{\mathrm {DA}} = 2$ – $3 \times 10^{17}$ cm−3 at the gate length of $0.3~\mu \text{m}$ , the breakdown voltage becomes about 500 V at a gate-to-drain distance of $1.5~\mu \text{m}$ , which corresponds to an average electric field of about 3.3 MV/cm between the gate and the drain.

A High-Performance Inverted-C Tunnel Junction FET With Source–Channel Overlap Pockets

Abstract: In this paper, we propose and simulate a new structure of a line tunnel FET employing gate over source–channel overlap pockets (GO-SCOPs). The SCOPs create vertical tunneling path within the source and the channel extension that lead to a faster thinning of the lateral tunneling barrier between the source and channel regions. As a result, an inverted C-shaped tunnel junction is formed providing both lateral tunneling and vertical tunneling. A calibrated 2-D simulation study shows that an ON-current improvement by one order is achieved in comparison with the gate over source only (GoSo) tunnel field-effect transistors with pockets. Further, the OFF-state leakage and average subthreshold swing are reduced by 44% and 21%, respectively, with an improved parasitic capacitance. This has improved the cutoff frequency from 8.3 MHz in GoSo with pockets structure to 1.19 GHz in the proposed GO-SCOP structure. Furthermore, by employing Ge SCOPs, the ON current is boosted by 4 orders of magnitude, maintaining leakage at ~0.25 fA/ $\mu \text{m}$ , giving ${I}_{\text {ON}}/{I}_{\text {OFF}} > {10}^{{9}}$ , and a much improved average subthreshold swing of ~48 mV/dec at ${V}_{ \text {GS}}= {2}$ V, ${V}_{\text {DS}}= {0.5}$ V.

14-nm FinFET Technology for Analog and RF Applications

Abstract: This paper describes the features and performance of an analog and RF device technology development on a 14-nm logic FinFET platform. An optimized single-side gate contact RF device layout shows a ${F}_{t}/{F}_{\text {max}}$ of 314/180 GHz and 285/140 GHz for ${N}$ and PFinFET device, respectively. The double-side gate contact structure with contact on either end of active gate enhances the peak ${F}_{\text {max}}$ performance to 227 and 195 GHz for both ${N}$ and PFinFET devices, respectively. A significant boost in the PFinFET RF performance is observed compared to 28-nm planar PFET, which is attributed to the source/drain SiGe epitaxy stressor that results in higher hole carrier mobility. On the other hand, the thin channel body of FinFET structure facilitates a better electrostatic control of gate over the channel region and hence suppresses short channel effects including the drain-induced barrier lowering. Consequently, a significantly higher self-gain ( ${G}_{m}/{G}_{\text {ds}})~40$ and 34 for both NFinFET and PFinFET is achieved. In addition, N/PFinFETs demonstrate superior 1/f noise of 17/35 fV $^{2}\mu \text{m}^{2}$ /Hz at 1 kHz compared to 171/106 fV $^{\mathrm {\mathbf {2}}}\mu \text{m}^{2}$ /Hz of 28-nm planar N/PFETs. To extend the low-voltage operation and power saving of FinFET RF platform, ultralow ${V}_{t}$ N/PFinFETs in the range of 50 mV ${V}_{t}\text{s}$ are also developed. Furthermore, a deep n-well process is added to the platform to provide device and circuit isolation from substrate and supply noise, while realizing the creation of new devices such as vertical NPN, PCAP, and high breakdown voltage deep n-well junction diodes. Overall, a superior ${F}_{t}/{F}_{\textsf {max}}$ , high self-gain, low 1/f noise, and robust substrate isolation characteristics extend the capability of this new 14-nm FinFET technology to the analog and RF circuit applications.

A High-Performance Gate Engineered InGaN Dopingless Tunnel FET

Abstract: A gate engineered InGaN dopingless tunnel FET (DL-TFET) using the charge plasma concept is proposed and investigated by silvaco Atlas simulation. In0.75Ga0.25N is a direct gap semiconductor, and the effective tunneling mass of electron and hole is smaller than that of silicon, which induces that the drain current and average subthreshold swing (SSavg) of InGaN DL-TFET improve $\text {1.3}\times \text {10}^{\text {2}}$ times and 51.1% than that of Si DL-TFET at the overdrive voltage of 0.5 V, respectively. What is more, better device performances are achieved by gate engineering with appropriate “In” fraction, proper space between the gate and source ( ${L}_{\text {gs}}$ ), and appropriate tunneling gate work function ( $\Phi _{\text {TG}}$ ). The direct-current, RF, and energy-efficient performance studies show that SSavg of 7.9 mV/dec, an on-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) of $\text {8.02} \times \text {10}^{-\text {5}}$ A/ $\mu \text{m}$ , a cutoff frequency ( ${f}_{T}$ ) of 119 GHz, and an energy delay product of 0.64 fJ-ps/ $\mu \text{m}$ can be obtained in the proposed TFET. This paper indicates that the gate engineered InGaN DL-TFET is a promising TFET for low-power RF and digital logic applications.

Frontiers in Thermionic Cathode Research

Abstract: The high electron emission resulting from low-work-function scandate-added dispenser cathodes has generated a great deal of interest and research since the late 1970s. Despite the reported high current density at low temperatures, scandate cathodes have not yet seen wide-scale industrial adoption due to poor emission uniformity, inadequate reproducibility, and short lifetimes. This lack of industrial adoption stemming from the above issues is likely due to insufficient fundamental understanding of the role that scandium plays in the emission process. Recent work by five research teams under the U.S. Defense Advanced Research Projects Agency Innovative Vacuum Electronics Science and Technology Program aims at advancing this fundamental understanding and the cathode manufacturing processing. Emission microscopy of model surfaces of adsorbed Ba–Sc–O on single crystal tungsten and detailed characterization techniques, such as Wulff shape analysis, are being used to understand the morphology, composition and phase of each of the species that comprise the cathode emitting surfaces. The structure of tungsten grains at the cathode surface of activated and unactivated scandate cathodes and the resulting emission performance are observed. 3-D printing is being investigated as an advanced manufacturing method to meet the demanding requirements of modern vacuum electron devices. Finally, density functional theory is being employed to study the work function of perovskite oxides as a novel class of alternative materials to tungsten dispenser cathodes.

Gain Analysis of a 0.2-THz Traveling-Wave Tube With Sheet Electron Beam and Staggered Grating Slow Wave Structure

Abstract: Results of numerical simulation of a miniaturized sub-THz traveling-wave tube amplifier with sheet electron beam and planar grating slow wave structure (SWS) are presented. Cold characteristics of the SWS are calculated. Small-signal and large-signal gain regimes are studied by the 1-D parametric frequency-domain code. The results are verified by simulations using 3-D particle-in-cell codes.

A Comparative Study on the Electrical Properties of Vertical ( $\bar{\sf2}01$ ) and (010) $\beta$ -Ga 2 O 3 Schottky Barrier Diodes on EFG Single-Crystal Substrates

Abstract: This paper reports a comprehensive study on the anisotropic electrical properties of vertical ( $\overline {\textsf {2}}01$ ) and (010) $\beta $ -Ga2O3 Schottky barrier diodes (SBDs). The devices were fabricated on single-crystal substrates grown by an edge-defined film-fed growth method. The temperature-dependent current–voltage (I–V) and capacitance–voltage (C–V) characteristics were systematically measured, analyzed, and compared. The ( $\overline {\textsf {2}}01$ ) and (010) SBDs exhibited on-resistances ( ${R}_{{ \mathrm{\scriptscriptstyle ON}}}$ ) of 0.56 and $0.77~\textsf {m}\Omega \cdot \textsf {cm}^{{\textsf {2}}}$ , turn- ON voltages ( ${V}_{{ \mathrm{\scriptscriptstyle ON}}}$ ) of 1.0 and 1.3 V, Schottky barrier heights (SBHs) of 1.05 and 1.20 eV, electron mobilities of 125 and 65 cm2/( $\textsf {V}\cdot ~\textsf {s}$ ), respectively, with an on-current of ~1.3 kA/cm2 and on/off ratio of ~109. The (010) SBD had a larger ${V}_{{ \mathrm{\scriptscriptstyle ON}}}$ and SBH due to anisotropic surface properties (i.e., surface Fermi level pinning and band bending), as supported by X-ray photoelectron spectroscopy measurements. Temperature-dependent I–V also revealed the inhomogeneous nature of the SBH in both devices, where the ( $\overline {\textsf {2}}01$ ) SBD showed a more uniform SBH distribution. The homogeneous SBH was also extracted: 1.33 eV for the ( $\overline {\textsf {2}}01$ ) SBD and 1.53 eV for the (010) SBD. The reverse leakage current of the devices was well described by the two-step trap-assisted tunnelingmodel and the 1-D variable range hopping conduction model. The ( $\overline {\textsf {2}}01$ ) SBD showed a larger leakage current due to its lower SBH and/or smaller activation energy, and thus a smaller breakdown voltage. These results indicate that the crystalline anisotropy of $\beta $ -Ga2O3 can affect the electrical properties of vertical SBDs and should be taken into consideration when designing $\beta $ -Ga2O3 electronics.

Ultrafast Measurements and Physical Modeling of NBTI Stress and Recovery in RMG FinFETs Under Diverse DC–AC Experimental Conditions

Abstract: Threshold voltage shift ( $\Delta {\text V}_{\text T}$ ) due to negative-bias temperature instability (NBTI) in p-FinFETs with replacement metal gate-based high-k metal gate process is measured using an ultrafast method. A comprehensive modeling framework involving uncorrelated contributions from the generation of interface traps ( $\Delta {\text V}_{\text {IT}}$ ), hole trapping in preexisting ( $\Delta {\text V}_{\text {HT}}$ ), and generation of new ( $\Delta {\text V}_{\text {OT}}$ ) bulk insulator traps is used to quantify measured data. The model can explain dc stress and recovery data over an extended temperature range (−40 °C to 150 °C), for different stress and recovery biases. It can explain ac stress and recovery data for different bias, temperature, frequency, and duty cycle. The differences in time kinetics and temperature activation of $\Delta {\text V}_{\text {IT}}$ , $\Delta {\text V}_{\text {HT}}$ , and $\Delta {\text V}_{\text {OT}}$ , and their relative dominance at various experimental conditions are shown. End-of-life NBTI for dc and ac stress is estimated by using the model and compared to prediction from conventional analytical methods.

Gate Conduction Mechanisms and Lifetime Modeling of p-Gate AlGaN/GaN High-Electron-Mobility Transistors

Abstract: The gate conduction mechanisms in p-gallium nitride (GaN)/AlGaN/GaN enhancement mode transistors are investigated using temperature-dependent dc gate current measurements. In each of the different gate voltage regions, a physical model is proposed and compared to experiment. At negative gate bias, Poole–Frenkel emission (PFE) occurs within the passivation dielectric from gate to source. At positive gate bias, the p-GaN/AlGaN/GaN “p-i-n” diode is in forward operation mode, and the gate current is limited by hole supply at the Schottky contact. At low gate voltages, the current is governed by thermionic emission with Schottky barrier lowering in dislocation lines. Increasing the gate voltage and temperature results in thermally assisted tunneling (TAT) across the same barrier. An improved gate process reduces the gate current in the positive gate bias region and eliminates the onset of TAT. However, at high positive gate bias, a sharp increase in current is observed originating from PFE at the metal/ p-GaN interface. Using the extracted conduction mechanisms for both devices, accurate lifetime models are constructed. The device fabricated with the novel gate process exhibits a maximum gate voltage of 7.2 V at ${t}_{\textsf {1}\%}=\textsf {10}$ years.

Resistive Switching Device Technology Based on Silicon Oxide for Improved ON–OFF Ratio—Part II: Select Devices

Abstract: The cross-point architecture for memory arrays is widely considered as one of the most attractive solutions for storage and memory circuits thanks to simplicity, scalability, small cell size, and consequently high density and low cost. Cost-scalable vertical 3-D cross-point architectures, in particular, offer the opportunity to challenge Flash memory with comparable density and cost. To develop scalable cross-point arrays, however, select devices with sufficient ON–OFF ratio, current capability, and endurance must be available. This paper presents a select device technology based on volatile resistive switching with Cu and Ag top electrode and silicon oxide (SiO x ) switching materials. The select device displays ultrahigh resistance window and good current capability exceeding 2 MAcm−2. Retention study shows a stochastic voltage-dependent ON–OFF transition time in the ${10}~\mu \text{s}$ –1 ms range, which needs to be further optimized for fast memory operation in storage class memory arrays.

Layout Design Correlated With Self-Heating Effect in Stacked Nanosheet Transistors

Abstract: With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation. The anisotropic thermal conductivity of nanosheets with the dependence of silicon thickness and temperature is implemented in the FEM simulator to evaluate thermal behavior accurately. The impact of layout design on thermal properties is investigated comprehensively from single device to device arrays with implication on electrical performance. The results indicate that the width of nanosheet is the key parameter to make the tradeoffs between self-heating and electrical characteristic. Meanwhile, the optimizations of layout design are given to suppress the thermal effects, including self-heating, nonuniformity of temperature, and thermal crosstalk at device level. This paper will provide guidelines for layout design, thermal management, device performance, and thermal-aware reliability prediction in the GAA-stacked structure.

The Fabrication and MOSFET-Only Circuit Implementation of Semiconductor Memristor

Abstract: In this paper, a ZnO-based semiconductor thin film memristor (300 nm in thickness) device is fabricated using metallic top and bottom electrodes by direct-current reactive magnetron sputter. The memristive characteristics of the device were completed by time-dependent current–voltage ( ${I}$ – ${V}$ - ${t}$ ) measurements, and the typical pinched hysteresis ${I}$ – ${V}$ loops of the memristor were observed. This paper is continued with the designing memristor emulator circuit, which has only four MOS transistors. The proposed circuit is suitable both for emulating the fabricated memristor and for using general memristor-based applications. Any circuit blocks such as a multiplier or active element are not used in the circuit to obtain memristive characteristics. All results of the proposed memristor emulator circuit are compatible with general characteristics of the fabricated semiconductor device. The MOSFET-based proposed memristor emulator circuit is laid out in the Analog Design Environment of Cadence Software using 180-nm TSMC CMOS process parameters and its layout area is 366 $\mu \text{m}^{\textsf {2}}$ . So as to show its performance, the dependences of the operating frequency and process corner as well as effects of radical temperature changes have been investigated in the simulation results section.

2-D Analytical Drain Current Model of Double-Gate Heterojunction TFETs With a SiO 2 /HfO 2 Stacked Gate-Oxide Structure

Abstract: A continuous 2-D analytical drain current model of double-gate (DG) heterojunction tunnel field-effect transistors (HJTFETs) with a SiO2/HfO2 stacked gate-oxide structures has been presented in this paper. The surface potential model has been developed by considering the effect of accumulation/inversion charges and depletion region at source/channel and drain/channel junctions. The electric field-dependent band-to-band tunneling generation rate has been derived from the surface potential model. The tangent line approximation method has been used to calculate the drain current of DG HJTFETs. The developed model is valid for all regions (subthreshold to strong accumulation/inversion region) of operation. The model has been developed for Si/Ge hetero and Si homojunction-based tunnel field-effect transistor devices. The model is also applicable for other structures such as III–V materials-based InAs/GaSb DG HJTFET and silicon-on-insulator-based HJTFET. The analytical model results are validated by 2-D ATLAS simulation data.