Showing papers in "IEEE Transactions on Electron Devices in 2019"

Fully Inkjet-Printed Photodetector Using a Graphene/Perovskite/Graphene Heterostructure

Abstract: Photodetectors (PDs) based on organic–inorganic hybrid materials such as graphene and perovskites have recently emerged at the forefront of the research in optoelectronic devices. Despite the remarkable progress in the performance of optoelectronic devices based on hybrid materials, some aspects such as stability have so far not been thoroughly addressed. This paper serves to demonstrate a fully inkjet-printed PD fabricated by hybrid perovskite (CH3NH3PbClx-3I3) layer between the two graphene electrodes as graphene/perovskite/graphene (GPG) heterostructure. The fully inkjet-printed GPG PD is found to be effective for the visible light region, which can be attributed by the high uniformity and low defects of the printed materials. Thus, the GPG PD achieves a high responsivity of 0.53 A/W. Fully inkjet-printed hybrid perovskite PD demonstrated in this paper unveils the facile, potentially large-scale and cost-effective methods for fabrication of hybrid perovskites-based optoelectronic devices, including PDs and solar cells.

Ferroelectric FETs With 20-nm-Thick HfO 2 Layer for Large Memory Window and High Performance

Abstract: Hafnium oxide (HfO2)-based ferroelectric field-effect transistor (FeFET) is an attractive device for nonvolatile memory. However, when compared to the well-established flash devices, the memory window (MW) of FeFETs reported so far is rather limited, which might be an obstacle to practical applications. In this article, we report on FeFETs fabricated in the 28-nm high- ${k}$ metal gate (HKMG) bulk technology with 90 and 80 nm for the channel length and width, respectively, which show a large MW of nearly 3 V. This is achieved by adopting 20-nm-thick HfO2 films in the gate stack instead of the usually employed 10-nm-thick films. We show that such a thickness increase leads to only a moderate increase of the switching voltages, and to a significantly improved resilience of the memory characteristics upon the parasitic charge trapping. The devices display a good retention at high temperatures and endure more than $10^{{5}}$ bipolar cycles, thus supporting this technology for a future generation of FeFET memories.

ASM GaN: Industry Standard Model for GaN RF and Power Devices—Part 1: DC, CV, and RF Model

Abstract: We present the latest developments in Advance SPICE Model for GaN (ASM GaN) HEMTs in this paper. The ASM GaN model has been recently selected as an industry-standard compact model for GaN radio frequency (RF) and power devices. The core surface-potential calculation and the modeling of real device effects in this model are presented. We discuss the details of the nonlinear access region model and enhancement in this model to include a physical dependence on barrier thickness. We also present the novel model feature of configurable field-plate modeling and discuss the extraction procedure for the same. New results with the ASM GaN model on high-frequency and enhancement-mode GaN power devices are also presented.

Review on SiC MOSFETs High-Voltage Device Reliability Focusing on Threshold Voltage Instability

Abstract: An overview over issues and findings in SiC power MOSFET reliability is given. The focus of this article is on threshold instabilities and the differences to Si power MOSFETs. Measurement techniques for the characterization of the threshold voltage instabilities are compared and discussed. Modeling of the threshold voltage instabilities based on capture–emission-time (CET) maps is a central topic. This modeling approach takes the complete gate bias/temperature history into account. It includes both gate stress polarities and is able to reproduce the short-term threshold variations during application-relevant 50-kHz bipolar ac-stress. In addition, the impact on circuit operation is discussed.

Frequency- and Temperature-Dependent Gate Reliability of Schottky-Type ${p}$ -GaN Gate HEMTs

Abstract: In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type ${p}$ -GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current–voltage ( I–V ) characteristics and threshold voltage ( ${V}_{\text {TH}}$ ) instability of ${p}$ -GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the ${p}$ -GaN layer would promote the formation of defect levels near the metal/ ${p}$ -GaN interface, leading to the initial ${p}$ -GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier.

Stability and Reliability of Lateral GaN Power Field-Effect Transistors

Abstract: GaN electronics constitutes a revolutionary technology with power handling capabilities that amply exceed those of Si and other semiconductors in many applications. RF, microwave, and millimeter-wave GaN-based power amplifiers are now deployed in commercial communications, radar, and sensing systems. GaN power transistors for electrical power management are also starting to reach the marketplace. From the dawn of this technology, inadequate transistor stability and reliability have represented stumbling blocks preventing widespread commercial use of GaN electronics. Intense research has been devoted to addressing these issues, and great progress has taken place recently. This article reviews some of the most interesting and significant stability and reliability issues that have plagued GaN power field-effect transistors for RF and power management applications.

Effects of Postannealing on the Characteristics and Reliability of Polyfluorene Organic Light-Emitting Diodes

Abstract: We studied the effects of postannealing on the performance of polyfluorene organic light-emitting diodes (OLEDs) with a pure poly(9, $9'$ -dioctylfluorene-co-benzothiadiazole) (F8BT) emissive layer. After annealing at 150 °C–200 °C, the OLED exhibited the lowest voltage and highest luminance. This correlated well with the highest crystallinity of the F8BT film, as revealed by X-ray diffraction. As the temperature was raised up to 300 °C, the voltage at 50 mA/cm2 increased by 2.7 V, and the luminance decreased by 44%, whereas the device lifetime was markedly extended by as much as 13 times. The loss of crystallinity at high temperatures suggested that structural disorders were created, resulting in degraded charge transport and radiative process. Our study demonstrates the necessity of posttreatment above the glass transition temperature to obtain desirable efficiency and lifetime of solution-processed polyfluorene OLEDs.

Performance Assessment of New Dual-Pocket Vertical Heterostructure Tunnel FET-Based Biosensor Considering Steric Hindrance Issue

Abstract: In this paper, a new dual-pocket (DP), dielectric modulated (DM) heterostructured tunnel field-effect transistor (DM-HTFET)-based biosensor has been reported. First, the efficacy of the DP-hetero-TFET (HTFET) has been analyzed by comparing it with other existing TFET structures. Next, a comprehensive assessment of sensitivity between single-pocket (SP) and DP-DM-HTFET biosensors for pocket thickness ( ${T}_{\text {pocket}}$ ), pocket length ( ${L}_{\text {pocket}}$ ), pocket doping ( ${N}_{\text {pocket}}$ ), work function of the gate metal, molar fraction of Ge, gate oxide layer, and gate oxide layer thickness ( ${T}_{\text {ox}}$ ) was done. Hence, a nonuniform arrangement of biomolecules inside the cavity simulation has been done using ATLAS device simulation software to validate the working ability of the proposed sensor. Significant improvement in the sensitivity due to threshold voltage (ON-current) i.e., 26.78% (78.5%), 60.8% (40.4%), 56% ( ${2.2} \times {10}^{{2}}$ %), and 40.6% (80.68%) has been observed for the DP-DM-HTFET over SP with the variation of ${T}_{\text {pocket}}$ , ${L}_{\text {pocket}}$ , ${N}_{\text {pocket}}$ , and ${T}_{\text {ox}}$ , respectively. DP-DM-HTFET-based current mirror circuit has also been demonstrated at the end. Sensitivity evaluation discloses that the DP-DM-HTFET can be a promising candidate for CMOS-based label-free biosensing applications.

Assessing MPPT Techniques on Hot-Spotted and Partially Shaded Photovoltaic Modules: Comprehensive Review Based on Experimental Data

Abstract: Hot-spotting is a reliability problem influencing photovoltaic (PV) modules, where a mismatched solar cell/cells heat up significantly and reduce the output power of the affected PV module. Therefore, in this paper, a succinct comparison of seven different state-of-the-art maximum power point tracking (MPPT) techniques are demonstrated, doing useful comparisons with respect to amount of power extracted, and hence calculate their tracking accuracy. The MPPT techniques have been embedded into a commercial off-the-shelf MPPT unit, accordingly running different experiments on multiple hot-spotted PV modules. Furthermore, the comparison includes real-time long-term data measurements over several days and months of validation. Evidently, it was found that both fast changing MPPT and the modified beta techniques are best to use with PV modules affected by hot-spotted solar cells as well as during partial shading conditions, on average, their tracking accuracy ranging from 92% to 94%. Ultimately, the minimum tracking accuracy is below 93% obtained for direct pulsewwidth modulation voltage controller MPPT technique.

Drain-Engineered TFET With Fully Suppressed Ambipolarity for High-Frequency Application

Abstract: In this paper, we propose and simulate a novel drain-engineered structure of a quadruple-gate tunnel field-effect transistor (TFET). The proposed device employs a lateral dual source with a vertical drain extension on top of T-shaped channel region. This enables the modification of screening length ( $\lambda $ ) by varying the silicon film ( ${t}_{\textsf {Si},\textsf {v}}$ ) and the oxide ( ${t}_{\textsf {Si},\textsf {v}}$ ) thicknesses at the channel–drain junction to overcome the limitations of high ambipolar leakage in the conventional double-gate TFET (DG-TFET). A 2-D calibrated simulation study has revealed the doubling of on-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) and significantly suppressed ambipolar leakage ( ${I}_{\textsf {AMB}}$ ) in the proposed device as compared to the conventional DG-TFET. Furthermore, a five orders of magnitude improvement in ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , 73% increase in transconductance ( ${g}_{\textsf {m}}$ ), 62% increase in cutoff frequency ( ${f}_{\textsf {T}}$ ), 72% increase in gain-bandwidth product, and 54% improvement in fall propagation delay ( ${t}_{\textsf {pHL}}$ ) are achieved in the proposed device.

Comparative Study on Performance of IGZO Transistors With Sputtered and Atomic Layer Deposited Channel Layer

Abstract: The structural, chemical, and electrical properties of amorphous indium gallium zinc oxide (a-IGZO) films by magnetron sputtering and atomic layer deposition (ALD) were investigated where both a-IGZO films had a comparable cation composition. The ALD-derived a-IGZO film exhibited the higher atomic packing density, the effective suppression of trap-like oxygen vacancy defect (VO), and the enhancement in the hybridization of the sp orbital of In, Ga, and Zn cations compared to those of the sputtered a-IGZO film. Hence, a significant improvement in terms of the field-effect mobility was observed for the thin-film transistors with an In0.50Ga0.34Zn0.16O channel by ALD (36.6 cm $^{\textsf {2}}/\text{V}\cdot \text{s}$ ) compared to that of the sputtered In0.48Ga0.38Zn0.14O transistor (20.1 cm $^{\textsf {2}}/\text{V}\cdot \text{s}$ ); the ${I}_{\text {ON/OFF}}$ ratios for both were ~107. Simultaneously, the gate bias stress stability and photobias stress stability were also improved for the IGZO transistors with an ALD-derived channel, which can be explained by its reduced trap-like VO density.

Double-Gate TFET With Vertical Channel Sandwiched by Lightly Doped Si

Abstract: This paper examines a tunnel field-effect transistor (TFET) as a promising device for achieving steeper switching and better electrical performances in low-power operation. It features a double-gate TFET with vertical channel sandwiched by lightly doped Si (VS-TFET). The vertical tunnel junction is employed on the source side for the steeper subthreshold swing (SS) and for the higher ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) by restricting tunnel barrier width. The VS-TFET shows 17-mV/dec minimum SS and ${10}^{ {4}}~{ \mathrm{\scriptstyle ON}}/{ \mathrm{\scriptstyle OFF}}$ current ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) for sub-0.7-V gate overdrive. In addition, the VS-TFET shows sub-60-mV/dec SS in a wide range of ${I}_{D}$ regardless of sweep directions. In conclusion, the work presented here demonstrates that the VS-TFET will be one of the most promising candidates for a next-generation low-power device.

Air Pollution Monitoring Using Near Room Temperature Resistive Gas Sensors: A Review

Abstract: The growth of industries and other human activities have led to ever increasing amounts of pollutants in both outdoor and indoor spaces. These pollutants have hazardous effects on humans and the wider ecology. Hence, air quality monitoring (AQM) is essential and involves the robust monitoring of various toxic gases and volatile organic compounds (VOCs)—in case, the concentration of any pollutant exceeds the safe limit in a given location. This paper describes the different sources of indoor and outdoor pollutants, reviews the current status of gas sensors, and discusses the role of new two dimensional (2-D) materials in detecting these hazardous gases at low power, i.e., close to the ambient temperature. Here, we review different synthesis techniques of 2-D materials and discuss the sensing performances of pristine and functionalized nanomaterials for some of the important pollutants such as NO x , NH3, SO x , CO, formaldehyde, toluene, and so on. The review concludes with some proposed methods to help in reducing air pollution today.

Performance Assessment of the Charge-Plasma-Based Cylindrical GAA Vertical Nanowire TFET With Impact of Interface Trap Charges

Abstract: In this article, a charge-plasma (CP)-based gate-all-around (GAA) silicon vertical nanowire tunnel field-effect transistor (NWTFET) is proposed. The effects of interface trap charges (ITCs) on dopingless (DL) NW-based device have been addressed for the first time. CP technique is used to induce charge carriers within the drain/source regions by depositing layers of metals with specific work function. Linearity performance parameters such as higher order harmonic distortions (HDs), intermodulation distortions (IMDs), and interception points are calculated including the effects of ITCs on the cylindrical channel–surround gate–oxide interface. This work shows that positive ITCs can help in improving the device characteristics, whereas negative ITCs degrade the device performance. The ON-state current to OFF-state current ratio decreases for either polarity of ITCs. The ON-state current has been improved by approximately 50% with higher positive ITCs. The presence of positive ITCs in DL NWTFET improves the driving capability to be used for analog applications. The linearity parameters tend to improve with positive ITCs and degrade with negative ITCs. The proposed device has reached the same cutoff frequency at lower operating gate bias (approximately 0.8 V) with half the threshold voltage for higher positive ITCs.

Compact Modeling of Perpendicular-Magnetic-Anisotropy Double-Barrier Magnetic Tunnel Junction With Enhanced Thermal Stability Recording Structure

Abstract: As the basic storage unit of spin transfer torque magnetic random-access memory (STT-MRAM), the perpendicular magnetic anisotropy (PMA) magnetic tunnel junction (MTJ) has been extensively studied in recent years. Lowering the critical switching current and improving the data retention are two crucial pathways to optimize the performance of STT-MRAM. However, the conventional MTJ can merely achieve both. In this paper, we present a physics-based compact model of Ta/CoFeB/MgO PMA double-barrier MTJ (DMTJ) with enhanced thermal stability recording structure. Combination of double-barrier and synthetic double-free layers can heighten the STT effect and enhance the thermal stability simultaneously. A larger STT switching efficiency, compared with conventional MTJ, can thus be realized. The modeling results show great agreement with experimental results. A 1-bit magnetic full adder (MFA) based on DMTJ, as a hybrid logic-in-memory circuit example, has been designed and simulated to validate its functionality. This SPICE-compatible compact model will be useful for high-performance hybrid MTJ/CMOS circuit and system designs.

Carrier Transport and Gain Mechanisms in $\beta$ –Ga 2 O 3 -Based Metal–Semiconductor–Metal Solar-Blind Schottky Photodetectors

Abstract: In this paper, carrier transport and gain mechanisms are exploited in the $\beta $ -Ga2O3-based metal–semiconductor–metal photodetectors with Au back-to-back Schottky contacts. The resultant devices exhibit a low dark current of $10^{{3}}$ , and a photo-to-dark current ratio of 50 at 473 K, indicative of its strong operation capability at high temperature and in harsh environments. Temperature-dependent current–voltage features reveal that the dark reverse leakage is dominated by the thermionic field emission at low electric field and Poole–Frenkel emission from a deep trap level of 0.42 eV under the conduction band at high field, respectively. These negatively charged traps positioned below the Fermi level in the vicinity of Schottky interface capture photogenerated holes and reduce the barrier height upon illumination. The temperature- and bias-dependent photoresponse features are identified in physics that the photoconductive gain as well as slow response speed is originated from the change of barrier height due to trap repopulation.

ASM GaN: Industry Standard Model for GaN RF and Power Devices—Part-II: Modeling of Charge Trapping

Abstract: Because of charge trapping in GaN HEMTs, dc characteristics of these devices are not representative of high-frequency operation. The advanced spice model GaN model presented in Part I of this paper is combined with a Shockley–Reed–Hall-based trap model, yielding a comprehensive FET model for GaN HEMTs which can accurately model GaN devices exhibiting trapping-related dispersion effects. Measurement results of the dc and pulsed output and transfer characteristics of a commercially available GaN HEMT are presented, trapping in the device is modeled, and excellent fit to the measured data is shown. This paper presents an accurate model of trapping which is validated for eight different quiescent bias points of pulse measurements, with quiescent drain voltage ranging from 5 to 20 V and quiescent gate voltage ranging from −2.8 to −3.8 V, and a large range of gate and drain voltages to which the device was pulsed in the pulse measurements and at which the device was measured in the dc measurements, with gate voltage ranging from −4 to 0.4 V and drain voltage ranging from 0 to 40 V. This paper also presents high-frequency (10 GHz) large-signal RF validation of the model for optimal complex load condition.

Part I: Physical Insight Into Carbon-Doping-Induced Delayed Avalanche Action in GaN Buffer in AlGaN/GaN HEMTs

Abstract: Physics behind the improvement in breakdown voltage of AlGaN/GaN HEMTs with carbon-doping of GaN buffer is discussed. Modeling of carbon as acceptor traps and self-compensating acceptor/donor traps is discussed with respect to their impact on avalanche breakdown. Impact of carbon behaving as a donor as well as acceptor traps on electric field relaxation and avalanche generation is discussed in detail to establish the true nature of carbon in GaN that delays the avalanche action. This understanding of the behavior of carbon-doping in GaN buffer is then utilized to discuss design parameters related to carbon doped buffer. Design parameters such as undoped channel thickness and relative trap concentration induced by carbon-doping are discussed with respect to the performance metrics of breakdown voltage, leakage current, sheet charge density, and dynamic ON-resistance.

Facilitation of GaN-Based RF- and HV-Circuit Designs Using MVS-GaN HEMT Compact Model

Abstract: This paper illustrates the usefulness of the physics-based compact device models in investigating the impact of device behavioral nuances on the operation and performance of the circuits and systems. The industry standard MIT virtual source gallium nitride high electron-mobility transistor (GaN HEMT) (MVSG) model is used as the modeling framework to understand the operation of the GaN HEMTs and study the key device–circuit interactions in the GaN-based high-frequency and power conversion circuits. Details of the core model equations along with their physical underpinnings are presented along with the benchmark tests to verify the model’s convergence robustness and simulation accuracy. The usefulness of such a compact model in circuit design is highlighted through examples of the GaN-based high-voltage converter and RF-power amplifiers. It is shown that the slew-rates in hard-switched buck converters are determined by the dynamic charge distribution among the field plates in GaN HEMTs, indicating the importance of the device-level effect on circuit performance. Likewise, it is shown using the MVSG model that the performance metrics, such as drain efficiency and linearity, of the GaN RF-power amplifiers are heavily dependent on the device-level effects, such as access-region depletion, thermal effects, and charge-trapping effects. These GaN-based circuits designed using the MVSG model can be used as the example cases to demonstrate the importance of the accurate physical compact models in designing high performance circuits and systems in emerging technologies.

Evaluation of Low-Temperature Saturation Velocity in $\beta$ -(Al x Ga 1–x ) 2 O 3 /Ga 2 O 3 Modulation-Doped Field-Effect Transistors

Abstract: We report on the high-field transport characteristics and saturation velocity in a modulation-doped $\beta $ -(AlxGa1–x)2O3/Ga2O3 heterostructure. The formation of a 2-D electron gas (2DEG) in the modulation-doped structure was confirmed from the Hall measurements, and the 2DEG channel mobility increased from 143 cm $^{2}/\text{V}\cdot \text{s}$ at room temperature to 1520 cm $^{2}/\text{V}\cdot \text{s}$ at 50 K. The high electron mobility at 50 K made it feasible to achieve velocity saturation inside the channel. The saturation velocity was estimated based on both pulsed current–voltage measurements and small-signal radio frequency (RF) measurements. The measured velocity–field profile suggested a saturation velocity above $1.1\times 10^{7}$ cm/s at 50 K. The small-signal RF characteristics were measured for the fabricated modulation-doped field-effect transistors with a Pt-based Schottky contact. The current gain cutoff frequency ( $\text{f}_{\text {t}}$ ) and maximum oscillation frequency ( $\text{f}_{\text {max}}$ ) showed significant increases from 4.0/11.8 GHz at room temperature to 17.4/40.8 GHz at 50 K for the device with gate length of $\text{L}_{{\textsf {G}}} = 0.61\,\,\mu \text{m}$ . The analysis of the low temperature $\text{f}_{\text {t}}$ based on device simulations indicated a peak velocity of $1.2\times 10^{7}$ cm/s. The three-terminal off-state breakdown measurement further suggested an average breakdown field of 3.22 MV/cm. The high saturation velocity and high breakdown field in $\beta $ -Ga2O3 make it a promising candidate for high-power and high-frequency device applications.

Spintronic Processing Unit in Spin Transfer Torque Magnetic Random Access Memory

Abstract: Recently, exploiting emerging nonvolatile memories to implement the process-in-memory (PIM) paradigm have shown great potential to address the von Neumann bottleneck and have attracted extensive research and development. In this paper, we present a novel PIM platform—spintronic processing unit (SPU), within spin transfer toque magnetic random access memory (STT-MRAM). This energy-efficient and reconfigurable PIM platform can perform different tasks—data storage and logic computing—using the same physical fabric that is programmable at the finest grain, i.e., the individual memory cell level, without the need to move data outside the memory fabric. The proposed SPU works just like a typical memory and all the logic functions are achieved through regularmemory-like write and read operations with minimal modifications. The functionality and performance are evaluated via hybrid circuit simulations under the 40-nm process technology node. Our proposed SPU is expected to be a feasible PIM platform in the near future, owing to the increasing maturity of STT-MRAM.

Investigation of a Ge-Source Vertical TFET With Delta-Doped Layer

Abstract: In this article, a $\delta $ -doped germanium-source vertical TFET (Ge-source vTFET) is proposed and investigated by Synopsis TCAD simulation. Higher ON-state current is obtained as the electron tunneling takes place in a direction parallel to the gate electric field. The incorporation of the $\delta $ -doped layer in the germanium source region further reduces the OFF-state leakage current. The impact on the variation of the device geometric dimensions has been studied for various electrical parameters and the dimensions are optimized accordingly through extensive simulations. A very high current ratio of the order ~1011 with a substantially low average subthreshold swing of 21.2 mV/decade is achieved. Benchmarking of the proposed Ge-source vTFET with other novel TFETs is carried out which produced better results in terms of high ON -state current and SSavg. The results obtained for the proposed vTFET make it a potential candidate for ultralow-power applications.

Carrier Transport Mechanisms Underlying the Bidirectional ${V}_{\mathrm{{TH}}}$ Shift in p-GaN Gate HEMTs Under Forward Gate Stress

Abstract: The threshold voltage ( ${V} _{\text {TH}}$ ) instability of p-GaN/AlGaN/GaN HEMTs was investigated under forward gate stress. A unique bidirectional ${V} _{\text {TH}}$ shift ( $\Delta {V}_{\text {TH}}$ ) with the critical gate voltage ( ${V} _{\text {G}}$ ) of 6 V was observed. The carrier transport mechanisms underlying the $\Delta {V} _{\text {TH}}$ were extensively investigated through the voltage-dependent, time-resolved, and temperature-dependent gate current. The gate current is decomposed into electron and hole current in three distinct regions with respect to ${V} _{\text {G}}$ , which are off-state for ${V} _{\text {G}} V ( ${V} _{\text {TH}}$ ), on-state for $1.2~{V} V and “gate-injected” region for ${V} _{\text {G}}> {5}$ V. In off-state, the electrons were thermally activated and transport towards the gate, while electron-trapping governed by the space charge limited conduction (SCLC) in AlGaN barrier was observed in on-state and “gate-injected” region. Such an electron-trapping effect results in the positive ${V} _{\text {TH}}$ shift for ${V} _{\text {G}} V. Meanwhile, the marginal hole transport from gate by thermal activation was also captured by gate current, which features negligible impact on ${V} _{\text {TH}}$ . However, for ${V} _{\text {G}}> {6}$ V, a drastic hole injection triggered by high ${V} _{\text {G}}$ takes place that causes subsequent hole-trapping in AlGaN barrier and hole-injection into GaN buffer. The injected holes enhance the positive charge in the gate region and turned the positively shifted ${V} _{\text {TH}}$ into a negative shift.

Nanotube Tunneling FET With a Core Source for Ultrasteep Subthreshold Swing: A Simulation Study

Abstract: In this article, we propose a novel nanotube (NT) tunneling field-effect transistor with a core source (CSNT-TFET) which uses line tunneling. We systematically investigate the CSNT-TFET with the help of calibrated 3-D simulations and demonstrate that it outperforms the conventional NT-TFET in terms of both static and dynamic performance. We show that the CSNT-TFET exhibits a reduced average subthreshold swing (SS) of 33 mV/decade with Ge-source for more than eight orders of magnitude of drain current at an ultralow supply voltage ( ${V}_{\text {DS}}= {0.3}$ V). In addition, the ON-state current of the CSNT-TFET is enhanced by ~13 times with Si-source and by ~6 times with Ge-source even at ${V}_{\text {DS}}= {V}_{\text {GS}}= {0.3}$ V when compared with the NT-TFET. Without the use of any exotic material for the source and channel regions, the CSNT-TFET offers an impact ionization MOS-like steep SS (a minimum SSpoint of ~1 mV/decade) and a high ON-state current of ~10−6 A for ${V}_{\text {DS}}= {V}_{\text {GS}}= {0.3}$ V. Furthermore, the impact of the gate sidewall spacer and source diameter on the performance of the CSNT-TFET is also investigated.

Design and Investigation of a Novel Charge Plasma-Based Core-Shell Ring-TFET: Analog and Linearity Analysis

Abstract: A novel device architecture charge plasma-based Ring-TFET (CP-RingTFET) has been described in this work. The ring structure of the proposed device uses a core-shell architecture with a drain at the center covered with the channel and followed by the source. The ring structure has the advantage of ultrascaling and mechanical strength as compared to the nanowire structure. The performance characteristics of the Ring-TFET are much better as compared to nanowire-TFET with similar physical dimensions. To investigate the impact of charge plasma on RingTFET architecture, various analog and linearity parameters have been studied; such as OFF-state current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ), ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ), ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , subthreshold slope (SS), gate-to-gate capacitance, transconductance ( ${g}_{m}$ ), transconductance gain factor (TGF), threshold voltage ( ${V}_{\text {TH}}$ ), higher-order transconductances, higher-order harmonic distortions, third-order current intercept point (IIP3), third-order intermodulation distortions (IMD3), and higher-order voltage intercept points. The ability of the CP-RingTFET to enhance the performance of the proposed device is confirmed with the reduction of ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ , improving ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ , lower SS including the benefits of threshold voltage reduction.

Design and Investigation of Charge-Plasma-Based Work Function Engineered Dual-Metal-Heterogeneous Gate Si-Si 0.55 Ge 0.45 GAA-Cylindrical NWTFET for Ambipolar Analysis

Abstract: In this paper, we have proposed dopingless gate all around (GAA) nanowire tunnel field-effect transistor (NWTFET) made up of dual-material channel (DMaC). Charge-plasma (CP) technique is used to induce the doping concentration of charge carriers in the intrinsic semiconductor. GAA structure uses zirconium silicate (IV) (ZrSiO4)/silicon dioxide (SiO2) for heterogeneous gate (HG) structure metalized with two different gate metals. Auxiliary gate (GM1) and tunneling gate (GM2) have different work functions, i.e., $\phi _{1}$ and $\phi _{2}$ . The device physics is analyzed using electric field, charge carrier concentration, energy-band diagram, and tunneling rate across the structure. The effect of variation in $\phi _{1}$ and $\phi _{2}$ helps in the analysis of the ambipolar and analog behavior of the proposed device CP-dual metal-HG-DMaC-NWTFET. The reported ON-state current is $5.54~\mu \text{A}/\mu \text{m}$ , and the OFF-state current is approximately 0.1 aA/ $\mu \text{m}$ . The proposed device showed negligible ambipolar current (10−19 A/ $\mu \text{m}$ ) as negative bias increases to $V_{\mathbf {GS}} =-0.8$ V making the device compatible for low-voltage applications.

Enhanced Synaptic Linearity in ZnO-Based Invisible Memristive Synapse by Introducing Double Pulsing Scheme

Abstract: The synaptic plasticity of indium tin oxide (ITO)/ZnO/ITO highly transparent (more than 88%) analog switching resistive memory device is investigated. Highly stable analog switching behavior for more than 2500 cycles with a good memory window of approximately two orders makes it suitable for synapse application. The synaptic response is investigated by applying identical electrical pulses. The potentiation and depression of the device used the conventional identical single-pulse scheme to perform high nonlinearity (0.83) and decaying training epochs. However, the linearity and the training epochs are improved to 0.44 by implementing the identical double-pulse scheme. The proposed double-pulse scheme offers a broad dynamic range (200) having 320 conductance states. This invisible structure and double-pulse scheme can be highly suitable for the neuromorphic computing devices.

X-Ray Detector Based on All-Inorganic Lead-Free Cs 2 AgBiBr 6 Perovskite Single Crystal

Abstract: In this paper, single crystals (SCs) of the Cs2AgBiBr6 double perovskite were grown using the method of crystallization from a supersaturated solution. It was shown that the natural crystal growth surface of the perovskite with perfect crystal quality is along the (111) plane by X-ray diffraction (XRD) and high-resolution transmission electron microscope (HRTEM) analyses. The fabricated high-sensitivity X-ray detector based on the Cs2AgBiBr6 SCs with vertical structure achieved detection sensitivity up to $316~\mu $ CGyair−1 cm−2 under bias voltage of 18 V. Furthermore, the frequency noise characteristics of the device under different posttreatment processes were systematically analyzed, which indicated that the combination of thermal annealing and isopropanol rinsing can suppress field-driven ion migration and surface conduction channel, thereby increasing the resistivity of the perovskite material and reducing the noise current of the device. Our results revealed that the Cs2AgBiBr6 SCs-based X-ray detector with high sensitivity and low cost has a great potential for application in manufacturing lead-free and stable radiation detection electronics in the future.

Reliability of NAND Flash Arrays: A Review of What the 2-D–to–3-D Transition Meant

Abstract: This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future.

A Simulation-Based Comparison Between Si and SiC MOSFETs on Single-Event Burnout Susceptibility

Abstract: This paper presents the simulation-based comparison between silicon (Si) and silicon carbide (SiC) MOSFETs on the single-event burnout (SEB) performance for the first time. The safe operation areas (SOAs) regarding SEB are extracted and compared between the two structures when the heavy ions with a different linear energy transfer (LET) strike the sensitive areas of the devices. It is demonstrated that benefiting from the higher doped drift region, SiC MOSFET has a larger SEB threshold voltage than Si MOSFET at low LET range. However, it is the other way around at high LET range, which is attributed to the thicker epitaxy of Si MOSFET. The introduction of buffer layer to enhance the SEB hardness is also discussed. Results indicate that a thicker buffer layer is required for SiC MOSFET to enlarge the SOA, resulting in a more serious degradation of the specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ). Consequently, other hardening solutions need to be further explored to ensure the safe operation of SiC MOSFET in space applications.