Showing papers in "IEEE Transactions on Electron Devices in 2021"

1.2-kV Vertical GaN Fin-JFETs: High-Temperature Characteristics and Avalanche Capability

Abstract: This work describes the high-temperature performance and avalanche capability of normally- off 1.2-K V-CLASS vertical gallium nitride (GaN) fin-channel junction field-effect transistors (Fin-JFETs). The GaN Fin-JFETs were fabricated by NexGen Power Systems, Inc. on 100-mm GaN-on-GaN wafers. The threshold voltage ( ${V}_{\text {TH}}$ ) is over 2 V with less than 0.15 V shift from 25 °C to 200 °C. The specific ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) increases from 0.82 at 25 °C to 1.8 $\text{m}\Omega \cdot $ cm2 at 200 °C. The thermal stability of ${V}_{\text {TH}}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}}$ are superior to the values reported in SiC MOSFETs and JFETs. At 200 °C, the gate leakage and drain leakage currents remain below $100~\mu \text{A}$ at −7-V gate bias and 1200-V drain bias, respectively. The gate leakage current mechanism is consistent with carrier hopping across the lateral p-n junction. The high-bias drain leakage current can be well described by the Poole–Frenkel (PF) emission model. An avalanche breakdown voltage ( $BV_{\!\!\text {AVA}}$ ) with positive temperature coefficient is shown in both the quasi-static ${I}$ – ${V}$ sweep and the unclamped inductive switching (UIS) tests. The UIS tests also reveal a $BV_{\!\!\text {AVA}}$ over 1700 V and a critical avalanche energy ( ${E}_{\text {AVA}}$ ) of 7.44 J/cm2, with the ${E}_{\text {AVA}}$ comparable to that of state-of-the-art SiC MOSFETs. These results show the great potentials of vertical GaN Fin-JFETs for medium-voltage power electronics applications.

The Influence of Top and Bottom Metal Electrodes on Ferroelectricity of Hafnia

Abstract: In recent years, several experimental approaches have been adopted to study and understand the mechanism and improve the ferroelectricity of fluorite-type hafnia-based ferroelectric materials. In this regard, significant efforts have been made to elucidate the role of top electrode and bottom electrode (TE and BE) materials in defining the ferroelectricity in such systems, especially in terms of induced mechanical tensile stress by these materials during the process of annealing. However, the effect of the electrode material was not investigated both at TE and BE, and despite numerous efforts, there is still a lack of accurate and systematic understanding. In this report, we have carried out a systematic investigation on the effect of TE and BE materials having different coefficient of thermal expansion (CTE), by changing the electrode material one at a time, both at the top and bottom. The influence of the TE was confirmed using [TE/Hf0.5Zr0.5O2(HZO)/TiN] structure in which the BE was fixed as TiN, and the influence of the BE was confirmed using [TiN/HZO/BE] structure by fixing TiN as the TE. As revealed by polarization versus electric field and residual stress analysis, smaller CTE of the electrode was found to result in higher tensile stress in the HZO films during the annealing process, facilitating the formation of higher ferroelectric o-phase and thereby resulting in greater ferroelectricity. Although the influence of TE and BE on the ferroelectric property of HZO films was found to show similar trends according to the CTE value of the electrodes, the influence of TE on the ferroelectric property of the HZO capacitors is found to be mainly due to the variation in the induced mechanical tensile stress; pulse switching measurement and X-ray photoelectron spectrometer (XPS) analysis suggest that in case of BE, both the induced mechanical tensile stress and the interfacial dead layer were found to play a significant part. As a result, BE was found to have a greater influence on ferroelectricity of the HZO capacitors when compared with that of TE. The highest remnant polarization of 48.2 and $58.7~\mu \text{C}$ /cm2 was obtained for W with the lowest of CTE of $4.5\times 10^{-6}/^{\circ }\text{C}$ in both the configurations. The results obtained in this article are expected to provide a new way out to optimize the interface quality and ferroelectricity in HZO-based capacitors.

Artificial Neural Network-Based Compact Modeling Methodology for Advanced Transistors

Abstract: The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) and pathfinding activities. An ANN model architecture for FETs is introduced, and the results clearly show that by carefully choosing the conversion functions (i.e., from ANN outputs to device terminal currents or charges) and the loss functions for ANN training, ANN models can reproduce the current–voltage and charge–voltage characteristics of advanced FETs with excellent accuracy. A few key techniques are introduced in this work to enhance the capabilities of ANN models (e.g., model retargeting, variability modeling) and to improve ANN training efficiency and SPICE simulation turn-around-time (TAT). A systematical study on the impact of the ANN size on ANN model accuracy and SPICE simulation TAT is conducted, and an automated flow for generating optimum ANN models is proposed. The findings in this work suggest that the ANN-based methodology can be a promising compact modeling solution for advanced DTCO and pathfinding activities.

Ferroelectric Field Effect Transistors as a Synapse for Neuromorphic Application

Abstract: In spite of the increasing use of machine learning techniques, in-memory computing and hardware have increased the interest to accelerate neural network operation Henceforth, novel embedded nonvolatile memories (eNVMs) for highly scaled technology nodes, like ferroelectric field effect transistors (FeFETs), are heavily studied and very promising Furthermore, inference and on-chip learning can be fostered by further eNVM technology options, such as multibit operation and linear switching In this article, we present the advantages of hafnium oxide-based FeFETs for such purposes due to their basic three-terminal structure, which allows to selectively activate or deactivate selected devices as well as tune linearity and dynamic range for certain applications Furthermore, we discuss the impact of the material properties of the ferroelectric layer, the interface layer thickness, and scaling on the device performance Here, we demonstrate good device properties even for highly scaled devices ( $100\,\,nm \times 100$ nm)

Accurate Program/Verify Schemes of Resistive Switching Memory (RRAM) for In-Memory Neural Network Circuits

Abstract: Resistive switching memory (RRAM) is a promising technology for embedded memory and its application in computing. In particular, RRAM arrays can provide a convenient primitive for matrix–vector multiplication (MVM) with strong impact on the acceleration of neural networks for artificial intelligence (AI). At the same time, RRAM is affected by intrinsic conductance variations, which might cause degradation of accuracy in AI inference hardware. This work provides a detailed study of the multilevel-cell (MLC) programming of RRAM for neural network applications. We compare three MLC programming schemes and discuss their variations in terms of the different slopes in the programming characteristics. We test the accuracy of a two-layer fully connected neural network (FC-NN) as a function of the MLC scheme, the number of weight levels, and the weight mapping configuration. We find a tradeoff between the FC-NN accuracy, size, and current consumption. This work highlights the importance of a holistic approach to AI accelerators encompassing the device properties, the overall circuit performance, and the AI application specifications.

Realizing High-Performance β-Ga₂O₃ MOSFET by Using Variation of Lateral Doping: A TCAD Study

Abstract: In this article, for the first time, a variation of lateral doping (VLD) technique was proposed to improve blocking voltage and ON-resistance properties in the lateral $\beta $ -Ga2O3 metal–oxide–semiconductor field-effect transistor (MOSFET). Enhancement-mode operation was achieved in the VLD transistor. The maximum transconductance of this new device is more than three times as large as the uniformly doped (UD) transistor. Moreover, the OFF-state electric field at the channel was suppressed compared to the UD transistor, resulting in higher blocking voltage. We also investigated the optimal device properties with changing channel concentration in the drift region of VLD transistor. A power figure of merit of 332.7 MW/cm2 was reached by VLD design. Thus, this proposed structure provides a new design strategy for high-power $\beta $ -Ga2O3 MOSFETs.

Electrostatic Engineering Using Extreme Permittivity Materials for Ultra-Wide Bandgap Semiconductor Transistors

Abstract: The performance of ultra-wide bandgap semiconductors like ${\beta }$ -Ga2O3 is critically dependent on achieving high average electric fields within the active region of the device. In this article, we show that dielectrics like BaTiO3 with extremely high dielectric constant can provide an efficient field management strategy by improving the uniformity of electric field profile within the gate–drain region of lateral field-effect transistors. Using this strategy, we achieved high average breakdown field of 1.5 and 4 MV/cm at gate–drain spacing ( ${L}_{\text {gd}}$ ) of 6 and $0.5~{\mu }\text{m}$ , respectively in ${\beta }$ -Ga2O3, at a high channel sheet charge density of $1.6\,\,{\times }\,\,10^{{13}}$ cm−2. The high channel charge density along with the high breakdown field enabled a record power figure of merit ( ${V}_{\text {br}}^{{2}}/{R}_{\text {ON}}$ ) of 376 MW/cm2 at a gate–drain spacing of ${3}~{\mu }\text{m}$ .

Tunable Electronic Trap Energy in Sol-Gel Processed Dielectrics

Abstract: We demonstrate the electronic trap energy distribution ( $\Delta {E}_{IL}$ ) in the wide bandgap, nonconventional aluminum oxide phosphate (ALPO) dielectrics The trap energy distribution has been measured by using the gate injection high-speed capacitance–voltage measurement technique and verified through conventional deep-level transient spectroscopy The electronic trap energies in ALPO dielectrics were found to be influenced and, hence, tunable by the irradiation temperature The nonirradiated dielectric film (NI-ALPO) displayed the maximum number of electronic traps at an energy level of 02 eV below the conduction band of silicon (Si-ECB) On the other hand, the dielectric film irradiated at 200 °C confirmed the highest number of traps at the location of 0 eV and at the same energy level of Si-ECB In addition, the NI-ALPO dielectric contained over 90% of traps in the deep level of the bandgap (below Si-ECB) In contrast, the ALPO film irradiated at 200 °C accommodated a limited number of traps (~75%) at the deep level of the bandgap

Enhancement-Mode Atomic-Layer-Deposited In 2 O 3 Transistors With Maximum Drain Current of 2.2 A/mm at Drain Voltage of 0.7 V by Low-Temperature Annealing and Stability in Hydrogen Environment

Abstract: In this article, we demonstrate atomic-layer-deposited (ALD) indium oxide (In2O3) transistors with a record high drain current of 2.2 A/mm at ${V}_{DS}$ of 0.7 V among oxide semiconductor transistors with the enhancement-mode operation. The impact of back-end-of-line (BEOL) compatible low-temperature annealing is systematically studied on these highly scaled In2O3 transistors with channel length ( ${L}_{ch}$ ) down to 40 nm, channel thickness ( ${T}_{ch}$ ) down to 1.2 nm, and equivalent oxide thickness (EOTs) of 2.1 nm, at annealing temperatures from 250 °C to 350 °C in N2, O2, and forming gas (FG, 96% N2/4% H2) environments. Annealing in all different environments is found to significantly improve the performance of ALD In2O3 transistors, resulting in enhancement-mode operation, high mobility, reduced bulk and interface trap density ( $\text{D}_{it}$ as low as $6.3\times 10^{11}$ cm $^{-2}\cdot $ eV−1), and nearly ideal subthreshold slope (SS) of 63.8 mV/dec. Remarkably, the ALD In2O3 devices are found to be stable in hydrogen environment, being less affected by the well-known hydrogen doping issue in indium–gallium–tin-oxide (IGZO). Therefore, low-temperature ALD In2O3 transistors are highly compatible with the hydrogen-rich environment in BEOL fabrication processes.

Vertical GaN Power Devices: Device Principles and Fabrication Technologies—Part II

Abstract: Vertical gallium nitride (GaN) power devices are enabling next-generation power electronic devices and systems with higher energy efficiency, higher power density, faster switching, and smaller form factor. In Part I of this review, we have reviewed the basic design principles and physics of building blocks of vertical GaN power devices, i.e., Schottky barrier diodes and p-n diodes. Key topics such as materials engineering, device engineering, avalanche breakdown, and leakage mechanisms are discussed. In Part II of this review, several more advanced power rectifiers are discussed, including junction barrier Schottky (JBS) rectifiers, merged p-n/Schottky (MPS) rectifiers, and trench metal–insulator–semiconductor barrier Schottky (TMBS) rectifiers. Normally- OFF GaN power transistors have been realized in various advanced device structures, including current aperture vertical electron transistors (CAVETs), junction field-effect transistors (JFETs), metal–oxide–semiconductor field-effect transistors (MOSFETs), and fin field-effect transistors (FinFETs). A detailed analysis on their performance metrics is provided, with special emphasis on the impacts of key fabrication processes such as etching, ion implantation, and surface treatment. Lastly, exciting progress has been made on selective area doping and regrowth, a critical process for the fabrication of vertical GaN power devices. Various materials characterization techniques and surface treatments have proven to be beneficial in aiding this rapid development. This timely and comprehensive review summarizes the current progress, understanding, and challenges in vertical GaN power devices, which can serve as not only a gateway for those interested in the field but also a critical reference for researchers in the wide bandgap semiconductor and power electronics community.

“Hole Redistribution” Model Explaining the Thermally Activated R ON Stress/Recovery Transients in Carbon-Doped AlGaN/GaN Power MIS-HEMTs

Abstract: RON degradation due to stress in GaN-based power devices is a critical issue that limits, among other effects, long-term stable operation. Here, by means of 2-D device simulations, we show that the RON increase and decrease during stress and recovery experiments in carbon-doped AlGaN/GaN power metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) can be explained with a model based on the emission, redistribution, and retrapping of holes within the carbon-doped buffer (“hole redistribution” in short). By comparing simulation results with front- and back-gating OFF-state stress experiments, we provide an explanation for the puzzling observation of both stress and recovery transients being thermally activated with the same activation energy of about 0.9 eV. This finds a straightforward justification in a model in which both RON degradation and recovery processes are limited by hole emission by dominant carbon-related acceptors that are energetically located at about 0.9 eV from the GaN valence band.

Enhanced Charge Extraction in Metal–Perovskite–Metal Back-Contact Solar Cell Structure Through Electrostatic Doping: A Numerical Study

Abstract: In conventional perovskite solar cells (PSCs), a thin active layer of perovskite is sandwiched between two charge transport layers (CTLs)–electron transport layer (ETL) and hole transport layer (HTL). CTLs help in extracting and navigating the photogenerated electron–hole (e-h) pairs to the respective electrodes. Although this phenomenon gives high-energy conversion efficiencies but leads to quite a few performances as well as fabrication challenges. The ways to partially overcome these challenges are to have a device without the need of having CTLs altogether and opting for the back-contact (BC) design for PSCs. Dipole fields (DFs) present at the metal perovskite interface may be thought for their possible utilization to have CTL-free BC PSC. However, the performance of such devices is limited by the difference between the metal work functions across the perovskite layer. In this article, we report the results for our studies to establish that an electrostatically doped DF-assisted metal perovskite metal back-contact (ED-DF-MPM) PSC structure has the ability to overcome the limitations of DF-assisted metal perovskite metal back-contact (DF-MPM) PSCs. As a part of the work carried out here, ED p-n-junction and corresponding built-in potential have been combined for DF-assisted extraction of generated carriers within the perovskite layer so as to enhance the collection probability and open-circuit voltage. Quantitively, 32.7%, 10.6%, and 8.6% improvement in short-circuit current density ( ${J}_{SC}$ ), open-circuit voltage ( ${V}_{OC}$ ), and fill factor (FF) are obtained, respectively, which resulted in an observation of 59.4% improvement in power conversion efficiency (PCE) for ED-DF-MPM PSC compared to DF-MPM PSC. Besides that, the reported ED-DF-MPM PSC structure delivers the photovoltage and photocurrent of 659 mV and 14.19 mA $\cdot $ cm−2, respectively. The work reported in this article may pave the way for the development of “transport layer-free” ED scalable and low-cost PSCs in future.

High Breakdown Voltage and Low-Current Dispersion in AlGaN/GaN HEMTs With High-Quality AlN Buffer Layer

Abstract: We have successfully grown AlGaN/GaN high electron mobility transistor (HEMT) structure on the high-quality undoped thick AlN buffer layer with large band offset to replace the conventional high-resistivity GaN buffer layer. The AlGaN/GaN HEMT fabricated on this AlN buffer layer exhibits low OFF-state leakage current with high ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ of $\sim 10^{{6}}$ due to enhanced confinement of the electrons in the 2-D electron gas (2-DEG) channel. The undoped AlN buffer layer is responsible for suppressing the trapping effects to greatly reduce the current dispersion in pulsed ${I}_{\text {D}}$ – ${V}_{\text {D}}$ characteristics, which is hardly avoided in conventional deep acceptor-doped GaN buffer layer. The device also demonstrates high breakdown voltage of 2154 V with very high figure of merit (FOM) of ~1.8 GV $^{2-1}$ cm $^{-{2}}$ , one of the highest ever reported, suggesting that the AlGaN/GaN-based Hemts WITH AlN buffer layer are promising for high-performance RF and power applications.

A Highly Scalable Junctionless FET Leaky Integrate-and-Fire Neuron for Spiking Neural Networks

Abstract: In this article, a highly scalable and CMOS compatible double-gate junctionless field-effect transistor (DG-JLFET)-based leaky integrate-and-fire (LIF) neuron is presented for the sub-20 nm gate length which is the smallest reported until now. Using well-calibrated 2-D TCAD simulations, we demonstrated that DG-JLFET LIF is able to mimic biological neuronal behavior. The DG-JLFET LIF neuron shows a low threshold voltage ( $\boldsymbol -0.31$ V) for firing a spike and requires 1.14 pJ of energy per spike which is $\sim 32\times $ less than partially depleted silicon-on-insulator (PD-SOI) MOSFET LIF neuron. The proposed neuron needs only 0.4 V of supply voltage that is $\sim 7\times $ , $7.5\times $ , $5\times $ , and $2\times $ lower as compared to its counterpart PD-SOI MOSFET, FinFET, L-shaped bipolar impact ionization MOS (LBIMOS), and Si NIPIN Diode-based LIF neurons, respectively. In addition, at a gate length of 10 nm the DG-JLFET LIF requires 0.07 pJ of energy per spike, which is $\sim 500\times $ , $\sim 642\times $ , and $\sim 86\times $ lower than that of the PD-SOI MOSFET, single MOSFET and Biristor based LIF neurons, respectively. Moreover, the DG-JLFET LIF neuron shows spiking frequency in the range of megahertz, which is ~5 orders high compared to the biological neuron. The absence of metallurgical junctions in DG-JLFET eases the fabrication complexity and cuts down the thermal budget requirement.

1300 V Normally-OFF p-GaN Gate HEMTs on Si With High ON-State Drain Current

Abstract: In this article, we demonstrate normally-OFF p-GaN gate high electron mobility transistors (HEMTs) on Si with an ultrahigh breakdown voltage ( ${V}_{BR}$ ) and excellent saturation drain current. Benefiting from the optimized material growth of high-resistivity buffer, effective Al2O3 surface passivation with suppressed OFF-state leakage current, and proper management of the electric field on the p-GaN gate edge, the device with a gate–drain distance of $18.5~\mu \text{m}$ exhibits a ${V}_{BR}$ of 1344 V at ${I}_{D}$ of $1~\mu \text{A}$ /mm with grounded substrates, the highest among all the reported normally-OFF GaN-on-Si transistors. Well-restored high-density 2-D electron gas and efficient gate modulation enable the device with a high ${I}_{DS,max}$ of 450 mA/mm and a low specific ON-resistance of 3.92 $\text{m}\Omega \cdot $ cm2. Moreover, a large threshold voltage of 1.6 V (at ${I}_{D}$ of $10~\mu \text{A}$ /mm) and a steep subthreshold slope of 66 mV/dec have been achieved, with negligible threshold voltage shift upon long-term forward gate stress at 150 °C. These results illustrate the great potential of p-GaN gate HEMTs on Si for beyond 600-V applications.

Computational Investigation of Negative Capacitance Coaxially Gated Carbon Nanotube Field-Effect Transistors

Abstract: In this article, we present a computational investigation on nanoscale coaxial-gate negative-capacitance carbon nanotube field-effect transistor (NC CNTFET). The proposed nanodevice is endowed with metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. The simulation approach is based on solving self-consistently the nonequilibrium Green’s function formalism with the NC FET electrostatics considering ballistic transport conditions. The computational assessment includes the switching performance and short-channel effects (SCEs) in NC CNTFETs. The negative capacitance behavior of the ferroelectric has been found efficient in boosting the performance of nanoscale CNTFETs in terms of subthreshold swing (SS), drain-induced barrier lowering (DIBL), ON-current, current ratio, and intrinsic delay. In addition, we show the capability of MFMIS configuration in improving the current ratio and SS of CNTFETs with ultrascaled gate lengths. The role of the ferroelectric layer thickness in enhancing the NC CNTFET performance is also studied, where improved performance has been recorded using thicker ferroelectric layer. Achieving high ${I} _{ \mathrm{ON}}/{I} _{ \mathrm{OFF}}$ current ratio, sub- kT SS, and improved immunity against SCEs makes the NC CNTFET as a potential candidate for modern CNT-based nanoelectronics.

A Comprehensive Study of Nanosheet and Forksheet SRAM for Beyond N5 Node

Abstract: SRAM bitcell area reduction, lower SRAM parasitic resistance, and higher drive strength are necessary to continue with technology scaling. Nanosheet (NSH) technology improves SRAM cell write-ability by having 50 mV more write trip point (WTP) than FinFET (FF) SRAM due to reduced bit line (BL) resistance (due to wider metal CD) and more drive current strength (more than 15%) than FF for the same leakage. However, due to higher bitcell area (20% larger), BL, and word line (WL) parasitic capacitance than FF, NSH SRAM would not compete with FF SRAM in terms of the read delay (26% more delay) and energy at the 3-nm technology node. PFET to NFET (PN) spacing, composed of gate cut, gate extension, and Fin pitch in an SRAM bitcell, is critical for SRAM cell height because it can take ~46% of the 111 SRAM total cell height. The forksheet (FSH), achieving extremely scaled PN space in SRAM bitcell due to device structure with limited additional processing complexity, reduces the SRAM bitcell area. As a result, BL and WL parasitics reduce and improve the SRAM read delay and stability. FSH SRAM saves 6% area benefit and achieves 24% lesser read delay than FF high density (HD) SRAM.

Characteristics of Stacked Gate-All-Around Si Nanosheet MOSFETs With Metal Sidewall Source/Drain and Their Impacts on CMOS Circuit Properties

Abstract: In this brief, we computationally examine electrical characteristics of stacked gate-all-around Si nanosheet MOSFETs (GAA NS-FETs) with and without metal sidewall (MSW) source/drain (S/D) by increasing the number of channels (NCs) and their impacts on digital circuits. The ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) and circuit performances of the NS-FETs without the MSW S/D are limited to three channels due to the electrostatic potential decreasing from the top contacts to the bottom S/D side of NS-FETs; however, the MSW S/D can improve the ${I}_{\text {on}}$ with increasing the NCs over three channels because of low resistivity of tungsten ( $5.6\times 10^{-{6}}\,\, \Omega \cdot \text {cm}$ ) in the sidewall of S/D and then the circuit performances can be boost by the MSW S/D structure of the stacked GAA NS-FETs over three channels. For example, up to six channels of the NS-FETs with the MSW S/D, the frequency of ring oscillator is 57% increase, compared with the case without MSW S/D. The results of this study can be considered to design the S/D structure of the stacked GAA NS-FETs in emerging device technologies.

Study on 1-THz Sine Waveguide Traveling-Wave Tube

Abstract: In this article, a 1-THz traveling-wave tube (TWT) based on flat-roofed sine waveguide (SWG) slow wave structure (SWS) has been studied theoretically and experimentally, and parts of the component have been fabricated First, the flat-roofed SWG SWS has been optimized for working at 1 THz, the normalized phase velocity is around 0287, and the interaction impedance is over $35~\Omega $ in the frequency range of 102–104 THz Meanwhile, the performance of the designed TWT has been simulated, whose saturated output power is 720 mW and the corresponding gain is 2857 dB What is more, to decrease the transmission loss of the high-frequency structure, the input and output structures have been designed and a transition structure that transforms the waveguide to standard rectangular waveguide has been proposed The simulation results show that the reflection coefficient of the novel proposed transmission system is less than −20 dB, and the insertion losses of the transition structure with the input and output waveguides are 245 and 168 dB, respectively Finally, the designed SWS has been fabricated by deep reactive-ion etching (DRIE) and tested; ${S}_{{11}}$ is generally less than −10 dB in the frequency range of 1020–1040 GHz

Revisiting the Time-Domain and Frequency-Domain Definitions of Capacitance

Abstract: The capacitance is a characteristic function of an electrical energy storage device that relates the applied voltage on the device to the accumulated electric charge. It is inconsistently taken in some studies as a multiplicative function in the time domain [i.e., ${q}_{t}{(}{t}{)}={c}_{t}{(}{t}{)} \times {v}_{t}{(}{t}{)}$ ], and in others as a multiplicative function in the frequency domain [i.e., ${Q}_{f}{(}{s}{)}={C}_{f}{(}{s}{)} \times \, {V}_{f}{(}{s}{)}$ derived from the definition of admittance ${I}_{f}{(}{s}{)}/{V}_{f}{(}{s}{)} = {s} {C}_{f}{(}{s}{)}$ ], despite the fact that the capacitance is time- and frequency-dependent. However, the convolution theorem states that multiplication of functions in the time domain is equivalent to a convolution operation in the frequency domain, and vice versa. In this work, we revisit and compare the two outlined definitions of capacitance for an ideal capacitor and for a lossy fractional-order capacitor. Although ${c}_{t}{(}{t}{)} = {C}_{f}{(}{s}{)} = {C}$ for an ideal constant capacitor, we show that this is not the case for fractional-order capacitors which exhibit frequency-dispersed impedance, memory effects, and nonexponential relaxation functions. This fact is crucial in the accurate modeling and characterization of supercapacitors and batteries. For these devices, and for being consistent with measurements using conventional impedance analyzers, it is recommended to apply the integral convolution definition in the time domain which reverts to the multiplicative definition in the frequency domain.

Compact Modeling of Temperature Effects in FDSOI and FinFET Devices Down to Cryogenic Temperatures

Abstract: We present compact models that capture published cryogenic temperature effects on silicon carrier mobility and velocity saturation, as well as fully depleted silicon on insulator (FDSOI) and fin field effect transistor (FinFET) devices characteristics within the industry-standard Berkeley short-channel IGFET model (BSIM) framework for cryogenic IC applications such as quantum computing. For the core model charge density/surface potential calculation, we introduce an effective temperature formulation to capture the effects of the band tail states. We also present a compact model that corrects the low-temperature threshold voltage for the band-tail states, Fermi–Dirac statistics, and interface traps. New temperature-dependent mobility and velocity saturation models are accurate down to cryogenic temperature. In addition, we propose that experimentally observed ${I}_{D}$ dependence of subthreshold swing (SS) at cryogenic temperatures is a consequence of the expectedly higher rate of Coulomb scattering of free carriers.

Laser-Induced Graphene Printed Wearable Flexible Antenna-Based Strain Sensor for Wireless Human Motion Monitoring

Abstract: Leveraging laser-induced graphene (LIG) in various flexible polymer electronics applications is becoming tremendously popular. LIG is porous multilayer graphene generated by a single-step process using infrared CO2 laser onto the carbon-based polymers. In this article, a direct LIG printed microstrip patch antenna operating at the 5.8-GHz unlicensed band is presented. Based on simulations, the proposed design exhibited the desired unidirectional radiation characteristics with a measured gain of 1.82 dBi at the resonant frequency. The LIG-based rectangular patch was printed using the CO2 laser by selective reduction of polyimide (PI) sheet. The chemical properties of LIG were examined using various structural and morphological characterization techniques, which confirmed the formation of multilayer graphene. The sensitivity of the patch antenna was analyzed for measuring strain and its effect on LIG. By harnessing LIG on flexible material such as PI sheet, the antenna exhibited a threshold increase in sensitivity. The proposed sensor shows a sensitivity of 14.08 and 11.34 for compressive and tensile strain, respectively. Inspired by the significant sensitivity, the fabricated device has been examined for human motion monitoring by attaching it to the human hand for practical usage in real-time applications. The proposed antenna-based sensor reduces the number of components by eliminating external wiring and onboard battery. Moreover, it serves as both the sensing and wireless data transmitting element. Overall, this work demonstrates designing a compact, easy-to-fabricate, sensitive, and flexible antenna-based Internet of Things (IoT) sensor for motion detection, structural health monitoring, and industrial strain sensing applications.

Applying Conformal Mapping to Derive Analytical Solutions of Space-Charge-Limited Current Density for Various Geometries

Abstract: While exact analytic solutions for space-charge-limited currents (SCLCs) are well-established for parallel plate geometries, they have only recently been derived for concentric cylindrical and spherical geometries using variational calculus (VC). However, actual diode systems and slow-wave structures are usually more complicated, making SCLC calculations more difficult. In this article, we apply conformal mapping to derive the analytical solutions for SCLC for various complicated geometries exhibiting curvilinear flow. We first replicate the exact solution of SCLC for concentric cylindrical electrodes from VC using conformal mapping to transform from the Child–Langmuir (CL) law for a planar geometry. We then derive SCLC in other geometries using conformal transformations to either the planar or the concentric cylinder solution. Because the SCLC calculated using such conformal mappings depends only on the CL law, this may permit future incorporation of relativistic or quantum corrections to determine the appropriate relationships for more complicated geometries.

Physical Modeling of Charge Trapping in 4H-SiC DMOSFET Technologies

Abstract: Silicon carbide (SiC) MOSFETs still exhibit higher drifts of the threshold voltage than comparable silicon devices due to charge trapping, especially regarding small time scales. Understanding this behavior and the consequences in application relevant conditions is therefore of high research interest. Since charge trapping at different defects close to the SiC/ SiO2 interface and in the bulk oxide is strong bias and temperature-dependent, the phenomenon is referred to as bias temperature instability (BTI). It has been shown that drifts caused by BTI vary both in transient shape and magnitude for commercially available devices. These differences arise from defect densities and properties in the respective technologies. A physical model together with defect parameters that explain the charge transfer reactions at the defects is essential to understand all peculiarities of the transient degradation. In this work, we use a novel method to semiautomatically extract defect parameters within a two-state nonradiative multiphonon model framework. Our work reveals properties of defects responsible for shifts of the threshold voltage for both short-term ac and long-term dc stress conditions which are accurately reproduced for three different DMOS technologies. Our calibrated simulation framework is further used to extrapolate device degradation at operation relevant ac bias conditions to typical device lifetimes.

A Novel Physics-Based Approach to Analyze and Model E -Mode p-GaN Power HEMTs

Abstract: In this article, a physics-based analytical model which considers the channel charge ( ${\mathrm {Q}}_{{\mathrm {ch}}}$ ) for enhancement-mode p-GaN power high-electron-mobility transistors (HEMTs) is developed. First, by considering the same dynamic channel charge ( ${\mathrm {dQ}}_{{\mathrm {ch}}}$ ) for the Schottky/p-GaN junction capacitance ( ${\mathrm {C}}_{{\mathrm {j,Sch}}}$ ) and the p-i-n-junction capacitance ( ${\mathrm {C}}_{{\mathrm {p-i-n}}}$ ), due to the p-GaN/AlGaN junction and two-dimensional electron gas (2DEG) charge, the analytical formula to calculate the voltage drop in the p-GaN layer ( ${\mathrm {V}}_{{\mathrm {pGaN}}}$ ) is presented. Second, by implementing the analytical formulae in the advanced SPICE model (ASM) GaN model, the proposed physics-based model reliably fits the measured ${C}$ – ${V}$ and ${I}_{{\mathrm {D}}}$ – ${V}_{{\mathrm {G}}}$ characteristics of the samples under different processing conditions. This provides significant insight regarding the Mg concentration, the voltage drop at the Schottky metal/p-GaN junction ( ${\mathrm {V}}_{{\mathrm {j,Sch}}}$ ), and the voltage drop at the p-GaN/AlGaN junction ( ${\mathrm {V}}_{{\mathrm {p-i-n}}}$ ). Finally, the ${I}_{{\mathrm {D}}}$ – ${V}_{{\mathrm {G}}}$ and ${I}_{{\mathrm {D}}}$ – ${V}_{{\mathrm {D}}}$ characteristics of enhancement-mode p-GaN power HEMTs are modeled, displaying good agreement with the experimental data.

Soft-Error Resilient Read Decoupled SRAM With Multi-Node Upset Recovery for Space Applications

Abstract: Space consists of high-energy particles and high-temperature fluctuations, which causes single event upsets (SEUs). Conventional 6T static random access memory (SRAM) is unable to tolerate this harsh environment in space. Therefore, it is necessary to design an SRAM, which can withstand this harsh environment. In order to mitigate SEUs, a radiation-hardened SRAM cell, named soft-error resilient read decoupled 12T (SRRD12T), is presented in this article. To estimate the relative performance of the proposed cell, it is compared with other contemporary designs, such as RHMN12T, RHMP12T, RHD12T, QUCCE12T, and QUATRO12T, over various important design metrics. SRRD12T can not only recover from SEU induced at any of its sensitive nodes but also from single event multi-node upsets (SEMNUs) induced at its storage node pair. Furthermore, due to the read decoupled design of SRRD12T, it exhibits the highest read stability. In addition to these, SRRD12T shows $1.14\times /1.17\times $ shorter write delay than RHD12T/RHMP12T. Moreover, SRRD12T consumes lower hold power and exhibits higher write ability than most of the comparison cells. However, these advantages are obtained by exhibiting a slightly longer read delay.

FDTD-Based Optimization of Geometrical Parameters and Material Properties for GaAs-Truncated Nanopyramid Solar Cells

Abstract: Solar cells (SCs) based on semiconductor nanostructures with the distinctive potential of significant savings in material and effective control over light trapping and scattering processes provide a pathway to low-cost and high-efficiency next-generation SCs. To realize efficient light harvesting and reduced reflection and transmission loss of the nanostructures, the geometrical parameters and material properties must be deliberately optimized. In this article, for SCs based on vertically aligned GaAs-truncated nanopyramids, using the 3-D finite-difference time-domain (FDTD) method, we have examined the optimization study of geometrical and material parameters, including base-width, period, top-surface flatness, carrier mobility and lifetime, doping concentration, and surface recombination, to achieve absorption enhancement and in turn optimum photovoltaic parameters. The optimized structure has exhibited an efficiency of 19.16% despite considering low carrier mobility of 1000 cm $^{2}\,\,\text{V}^{-1}\,\,\text{s}^{-1}$ and lifetime of 3 nanoseconds, with heavily doped core ( $\sim 4\times 10^{17}$ cm−3) and substrate ( $\sim 1\times 10^{19}$ cm−3) and surface recombination velocity of 105cm/s at the contacts.

TCAD-Augmented Machine Learning With and Without Domain Expertise

Abstract: In this article, using experimental data, we demonstrate that the technology computer-aided design (TCAD) is a very cost-effective tool to generate the data to build machine learning (ML) models for semiconductor device and process characterization. Characterization of the emerging ultra wide bandgap gallium oxide (Ga2O3) Schottky barrier diode (SBD) is used as an example. Machines are trained by using only TCAD ${I}$ – ${V}$ ’s and then used to deduce the effective Schottky metal work function (WF) and ambient temperature ( ${T}$ ) of an experimental SBD based on its ${I}$ – ${V}$ . Besides noise, the experimental device also suffers from relatively large variations in drift layer thickness and doping concentrations. Both ML models with domain expertise (WDE) and without domain expertise (WoDE) are studied and compared. The ML model WDE requires the use of device knowledge to extract relevant features (e.g., subthreshold slope and turn-on voltage) for ML. The ML model WoDE obviates such a requirement and can be extended to cases where domain expertise is difficult to apply. Denois- ing autoencoder is used in the WoDE case. We showed that with only 500 TCAD ${I}$ – ${V}$ ’s, we can train machines WDE and WoDE that can deduce the experimental device WF and ${T}$ reasonably well. In particular, the ML model WoDE has an acceptable prediction accuracy despite the noise and additional variations in the experimental device.

16 × 4 Linear Solar-Blind UV Photoconductive Detector Array Based on β-Ga 2 O 3 Film

Abstract: In this article, a $16\times4$ linear array of $\beta $ -Ga2O3-based metal-semiconductor-metal structured photodetector is described for solar-blind sensing operation at a wavelength of 254 nm. The $\beta-\mathrm{Ga}_{2} \mathrm{O}_{3}$ film is grown by using metal-organic chemical vapor deposition (MOCVD) equipment, and the photodetectors are finished in constructing with standard photolithography and ion beam sputtering procedures. The results show that the dark current ( ${\mathrm {I}}_{{dark }}$ ), photo-to-dark current ratio (PDCR), photo responsivity (R), specific detectivity $\left(D^{*}\right)$ , exterl quantum efficiency (EQE), and linear dynamic region (LDR) are 1.94 pA, $2.95 \times 10^{7}$ , 139.56 A/W, $2.55 \times 10^{15}$ Jones, $6.8 \times 10^{4 \%}$ , and 149.4 dB, at 10 V bias and $2000 \mu \mathrm{W} / \mathrm{cm}^{2}$ light intensity illumination. In addition, the standard deviation of $R$ for this photodetector array is 10%. Overall, such a $16 \times 4$ linear array of $\beta-\mathrm{Ga}_{2} \mathrm{O}_{3}$ -based photodetector array makes a progress in the field of Ga2O3 photodetectors.

Synergistic Modulation of Synaptic Plasticity in IGZO-Based Photoelectric Neuromorphic TFTs

Abstract: Neuromorphic devices are of great significance for next generation energy-efficient brain-like computing and perception. Oxide-based photoelectric neuromorphic transistors are very promising due to the proton-related electric-double-layer (EDL) effect and persistent photoconductivity behavior. In this study, indium-gallium-zinc-oxide (IGZO)-based photoelectric neuromorphic thin-film transistors (TFTs) with tunable synaptic plasticity are proposed. Some important synaptic functions, such as excitatory postsynaptic current, multipulse facilitation, and long-term plasticity, can be effectively tuned by the photoelectric synergistic modulation. More importantly, under the photoelectric synergistic modulation, the temporary short-term memory can be converted into permanent long-term memory. And the voltage coordinated modulation can enhance the image in the pixel and the ability of real-time data processing of the input visual information. Our results are very important for the development of photoelectric neuromorphic devices with configurable dynamic functions.