Journal•ISSN: 0367-7508

# IEEE Transactions on Electronic Computers

About: IEEE Transactions on Electronic Computers is an academic journal. The journal publishes majorly in the area(s): Boolean function & Analog computer. It has an ISSN identifier of 0367-7508. Over the lifetime, 694 publication(s) have been published receiving 18185 citation(s).

##### Papers

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TL;DR: It is shown that a family of surfaces having d degrees of freedom has a natural separating capacity of 2d pattern vectors, thus extending and unifying results of Winder and others on the pattern-separating capacity of hyperplanes.

Abstract: This paper develops the separating capacities of families of nonlinear decision surfaces by a direct application of a theorem in classical combinatorial geometry. It is shown that a family of surfaces having d degrees of freedom has a natural separating capacity of 2d pattern vectors, thus extending and unifying results of Winder and others on the pattern-separating capacity of hyperplanes. Applying these ideas to the vertices of a binary n-cube yields bounds on the number of spherically, quadratically, and, in general, nonlinearly separable Boolean functions of n variables. It is shown that the set of all surfaces which separate a dichotomy of an infinite, random, separable set of pattern vectors can be characterized, on the average, by a subset of only 2d extreme pattern vectors. In addition, the problem of generalizing the classifications on a labeled set of pattern points to the classification of a new point is defined, and it is found that the probability of ambiguous generalization is large unless the number of training patterns exceeds the capacity of the set of separating surfaces.

1,840 citations

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TL;DR: A design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step, using straightforward diode-transistor logic.

Abstract: It is suggested that the economics of present large-scale scientific computers could benefit from a greater investment in hardware to mechanize multiplication and division than is now common. As a move in this direction, a design is developed for a multiplier which generates the product of two numbers using purely combinational logic, i.e., in one gating step. Using straightforward diode-transistor logic, it appears presently possible to obtain products in under 1, ?sec, and quotients in 3 ?sec. A rapid square-root process is also outlined. Approximate component counts are given for the proposed design, and it is found that the cost of the unit would be about 10 per cent of the cost of a modern large-scale computer.

1,650 citations

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TL;DR: This paper treats the problem of automatic fault diagnosis for systems with multiple faults by means of a given arrangement of testing links (connection assignment), and a proper diagnosis can be arrived at for any diagnosable fault pattern.

Abstract: This paper treats the problem of automatic fault diagnosis for systems with multiple faults. The system is decomposed into n units u 1 , u 2 , . . . , u n , where a unit is a well-identifiable portion of the system which cannot be further decomposed for the purpose of diagnosis. By means of a given arrangement of testing links (connection assignment) each unit of the system tests a subset of units, and a proper diagnosis can be arrived at for any diagnosable fault pattern. Methods for optimal assignments are given for instantaneous and sequential diagnosis procedures.

1,321 citations

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General Electric

^{1}TL;DR: A set of conditions are described which determine whether or not two successive portions of a given program can be performed in parallel and still produce the same results.

Abstract: A set of conditions are described which determine whether or not two successive portions of a given program can be performed in parallel and still produce the same results. The conditions are general and can be applied to sections of the program of arbitrary size. The conditions are interesting because of the light they shed on the structure of programs amenable to parallel processing and the memory organization of a multi-computer system.

442 citations

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TL;DR: The author develops an adder tree to sum this set when t= 1 the maximum number of regions intersections of n t-flats and shows that a tree will be dependent on both t and n.

Abstract: will be less than Cnt+1(t+1)! but may be space into which the latter may be divided multiplier into twenty 2-bit segments. He (and usually will be) more than (t+2)!. by a maximum possible number of mutual then develops an adder tree to sum this set When t= 1 the maximum number of regions intersections of n t-flats. In general, q will be of twenty entries. He then shows that a tree will be dependent on both t and n. It is first shown of nineteen adders (I believe twenty are

429 citations