Showing papers in "IEEE Transactions on Electronic Computers in 1965"

Geometrical and Statistical Properties of Systems of Linear Inequalities with Applications in Pattern Recognition

Abstract: This paper develops the separating capacities of families of nonlinear decision surfaces by a direct application of a theorem in classical combinatorial geometry. It is shown that a family of surfaces having d degrees of freedom has a natural separating capacity of 2d pattern vectors, thus extending and unifying results of Winder and others on the pattern-separating capacity of hyperplanes. Applying these ideas to the vertices of a binary n-cube yields bounds on the number of spherically, quadratically, and, in general, nonlinearly separable Boolean functions of n variables. It is shown that the set of all surfaces which separate a dichotomy of an infinite, random, separable set of pattern vectors can be characterized, on the average, by a subset of only 2d extreme pattern vectors. In addition, the problem of generalizing the classifications on a labeled set of pattern points to the classification of a new point is defined, and it is found that the probability of ambiguous generalization is large unless the number of training patterns exceeds the capacity of the set of separating surfaces.

An Algorithm for Linear Inequalities and its Applications

Abstract: An exponentially convergent and finite algorithm is presented for the determination of the solution ? of the linear inequalities A?≫0 for a given matrix A, or for determining the non-existence of solution for A?≫0. This result is useful in threshold-switching theory and in pattern classification problems. Experiments indicate extremely rapid convergence of the method.

On an Improved Diagnosis Program

Abstract: One of the more promising areas of computer use involves the coupling of a man to a computer system for real-time problem-solving where the procedure for solution of the problem is either unknown or involves complex tasks, such as pattern recognition, that can best be performed by humans [1]. Unfortunately, a straightforward approach to such use commits significant amounts of computer time most of which is spent idling. The imbalance in operating costs, assignable to the human and the computer, argues against computer use unless the total gain over strictly manual operations is sufficiently great.

A Method for Minimizing the Number of Internal States in Incompletely Specified Sequential Networks

Abstract: A method is illustrated for minimizing the number of internal states in incompletely specified sequential networks. The minimization algorithm applies to any type of incompletely specified flow table. It is shown that only some compatibility classes (prime compatibility classes) need be considered as members of a solution. The selection of prime classes may be obtained as the solution of an integer linear program or by tabular techniques that are an extension of those used in the selection of prime implicants.

Computation of the Base Two Logarithm of Binary Numbers

Abstract: An approximation to the computation of the base two logarithm of a binary number, realized with binary circuitry, is described. It is known that the logarithm can be obtained approximately from the binary number itself by simple counting and shifting. A method for the reduction of the resulting approximation error by a factor six is given. The same principle can be used for further reduction of the error. The realization involving not only counting and shifting but also binary decision making and addition is described. Technical data about the performance of the constructed computer are given.

Enumeration of Seven-Argument Threshold Functions

Abstract: A tabulation of the 2470 representative threshold functions of seven arguments has been prepared by the author. This paper discusses the methods used in, and the threshold logic implications of, the enumeration. The self-dual classification method of Goto-Takahasi was employed. A lattice was defined on the 8-cube in terms of which all 2-monotonic, canonical, self-dual functions of eight arguments were directly generated. Each such representative function was then treated by a modified form of the Muroga-Toda-Takasu linear programming test-synthesis procedure to obtain minimal 1-realizations. The Chow parameters for each function were calculated, and the final enumeration was ordered lexicographically by these parameters to afford a trivial test-synthesis procedure for n?7. The enumeration demonstrated that minimal 1-realizations are still integral for n?7; it corroborated Cobham's result that complete monotonicity is equivalent to 1-realizability, and established hyper-2-monotonicity as a useful characterization, for n?7. It significantly extended our knowledge of the number of threshold functions and the various symmetry types, the size of weights and threshold required, the number of iterations required by the linear program, and similar statistics.

Slave Memories and Dynamic Storage Allocation

Abstract: The use is discussed of a fast core memory of, say, 32000 words as a slave to a slower core memory of, say, one million words in such a way that in practical cases the effective access time is nearer that of the fast memory than that of the slow memory.

A One-Dimensional Real-Time Iterative Multiplier

Abstract: The class of one-dimensional, real-time, iterative, discrete-state automata is described. By example, it is shown that serial multiplication can be carried out by such a sequential switching network. Each of two arbitrarily large integers is represented in binary notation by a time sequence of digits 0 or 1, the lowest order digits first. A design is given for a discrete-state machine that has as input the two time sequences of binary digits and as output a single sequence of binary digits, which is the product of the two input integers, lowest-order digit first. The multiplier is constrained to be a linear array of identical cells. The cells each have a finite number of states and each cell communicates directly only with the adjacent cells, such communications occurring in a synchronous manner. The multiplication is performed in real time; that is, the delay between the receipt of the nth digits of the input and the generation of the nth digit of the output is a fixed number of periods of the synchronizing clock. A design with no time delay is described.

Logical Design of Ternary Switching Circuits

Abstract: A logical design theory for ternary voltage switching circuits is developed. The theory is based on familiar binary switching circuit elements and simplification methods. The theory thus leads to simple electronic realization. The basic system of ternary switching elements consists of function realizable by means of either diode gates or a single triode (transistor). Various simplification methods for combinational circuits are described, namely a map method and two algebraic methods. The first algebraic method is an adaptation of the Quine method for determining the prime implicants of a given binary function, and the second is a modification of the Scheinman binary method.

Statistical Independence and Threshold Functions

Abstract: The memory we describe here is a logical and practical outgrowth of the content addressable distributed logic memory of Lee and Paull.1 However, there are several significant differences: the inclusion of a "match" flip-flop and a "control" flip-flop in each cell of the memory, the addition of a "Mark" line to activate many cells simultaneously, and the control of the propagation of the marking signal. As a consequence of these, the memory has some novel capabilities, among which are the ability to simultaneously shift the contents of a large group of cells, thus opening or closing a gap in the memory, and the ability to simultaneously mark strings of interest in separate parts of the memory.

On Information Lossless Automata of Finite Order

Abstract: A coding graph is a model which contains all the types of finite automata and codes as special cases. A test for information losslessness and for information losslessness of finite order of a coding graph is described. Efficient methods of computation are given which make the calculation simple and mechanizable. The application of the tests to finite deterministic automata is discussed and a method of constructing a decoder for a given finite automaton that is information lossless of finite order, is described.

An Algorithm for Selecting an Optimum Set of Diagnostic Tests

Abstract: In the design of combinational diagnostic testing procedure for a large digital system, some redundant tests are expected. This paper describes an algorithm for selecting a good (locally optimized) set of diagnostic tests which contains no redundancy. The algorithm will in general tend to give a ``fairly good'' set of test patterns, but is not guaranteed to be absolutely minimal. An overall optimization scheme is desirable but seems impractical [1]. The procedure described can be used either to yield a set of diagnostics which loses no resolution from the full set, or to yield a smaller set with some loss in resolution.

A Reduction Technique for Prime Implicant Tables

Abstract: Solving prime implicant tables is greatly facilitated by reduction techniques such as row dominance, column dominance, and essential row selection. This paper presents a new reduction technique which is operable on any otherwise irreducible table having a column covered by exactly two rows.

Synthesis of Minimal Threshold Logic Networks

Abstract: An algorithm is developed for synthesizing networks which realize Boolean switching functions through the use of a minimum number of threshold logic elements. A switching function is represented by a matrix and the algorithm is based on the principle that the removal of the positive linear dependences from the rows of this matrix results in a linearly separable function. The positive linear dependences are removed by adding columns to the matrix, each column representing the output of a threshold logic element in the network. The added columns in effect transform a nonseparable function into a sparable function a higher dimensional space. The algorithm is illustrated with examples of the synthesis of both single and multiple output networks. The technique is not restricted to completely specified functions.

Bulk Processing in Distributed Logic Memory

Abstract: Use of a content-addressable memory as a highly parallel digital computer is described. The ability to perform any arithmetic operation on many sets of data at the same time is shown. The memory organization and the storage of data are such that many operations are performed parallel by bit as well as parallel by word, resulting in more efficient algorithms and shorter execution times. Consideration of the limitations of a linear memory array in performing such operations leads to the description of a more efficient organization, called the two-dimensional distributed logic memory. The efficiency of this form in the bulk processing of data is illustrated by a number of algorithms for basic data processing operations, including matrix inversion.

Lower Bounds of the Number of Threshold Functions and a Maximum Weight

Abstract: A lower bound on the number of threshold functions and a lower bound on the maximum of minimum weights of a threshold element are derived from a recursively constructed family of threshold elements. All threshold functions of n variables are difficult to construct for a general value of n, but it is shown that a large number of them can be constructed recursively from threshold functions of fewer variables. Schemes of such generation and related proper ties are discussed. Threshold functions generated in this way are so numerous that they constitute a constructive proof of a good lower bound on the number of threshold functions. By a similar procedure, we can derive a lower bound on the maximum of minimum weights of a threshold element. In this paper, discussion is limited to self-dual threshold functions, but this does not sacrifice generality, because any threshold function can be derived from a self-dual threshold function by assigning 1 or 0 to a certain variable.

A Lower Bound of the Number of Threshold Functions

Abstract: Threshold functions are a class of Boolean Functions which have been studied for several years under different names such as majority functions, linearly separable functions, and linear input functions.

On the Construction of (d, k) Graphs

Abstract: The computer organization described here is an extension of a concept of Leondes and Rubinoff [1]. The original machine consisted of a drum store and a single processor capable of sequencing its access from one track (array column) to another at the end of each drum revolution. In this way the system could process one iteration of a Laplace equation in n-drum revolutions, where n is the number of columns of the array.

Canonical Form and Synthesis of Cellular Cascades

Abstract: Cascades of two-input, one-output general function cells have been studied previously with the restriction that no external variable may drive more than one cell. Upon relaxing this restriction, it is shown that a variable that drives more than one cell in a cascade need never drive more than one cell that is not an EXCLUSIVE-OR cell, and that cell must be the first cell driven by the variable in the cascade. From this it follows that there exists a canonical form for cellular cascades with repeated inputs. Furthermore, the length of a cascade required to produce an n-variable function is bounded by (n2+n-4)/2, and there are functions that meet this bound for all n. Derived from knowledge of the canonical form, a realizability and synthesis algorithm is described that is an extension of previously described algorithms. The algorithm has been used to test the 402 Harvard functions, and a table of minimal-length cascades of realizable functions is included in the paper. Although the number of realizable functions is greatly increased when the input restriction is relaxed, it is shown that the fraction of n-variable functions that are realizable becomes vanishingly small as n grows large. In particular, for example, of the 2n+1 symmetric functions of n-variables, precisely 12 are realizable for all n?3.

Minimal Square Rooting

Abstract: Binary square rooting algorithms which yield a root in a redundant representation using digits 1, ?1, and 0 are analyzed, particularly those yielding a root in a representation in which the number of nonzero digits is minimal. An algorithm which may lead to any possible minimal representation of the square root is developed.

Minimal Shift-Register Realizations of Sequential Machines

Abstract: This paper is concerned with the problem of mechanizing synchronous sequential machines with the least number of shift registers. An algorithm, suitable for programming on a digital computer, is developed which starts with the state table of the given machine and yields mechanizations having the least possible number of shift registers. The algorithm is based on the fact that there is a one-to-one correspondence between shift registers and certain partitions of the set of states of the machine. These partitions are called shift-register partitions (SRP's), and it is shown that every SRP can be generated from two special partitions called the column partition (? c ) and the row partition (? r ). States are grouped together in ? c if they have transitions into common states and are grouped together in ? r if they have transitions from common states.

Minimal Three-Variable NOR and NAND Logic Circuits

Abstract: Cantor, Estrin and Turn have described a special-purpose structure to implement sequential table look-up (STL) algorithms for the evaluation of ln x and exp x.1 Tables of precomputed constants are used to transform the argument into a range where the function may be approximated by a simple polynomial. The transformation for ln x, originally proposed by Bemer,2 is where the set of constants ai are precomputed. A power series expansion for ln x is

Comments on the Minimization of Stochastic Machines

Abstract: In a recent note by Bacon [1], a new result about the minimization of stochastic finite state machines has been proven. Extending the theory developed by Carlyle [2], he shows that all minimal-state forms of equivalent machines are state equivalent, and they all have the same number of states. He also describes a necessary and sufficient condition for a machine to be minimal.

Flow Table Simplification-Some Useful Aids

Abstract: Three results are presented pertinent to the problem of finding minimum-row versions of incompletely specified flow tables for sequential or iterative circuits. 1) Conditions are precisely stated under which preliminary mergers can be made without the danger of ruining opportunities for ultimately finding a minimal-row version. 2) A theorem by McCluskey is generalized to show that for all flow tables if optional entries arise only due to restrictions as to which input states may immediately follow one another, then the reduction problem is relatively simple. 3) A useful heuristic in the form of a diagram illustrating implication relations of 2-member compatibles is introduced as an aid in finding minimal closed sets of compatibles.

Identification and Minimization of Linear Machines

Abstract: This paper is a study of linear machines and their submachines. Methods are presented for finding the reduced form of a given linear machine with or without fixed initial state. A technique is suggested for detecting whether a machine is linear or can be embedded as a submachine in a linear machine. In the latter case a state assignment is produced for the minimum linear realization. Encoded inputs and outputs are assumed, but given machines are not assumed reduced, nor are there any restrictions on the number of states in the given machine or in the linear realization. The method also detects machines that are linearly realizable when constants are available. The main results are that the reduced form of a linear machine is linear and that a linearly realizable machine with r-independent states has an r-dimensional realization.

A Critical Comparison of Two Kinds of Adaptive Classification Networks

Abstract: : This report compares the capabilities and equipment requirements of two kinds of adaptive classification networks--the 'Learning Matric,' and the Madaline. The Learning Matrix and the Madaline are structurally quite similar, forming arrays of binary output signals from linear combinations of binary or analog input signals. Both systems can learn (adjust their own parameters) from sets of patterns (with corresponding desired outputs) presented to them, and they can thereafter successfully classify additional patterns as presented. The two systems differ primarily in their training methods and in their output logic. Both the Learning Matrix and the Madaline can be realized either by the use of adaptive hardware or by digital-computer simulation. The comparison indicates that in most cases the Learning Matrix will require fewer adaptation cycles than will the Madaline when applied to a given problem; on the other hand, the Madaline will usually require less equipment than the Learning Matrix. However, in making a choice of techniques for a given situation, the overriding consideration will usually be the question of optimality. (Author)