Showing papers in "IEEE Transactions on Nanotechnology in 2014"

A First Step Toward Cost Functions for Quantum-Dot Cellular Automata Designs

Abstract: Quantum-dot cellular automata (QCA) is potentially a very attractive alternative to CMOS for future digital designs. Circuit designs in QCA have been extensively studied. However, how to properly evaluate the QCA circuits has not been carefully considered. To date, metrics and area-delay cost functions directly mapped from CMOS technology have been used to compare QCA designs, which is inappropriate due to the differences between these two technologies. In this paper, several cost metrics specifically aimed at QCA circuits are studied. It is found that delay, the number of QCA logic gates, and the number and type of crossovers, are important metrics that should be considered when comparing QCA designs. A family of new cost functions for QCA circuits is proposed. As fundamental components in QCA computing arithmetic, QCA adders are reviewed and evaluated with the proposed cost functions. By taking the new cost metrics into account, previous best adders become unattractive and it has been shown that different optimization goals lead to different “best” adders.

MHD Three-Dimensional Boundary Layer Flow of Casson Nanofluid Past a Linearly Stretching Sheet With Convective Boundary Condition

Abstract: Steady flow of a Casson fluid in the presence of a nanoparticle is studied. It is considered that the sheet is stretched in both the direction along the xy-plane. Moreover, we have considered the magnetohydrodynamics effect within the fluid and convective condition along the surface. Similarity transformation is used to convert the governing partial differential equations to a set of coupled nonlinear ordinary differential equations which are solved numerically. The behavior of emerging parameters are presented graphically and discussed for velocity, temperature, and nanoparticles fraction. Variation of the reduced Nusselt and Sherwood number against physical parameters are presented graphically. It is found that the reduced Nusselt number is the decreasing function and the reduced Sherwood number is the increasing function of Brownian parameter Nb and thermophoresis parameter Nt.

Graphene-Based Plasmonic Tunable Low-Pass Filters in the Terahertz Band

Abstract: We propose the concept, synthesis, analysis, and design of graphene-based plasmonic tunable low-pass filters operating in the terahertz band. The proposed structure is composed of a graphene strip transferred onto a dielectric and a set of polysilicon dc gating pads located beneath it. This structure implements a stepped impedance low-pass filter for the propagating surface plasmons by adequately controlling the guiding properties of each strip section through graphene's field effect. A synthesis procedure is presented to design filters with desired specifications in terms of cutoff frequency, in-band performance, and rejection characteristics. The electromagnetic modeling of the structure is efficiently performed by combining an electrostatic scaling law to compute the guiding features of each strip section with a transmission line and transfer-matrix framework, approach further validated via full-wave simulations. The performance of the proposed filters is evaluated in practical scenarios, taking into account the presence of the gating bias and the influence of graphene's losses. These results, together with the high miniaturization associated with plasmonic propagation, are very promising for the future use and integration of the proposed filters with other graphene and silicon-based elements in innovative terahertz communication systems.

Effect of Drain Doping Profile on Double-Gate Tunnel Field-Effect Transistor and its Influence on Device RF Performance

Abstract: In this paper, we have investigated the effect of drain doping profile on a double-gate tunnel field-effect transistor (DG-TFET) and its radio-frequency (RF) performances. Lateral asymmetric drain doping profile suppresses the ambipolar behavior, improves OFF-state current, reduces the gate-drain capacitance, and improves the RF performance. Further, placing the high-density layer in the channel near the source-channel junction, a reduction in the width of depletion region, improvement in ON-state current (I ON ), and subthreshold slope are analyzed for this asymmetric drain doping. However, it also improves many RF figures of merit for the DG-TFET. Furthermore, lateral asymmetric doping effects on RF performances are also checked for the various channel length. Therefore, this paper would be beneficial for a new generation of RF circuits and systems in a broad range of applications and operating frequencies covering RF spectrum. So, the RF figures of merit for the DG-TFET are analyzed in terms of transconductance (g m ), unit-gain cutoff frequency (f T ), maximum frequency of oscillation (f max ), and gain bandwidth product. For this, the RF figures of merit have been extracted from the V-parameter matrix generated by performing the small-signal ac analysis. Technology computer-aided design simulations have been performed by 2-D ATLAS, Silvaco International, Santa Clara, CA, USA.

Design and Evaluation of Multiple Valued Logic Gates Using Pseudo N-Type Carbon Nanotube FETs

Abstract: Multiple valued logic (MVL) circuits are particularly attractive for nanoscale implementation as advantages in information density and operating speed can be harvested using emerging technologies. In this paper, a new family of MVL gates is proposed for implementation using carbon nanotube field-effect transistors (CNTFETs). The proposed designs use pseudo N-type CNTFETs and no resistor is utilized for their operation. This approach exploits threshold voltage control of the P-type and N-type transistors, while ensuring correct MVL operation for both ternary and quaternary logic gates. This paper provides a detailed assessment of several figures of merit, such as static power consumption, switching power consumption, propagation delay and the power-delay product (PDP). Compared with resistor-loaded designs, the proposed pseudo-NCNTFET MVL gates show advantages in circuit area, power consumption and energy efficiency, while still incurring a comparable propagation delay. Compared to a complementary logic family, the pseudo-NCNTFET MVL logic family requires a smaller circuit area with a similar propagation delay on average, albeit with a larger PDP and static power consumption. A design methodology and a discussion of issues related to leakage and yield are also provided for the proposed MVL logic family.

Top–Down Fabrication of Gate-All-Around Vertically Stacked Silicon Nanowire FETs With Controllable Polarity

Abstract: Asthe currentMOSFET scaling trend is facing strong limitations, technologies exploiting novel degrees of freedom at physical and architecture level are promising candidates to enable the continuation of Moore's predictions. In this paper, we report on the fabrication of novel ambipolar Silicon nanowire (SiNW) Schottky-barrier (SB) FET transistors featuring two independent gate-all-around electrodes and vertically stacked SiNW channels. A top-down approach was employed for the nanowire fabrication, using an e-beam lithography defined design pattern. In these transistors, one gate electrode enables the dynamic configuration of the device polarity (n- or p-type) by electrostatic doping of the channel in proximity of the source and drain SBs. The other gate electrode, acting on the center region of the channel switches ON or OFF the device. Measurement results on silicon show I-on/I-off > 10(6) and subthreshold slopes approaching the thermal limit, SS approximate to 64 mV/dec (70 mV/dec) for p(n)-type operation in the same physical device. Finally, we show that the XOR logic operation is embedded in the device characteristic, and we demonstrate for the first time a fully functional two-transistor XOR gate.

A Native Stochastic Computing Architecture Enabled by Memristors

Abstract: A two-terminal memristor device is a promising digital memory for its high integration density, substantially lower energy consumption compared to CMOS, and scalability below 10 nm. However, a nanoscale memristor is an inherently stochastic device, and extra energy and latency are required to make a deterministic memory based on memristors. Instead of enforcing deterministic storage, we take advantage of the nondeterministic memory for native stochastic computing, where the randomness required by stochastic computing is intrinsic to the devices without resorting to expensive stochastic number generation. This native stochastic computing system can be implemented as a hybrid integration of memristor memory and simple CMOS stochastic computing circuits. We use an approach called group write to program memristor memory cells in arrays to generate random bit streams for stochastic computing. Three methods are proposed to program memristors using stochastic bit streams and compensate for the nonlinear memristor write function: voltage predistortion, parallel single-pulse write, and downscaled write and upscaled read. To evaluate these technical approaches, we show by simulation a memristor-based stochastic processor for gradient descent optimization, and k-means clustering. The native stochastic computing based on memristors demonstrates key advantages in energy and speed in compute-intensive, data-intensive, and probabilistic applications.

Memristor Multiport Readout: A Closed-Form Solution for Sneak Paths

Abstract: In this paper, we introduce for the first time, a closed-form solution for the memristor-based memory sneak paths without using any gating elements The introduced technique fully eliminates the effect of sneak paths by reading the stored data using multiple access points and evaluating a simple addition/subtraction on the different readings The new method requires fewer reading steps compared to previously reported techniques, and has a very small impact on the memory density To verify the underlying theory, the proposed system is simulated using Synopsys HSPICE showing the ability to achieve a 100% sneak-path error-free memory In addition, the effect of quantization bits on the system performance is studied

An Accurate and Verilog-A Compatible Compact Model for Graphene Field-Effect Transistors

Abstract: The present paper provides an accurate drift-diffusion model of the graphene field-effect transistor (GFET). A precise yet mathematically simple current-voltage relation is derived by focusing on device physics at energy levels close to the Dirac point. With respect to previous work, our approach extends modeling accuracy to the low-voltage biasing regime and improves the prediction of current saturation. These advantages are highlighted by a comparison study of the drain current, transconductance, output conductance, and intrinsic gain. The model has been implemented in Verilog-A and is compatible with conventional circuit simulators. It is provided as a tool for the exploration of GFET-based integrated circuit design. The model shows good agreement with measurement data from GFET prototypes.

Cofabrication of Vacuum Field Emission Transistor (VFET) and MOSFET

Abstract: Co-fabrication of a nanoscale vacuum field emission transistor (VFET) and a metal-oxide-semiconductor field effect transistor (MOSFET) is demonstrated on a silicon-on-insulator wafer. The insulated-gate VFET with a gap distance of 100 nm is achieved by using a conventional 0.18-μm process technology and subsequent photoresist ashing process. The VFET shows a turn-on voltage of 2 V at a cell current of 2 nA and a cell current of 3 μA at the operation voltage of 10 V with an ON/OFF current ratio of 10 $^{4}$ . The gap distance between the cathode and anode in the VFET is defined to be less than the mean free path of electrons in air, and consequently, the operation voltage is reduced to be less than the ionization potential of air molecules. This allows the relaxation of the vacuum requirement. The present integration scheme can be useful as it combines the advantages of both structures on the same chip.

Reconfigurable Nanowire Electronics-Enabling a Single CMOS Circuit Technology

Abstract: Reconfigurable nanowire transistors are multifunctional switches that fuse the electrical characteristics of unipolar n- and p-type field effect transistors (FETs) into a single universal type of four-terminal device. In addition to the three known FET electrodes the fourth acts as an electric select signal that dynamically programs the desired polarity. The transistor consists of two independent charge carrier injection valves as realized by two gated Schottky junctions integrated within an intrinsic silicon nanowire. The transport properties that provide unipolar n- and p-type behavior will be elucidated. Further, solutions to the major device challenges toward the implementation of these novel transistors at the circuit level are proposed, by exploiting specific nanowire geometries and dimensions. These include methods that deliver equal on-currents and symmetric transfer characteristics for n- and p-type, and that eliminate supra-linear output characteristics at low source–drain biases. We will further show that circuits built of these symmetric transistors successfully exhibit complementary operation. Finally, the prospects in building reconfigurable circuits and systems will be briefly summarized.

Spiral Scanning With Improved Control for Faster Imaging of AFM

Abstract: One of the key barriers to an atomic force microscope (AFM) achieving high scanning speeds is its use of the traditional zig-zag raster pattern scanning technique. In this paper, we consider the use of a high-speed spiral imaging technique with an improved multi-input multi-output (MIMO) model predictive control (MPC) scheme with a damping compensator for faster scanning by an AFM. The controller’s design is based on an identified MIMO model of the AFM’s piezoelectric tube scanner (PTS) and it achieves a higher closed-loop bandwidth, significant damping of the resonant mode of the PTS, and reduces the cross-coupling effect between the PTS’s axes. The spirals produced have particularly narrow-band frequency measures which change slowly over time, thereby making it possible for the scanner to achieve improved tracking and continuous high-speed scanning rather than being restricted to the back and forth motion of raster scanning. To evaluate the performance improvement using this proposed control scheme for spiral scanning, an experimental comparison of its scanned images with those of the open-loop condition is performed. Experimental results show that, by using the proposed method, the AFM’s scanning speed is significantly increased up to 180 Hz.

Energy-Efficient Non-Boolean Computing With Spin Neurons and Resistive Memory

Abstract: Emerging nonvolatile resistive memory technologies can be potentially suitable for computationally expensive analog pattern-matching tasks. However, the use of CMOS analog circuits with resistive crossbar memory (RCM) would result in large power consumption and poor scalability, thereby eschewing the benefits of RCM-based computation. We explore the potential of emerging spin-torque devices for RCM-based approximate computing circuits. Emerging spin-torque switching techniques may lead to nanoscale, current-mode spintronic switches that can be used for energy-efficient analog-mode data processing. We propose the use of such low-voltage, fast-switching, magnetometallic “spin neurons” for ultralow power non-Boolean computing with RCM. We present the design of analog associative memory for face recognition using RCM, where, substituting conventional analog circuits with spin neurons can achieve ~100× lower power consumption.

Design of a Nonvolatile 7T1R SRAM Cell for Instant-on Operation

Abstract: Energy consumption is a major concern in nanoscale CMOS ICs; the power-Off operational mode and low-voltage circuits have been proposed to alleviate energy dissipation Static random access memories (SRAMs) are widely used in today's chips; nonvolatile SRAMs (NVSRAMs) have been proposed to preserve data, while providing fast power- On/Off speeds Nonvolatile operation is usually accomplished by the use of a resistive RAM circuit (hence referred to as RRAM); the utilization of a RRAM with an SRAMs not only enables chips to achieve low energy consumption for nonvolatile operation, but it also permits to restore data when a restore on power-up is performed (this operation is also commonly referred to as “Instant-on”) This paper presents a novel NVSRAM circuit for “Instant-on” operation and evaluates its performance at nanometric feature sizes The proposed memory cell consists of a SRAM core (in this case, a 6T cell) and an oxide resistive RRAM circuit (1T1R), thus making a 7T1R scheme The proposed cell offers better nonvolatile performance (in terms of operations such as “Store,” “Power-down,” and “Restore”) when compared with existing nonvolatile cells The scenario of multiple-context configuration is also analyzed Figures of merit such as energy, operational delay, and area are also substantially improved, making the proposed design a better scheme for “Instant-on” operation

Experimental Demonstration of Ultrashort-Channel (3 nm) Junctionless FETs Utilizing Atomically Sharp V-Grooves on SOI

Abstract: Ultrashort-channel junctionless FETs (JL-FETs) were fabricated on silicon-on-insulator substrates utilizing atomically sharp V-shaped grooves produced by anisotropic wet etching. The channel length, defined as the width of the V-groove bottom, was as short as 3 nm, and the channel thickness was between 1 and 8 nm. Excellent transistor characteristics with threshold voltages that are optimal for low-power operation were obtained for both n-FETs and p-FETs when the thickness of both the channel and gate dielectric film thickness was reduced to 1 nm. The origin of the excellent electrostatic control is discussed on the basis of fringe capacitance and quantum confinement effects in a nanometer-scale ultrathin Si layer where band-gap expansion, dielectric constant reduction, and increase in the dopant activation energy become prominent. The electrical characteristics of the ultrashort channel JL-FETs were found to be very sensitive to device parameters such as the channel thickness and dopant concentration.

Variation-Tolerant and Disturbance-Free Sensing Circuit for Deep Nanometer STT-MRAM

Abstract: This paper presents a high reliability sensing circuit for the deep nanometer spin-transfer torque magnetic random-access memory (STT-MRAM). This sensing circuit, using a triple-stage sensing operation and source follower charge transfer amplification, is able to tolerate mostly the process, voltage, and temperature variations, thus improving greatly the sensing margin. Meanwhile, it clamps the bit-line voltage to a predefined small bias voltage to avoid any read disturbance. With the STMicroelectronics CMOS 40-nm design kit and a precise STT-MTJ compact model, Monte-Carlo simulations have been performed to evaluate its sensing reliability performance.

Video-Rate Lissajous-Scan Atomic Force Microscopy

Abstract: Raster scanning is common in atomic force microscopy (AFM). The nonsmooth raster waveform contains high-frequency content that can excite mechanical resonances of an AFM nanopositioner during a fast scan, causing severe distortions in the resulting image. The mainstream approach to avoid scan-induced vibrations in video-rate AFM is to employ a high-bandwidth nanopositioner with the first lateral resonance frequency above 20 kHz. In this paper, video-rate scanning on a nanopositioner with 11.3-kHz resonance frequency is reported using a smooth Lissajous scan pattern. The Lissajous trajectory is constructed by tracking two sinusoidal waveforms on the lateral axes of the nanopositioner. By combining an analog integral resonant controller (IRC) with an internal model controller, 1- and 2-kHz single tone set-points were successfully tracked. High-quality time lapsed AFM images of a calibration grating recorded at 9 and 18 frames/s without noticeable image distortions are reported.

Metallic Nanoparticles Analysis for the Peristaltic Flow in an Asymmetric Channel With MHD

Abstract: The peristaltic flow of an incompressible viscous-fluid-containing metallic nanoparticles in an irregular conduit is analyzed. The metallic nanoparticles for the peristaltic flow are not explored so far. The governing equations are streamlined using “long wavelength and low Reynolds number approximation.” Exact solutions have been evaluated for velocity, pressure gradient, the solid volume fraction of the nanoparticles, and temperature profile. The effects of various flow parameters, i.e., Hartmann number, Eckert number, the solid volume fraction of the nanoparticles amplitude ratio, and Prandtl number are presented graphically.

MHD Stagnation Point Ferrofluid Flow and Heat Transfer Toward a Stretching Sheet

Abstract: This paper investigates stagnation point flow and heat transfer of a ferrofluid toward a stretching sheet in the presence of viscous dissipation. Three types of ferroparticles: magnetite (Fe 3O 4 ), cobalt ferrite (CoFe 2O 4), and Mn-Zn ferrite (Mn-ZnFe 2O 4) are considered with water and kerosene as conventional base fluids. Numerical solutions to the resulting ordinary differential equations are obtained by using an implicit finite-difference method with quasi-linearization technique. The effects of controlling parameters on the dimensionless velocity, temperature, skin friction, and Nusselt numbers are investigated. It is found that kerosene-based ferrofluids have higher skin friction and Nusselt numbers than water-based ferrofluids. The numerical results of skin friction are compared with the available data for special cases and are found to be in good agreement.

An Ambipolar Virtual-Source-Based Charge-Current Compact Model for Nanoscale Graphene Transistors

Abstract: A compact physics-based ambipolar-virtual-source (AVS) model is presented that describes carrier transport in both unipolar and ambipolar regimes in quasi-ballistic graphene field-effect transistors (GFETs). The transport model incorporates two separate virtual sources for electrons and holes and is supplemented by a self-consistent channel-charge-partitioning model valid from drift-diffusive to ballistic transport conditions. The model comprehends the asymmetry introduced by different contact resistances for electrons and holes. The AVS model has a limited number of parameters, most of which have a physical meaning and can easily be extracted from device characterization. The model has been extensively calibrated with experimental dc I-V and s-parameter measurements of devices with gate lengths from 650 to 40 nm. This has allowed the scaling of mobility and VS source injection velocity of carriers with gate length to be investigated for the first time. The new compact model yields continuous currents and charges and can easily be used in the design and analysis of circuits and systems implemented with GFETs.

Electromagnetic Performance of RF NEMS Graphene Capacitive Switches

Abstract: The RF performance of a nanoelectromechanical systems (NEMS) capacitive switch based on graphene is evaluated. Our results show that graphene can be a good candidate for the membrane of RF NEMS switches in applications where low actuation voltage and fast switching are required. The conductivity of the membrane is accurately modeled in the up- and down-state positions of the switch by considering the field effect of graphene. Rigorous full-wave simulations are then performed to obtain the scattering parameters of the switch. It is shown that graphene's conductivity variation due to electric field effect has a limited yet beneficial impact on the performance of the switch. It is also demonstrated that while monolayer graphene results in quite high switch losses at high frequency, the use of multilayer graphene, can considerably reduce the switch losses and improve the RF performance. Finally, an equivalent circuit model for the graphene-based RF NEMS switch is extracted and the results are compared with the full-wave 3-D electromagnetic simulation. These results motivate further efforts in the fabrication and characterization of graphene RF NEMS.

Design and Synthesis of Ultralow Energy Spin-Memristor Threshold Logic

Abstract: A threshold logic gate performs weighted sum of multiple inputs and compares the sum with a threshold We propose spin-memeristor threshold logic (SMTL) gates, which employ a memristive cross-bar array to perform current-mode summation of binary inputs, whereas the low-voltage fast-switching spintronic threshold devices carry out the threshold operation in an energy efficient manner Field-programmable SMTL gate arrays can operate at a small terminal voltage of ∼50 mV, resulting in ultralow power consumption in gates as well as programmable interconnect networks We evaluate the performance of SMTL using threshold logic synthesis Results for common benchmarks show that SMTL-based programmable logic hardware can be more than 100 × energy efficient than the state-of-the-art CMOS field-programmable gate array

Single-Metal Nanoscale Thermocouples

Abstract: We study the generation of thermoelectricity by nanoscale thermocouples (TCs) formed from a single layer of metal with cross-sectional discontinuity. Typically, a TC is formed when a second conductor is inserted between two sections of a first conductor forming two junctions situated at different temperatures. Here, we investigate the behavior of TCs formed not of two conductors but rather nanowires of the same metal of two cross-sectional areas. Monometallic TCs were constructed from a lithographically defined nanowire having one abrupt variation in width along its length, and tested at room temperature; these structures exploit a change in Seebeck coefficient that is present at these size scales. To investigate the thermoelectric properties of such “shape-engineered” TCs, nanoscale heaters were employed to set the local temperatures. Temperature profiles at the hot and cold junctions of the TCs were determined both by simulations and experiments. Results demonstrate that the magnitude of the open-circuit voltage, and hence the relative Seebeck coefficient, is a function of the parameters of the variations in the segment widths. The fabrication complexity of such shape-engineered monometallic nanowire TCs is greatly reduced compared to that of conventional bimetallic TCs, and could be mass-produced using simpler manufacturing techniques.

Two Memristor SPICE Models and Their Applications in Microwave Devices

Abstract: This paper presents two simple SPICE circuit models of the memristor using two different kinds of integrators. These models expand and simplify the previous methods of solving the memristor's modeling equations presented by Hewlett–Packard Lab. The behaviors of the two memristor models are investigated when they are excited by a sinusoidal voltage source. Both models satisfy the general features of memristive systems such as having a zero-crossing property in the form of an i–v Lissajous figure. In order to explore the unique characteristics and applications of the memristor in microwave devices, first we incorporate the memristor in a microstrip transmission line as a load. We do the analysis using a finite-difference time-domain simulator integrated with a nonlinear SPICE circuit solver. Furthermore, we design a reconfigurable microstrip bandpass filter based on a memristor-loaded resonator, and utilize a memristor as a carrier-wave modulator connecting the microstrip patch antenna to the ground.

Analysis of Temperature-Dependent Electrical Characteristics of n-ZnO Nanowires (NWs)/p-Si Heterojunction Diodes

Abstract: This paper presents the electrical characteristics of n-zinc oxide (ZnO) nanowires (NWs)/p-Si (100) heterojunction diodes fabricated by the oxidation of thermally deposited metallic Zn on Al:ZnO-coated p-Si 〈1 0 0〉 substrates. The electrical parameters of the n-ZnO NWs/p-Si diodes have been estimated by using the room temperature capacitance-voltage (C-V) and temperature-dependent current-voltage (I-V) characteristics of the heterojunction. The carrier concentration of the ZnO NW film and the barrier height of the diode estimated from the C-V characteristics at room temperature are 1.54 × 10 15 cm -3 and 0.75 eV, respectively. The thermionic emission model was used to analyze the temperature-dependent measured I-V characteristics to estimate the parameters of the diode. The estimated values of the barrier height and ideality factor at room temperature were 0.715 eV and 2.13, respectively. The spatial barrier inhomogeneity was included in the aforementioned analysis by assuming a Gaussian distribution for the barrier height at the n-ZnO NWs/p-Si heterojunction. The Richardson constant A* of ZnO was found to be increased from a relatively low value of 9.75 ×10 - 8 A ·cm - 2 ·K - 2 to a more realistic value of 49A ·cm - 2 ·K - 2 after incorporating the barrier inhomogeneity phenomenon in the aforementioned analysis.

Quartz Crystal Microbalance Humidity Sensors Based on Nanodiamond Sensing Films

Abstract: A novel quartz crystal microbalance (QCM) humidity sensor using nanodiamond (ND) as sensing films has been presented in this paper. For evaluating the performance of ND-coated QCM humidity sensor, a series of humidity-sensing experiments were carried out by using both oscillating circuit and impedance analysis methods. Based on the large specific surface area and high mechanical modulus, the ND-coated sensor exhibited large humidity-sensing response and good stability. In addition, the resultant sensors displayed low hysteresis, good repeatability, and short response time. The influence of the depositing amount of ND on the sensor's performance has also been discussed. The result indicated that the stability of QCM humidity sensor showed an extreme decrease when the deposition amount of ND on QCM is large enough. The possible reason for this anomalous phenomenon is analyzed and discussed. This study suggests that ND could be a promising candidate material for developing high-performance QCM humidity sensor.

Design of Efficient Binary Comparators in Quantum-Dot Cellular Automata

Abstract: Quantum-dot cellular automata (QCA) are an attractive emerging technology suitable for the development of ultra-dense low-power high-performance digital circuits. Efficient solutions have recently been proposed for several arithmetic circuits, such as adders, multipliers, and comparators. Nevertheless, since the design of digital circuits in QCA still poses several challenges, novel implementation strategies and methodologies are highly desirable. This paper proposes a new design approach oriented to the implementation of binary comparators in QCA. New formulations of basic logic equations required to perform the comparison function are proposed. The new strategy has been exploited in the design of two different comparator architectures and for several operands word lengths. With respect to existing counterparts, the comparators proposed here exhibit significantly higher speed and reduced overall area.

Transmission Protocols for Calcium-Signaling-Based Molecular Communications in Deformable Cellular Tissue

Abstract: Molecular communications is a new paradigm that enables nanomachines to communicate within a biological environment. One form of molecular communications is calcium (Ca 2+ ) signaling, which occurs naturally in living biological cells. Ca 2+ signaling enables cells in a tightly packed tissue structure to communicate at short ranges with neighboring cells. The achievable mutual information of Caa 2+ signaling between tissue embedded nanomachines is investigated in this paper, focusing in particular on the impact that the deformation of the tissue structure has on the communication channel. Based on this analysis, a number of transmission protocols are proposed; nanomachines can utilize these to communicate using Ca 2+ signaling. These protocols are static time-slot configuration, dynamic time-slot configuration, dynamic time-slot configuration with silent communication, and improved dynamic time-slot configuration with silent communication (IDTC-SC). The results of a simulation study show that IDTC-SC provides the maximum data rate when tissues experience frequent deformation.

Current–Voltage Characteristics of ZnO Nanowires Under Uniaxial Loading

Abstract: The charge transport in zinc-oxide piezosemiconductive nanowires under purely vertical compressive or tensile strains is investigated. For simplicity, only the additional band bending originated by the piezoelectric charges has been accounted for. Moreover, a constant volumetric piezoelectric charge density is assumed, distributed within a maximum distance $\delta_{\rm piezo}$ from the two junctions between the metal ends and the nanowire. Examples demonstrate that the carrier concentration, the energy conduction band profile, and the current–voltage characteristics significantly depend on $\delta_{\rm piezo}$. Therefore, we propose the use of current–voltage measurements to obtain information on $\delta_{\rm piezo}$ in strained piezosemiconductors.

Magnetoelastic Clock System for Nanomagnet Logic

Abstract: In recent years, magnetic-based technologies, like nanomagnet logic (NML), are gaining increasing interest as possible substitutes of CMOS transistors. The possibility to mix logic and memory in the same device, coupled with a potential low power consumption, opens up completely new ways of developing circuits. The major issue of this technology is the necessity to use an external magnetic field as clock signal to drive the information through the circuit. The power losses due to the magnetic field generation potentially wipe out any advantages of NML. To solve this problem, new clock mechanisms were developed, based on spin transfer torque current and on voltage-controlled multiferroic structures that use magnetoelastic properties of magnetic materials, i.e., exploiting the possibility of influencing magnetization dynamics by means of the elastic tensor. In particular, the latter shows an extremely low power consumption. In this paper, we propose an innovative voltage-controlled magnetoelastic clock system aware of the technological constraints risen by modern fabrication processes. We show how circuits can be fabricated taking into account technological limitations, and we evaluate the performance of the proposed system. Results show that the proposed solution promises remarkable improvements over other NML approaches, even though state-of-the-art ideal multiferroic logic has in theory better performance. Moreover, since the proposed approach is technology-friendly, it gives a substantial contribution toward the fabrication of a full magnetic circuit and represents an optimal tradeoff between performance and feasibility.