Showing papers in "Iet Circuits Devices & Systems in 2017"

Reversible logic-based image steganography using quantum dot cellular automata for secure nanocommunication

Abstract: This study introduces a novel architecture for image steganography using reversible logic based on quantum dot cellular automata (QCA). Feynman gate is used to achieve the reversible encoder and decoder for image steganography. A Nanocommunication circuit for image steganography is shown using proposed encoder/decoder circuit. The proposed QCA circuits have lower quantum cost than traditional designs. It shows the cost effectiveness functionality of the proposed designs. The proposed circuit has 28.33% improvement in terms of area over complementary metal-oxide-semiconductor circuit. To perform image steganography LSB technique is used; signal-to-noise ratio (SNR), peak SNR and mean squared error (MSE) are also computed. The proposed QCA encoder/decoder circuit is suitable for reversible computing. To establish this, the heat energy dissipation by the proposed encoder/decoder circuit is estimated. The estimation shows that the encoder/decoder circuit has very low energy dissipation. Single missing/additional cell-based defect analysis is also explored in this study. Reliability of the circuit is tested against different temperatures. Implementation and testing of the circuit are achieved using QCADesigner tool. MATLAB is used to produce the input to the proposed circuit.

Comparative study of 16-order FIR filter design using different multiplication techniques

Abstract: This study represents designing and implementation of a low power and high speed 16 order FIR filter. To optimise filter area, delay and power, different multiplication techniques such as Vedic multiplier, add and shift method and Wallace tree (WT) multiplier are used for the multiplication of filter coefficient with filter input. Various adders such as ripple carry adder, Kogge Stone adder, Brent Kung adder, Ladner Fischer adder and Han Carlson adder are analysed for optimum performance study for further use in various multiplication techniques along with barrel shifter. Secondly optimisation of filter area and delay is done by using add and shift method for multiplication, although it increases power dissipation of the filter. To reduce the complexity of filter, coefficients are represented in canonical signed digit representation as it is more efficient than traditional binary representation. The finite impulse-response (FIR) filter is designed in MATLAB using equiripple method and the same filter is synthesised on Xilinx Spartan 3E XC3S500E target field-programmable gate array device using Very High Speed Integrated Circuit Hardware Description Language (VHDL) subsequently the total on-chip power is calculated in Vivado2014.4. The comparison of simulation results of all the filters show that FIR filter with WT multiplier is the best optimised filter.

Review on system development in eddy current testing and technique for defect classification and characterization

Abstract: Eddy current testing (ECT) is one of the non-destructive evaluation techniques widely used, especially in oil and gas industries. It characterized noisy data to the less-than-perfect detection and as an indication of serious false alarm problem. However, not many researchers have described in detail the intelligent ECT crack detection system. This paper introduces a review of ECT technique and factors that affect the signal fundamental according to the hardware and software development. First, describe the magnetic excitation resources including the sinusoidal and pulse exciting signal. Second, outlines explanation about the ECT probe. The explanations are more about the probes development for air core probe and giant magnetoresistance probe. Third, there is discussion on ECT circuit that used including ECT system, ECT rotating magnetic field and application measurement for optimal control parameters. The defect in characterizations and measurement are discussed on the fourth part of this paper. The fourth part discusses the ECT lift-off compensation including the lift-off and application of intelligent technique in ECT. The limitations of lift-off for coil probe and compensation techniques also discussed in this part. Finally, a comprehensive review of previous studies on the application of intelligent ECT crack detection in nondestructive ECT is presented.

Thermal image processing for real-time non-contact respiration rate monitoring

Abstract: A real-time thermal imaging based, non-contact respiration rate monitoring method was developed. It measured the respiration related skin surface temperature changes under the tip of the nose. Facial tracking was required as head movements caused the face to appear in different locations in the recorded images over time. The algorithm detected the tip of the nose and then, a region just under it was selected. The pixel values in this region in successive images were processed to determine respiration rate. The segmentation method, used as part of the facial tracking, was evaluated on 55,000 thermal images recorded from 14 subjects with different extent of head movements. It separated the face from image background in all images. However, in 11.7% of the images, a section of the neck was also included, but this did not cause an error in determining respiration rate. The method was further evaluated on 15 adults, against two contact respiration rate monitoring methods that tracked thoracic and abdominal movements. The three methods gave close respiration rates in 12 subjects but in 3 subjects, where there were very large head movements, the respiration rates did not match.

Method for designing ternary adder cells based on CNFETs

Abstract: Recently multiple valued logic has attracted the attention of digital system designers. Scalable threshold voltage values of carbon nanotube field-effect transistors (CNFETs) can easily be utilised for multiple-Vt circuit designs. In this study, a novel energy-efficient method for designing one-digit adder is proposed. The suggested design employ ternary multiplexers to select s u c c e s s o r ¯ and p r e d e c e s s o r ¯ of input trits for the output node values. This study describes the novel ternary multiplexer, s u c c e s s o r ¯ and p r e d e c e s s o r ¯ cells. The proposed full adder design is evaluated using HSPICE simulation with the standard 32 nm CNFET technology under different operational conditions, including different supply voltages, variation of output load and various operational temperatures. In addition, the sensitivity to process variations of the design is investigated. Finally, the proposed designs are compared with state-of-the-art ternary circuits and based on the simulation results, the proposed full adder cell decreases the power consumption up to 2.3 times lower than the best existing techniques in the literature.

AS8-static random access memory (SRAM): asymmetric SRAM architecture for soft error hardening enhancement

Abstract: Soft errors in semiconductor memories occur due to charged particle strikes on sensitive nodes. Technology and voltage scaling increased dramatically the susceptibility of static random access memories (SRAMs) to soft errors. In this study, the authors present AS8-SRAM, a new asymmetric memory cell that enhances the soft error resilience of SRAMs by increasing the cells critical charge. They run Simulation Program with Integrated Circuit Emphasissimulations and system level experiments to validate the AS8-SRAM cell characteristics at circuit level and evaluate the energy and reliability effectiveness of an AS8-SRAM-based cache memory. The authors’ results show that AS8-SRAM presents up to 58 times less failures in time compared to six-transistor SRAM. Moreover, based on embedded benchmarks experimentations, AS8-SRAM achieves up to 22% reduction in energy-delay product without any considerable loss in performance.

Carbon nanotube FET-based low-delay and low-power multi-digit adder designs

Abstract: Several field-effect transistor (FET)-based device technologies are emerging as powerful alternatives to the classical metal oxide semiconductor FET (MOSFET) for computing applications. The focus of this study is on arithmetic circuit design in carbon nanotube FET (CNTFET) technology. In particular, the authors develop low-delay and low-power multi-ternary digit CNTFET-based adder designs. The proposed designs are based on unary operators of multi-valued logic. Efficient designs for primitives such as ternary half-adder (HA) and full-adder are developed and they are used to obtain low-complexity multi-digit adders based on the notions of conditional sum and carry lookahead. Extensive HSPICE simulations reveal that the power-delay product of the proposed CNTFET-based HA and full-adder are roughly 20 and 50%, respectively, of that of recent designs. Further, the proposed CNTFET-based conditional sum adder has a power-delay product of approximately 27% of that of a multi-trit design derived from a recent single-trit adder design (for a load capacitance of 2 fF). Moreover, the proposed CNTFET-based carry lookahead adder has low delay in comparison with the conditional sum strategy for different supply voltages. Studies on robustness of the designs are also reported.

Design of non-restoring divider in quantum-dot cellular automata technology

Abstract: Among all basic arithmetic operations, the division is the most complex one. On the other hand, working on post-complementary metal–oxide–semiconductor (CMOS) technology attracts attention of many researchers, while the progress of miniaturisation in CMOS technology faced physical limits. Therefore, in this study, the authors propose a non-restoring divider in quantum-dot cellular automata (QCA), as one of the most promising technology. To achieve an efficient divider, they propose a novel 1 bit full-adder and take advantage of improved design of XOR gate. This design has considerable improvements in terms of cell numbers, delay and area, compared with other dividers. The suggested design is simulated in QCADesigner software and acceptable results are achieved.

Modelling and performance analysis of dielectric inserted side contact multilayer graphene nanoribbon interconnects

Abstract: In this work, performance of dielectric inserted side contact multilayer graphene nanoribbon (Di-side-GNR) coupled interconnects using unconditionally stable finite-difference time-domain (USFDTD) technique has been investigated. The model developed for the same, overcomes the limitation of Courant stability criterion prevalent in the conventional finite-difference time-domain (FDTD) technique. The proposed model accurately analyses the crosstalk effect in copper (Cu), side contact multilayer graphene nanoribbon and Di-side-GNR interconnects. It is found that the crosstalk effect is least in Di-side-GNR amongst the three types of interconnect considered in this study. The proposed model and HSPICE simulation results match closely. Further, for transient analysis USFDTD technique based proposed model takes nearly 1.5 times lesser CPU runtime compared to the conventional FDTD technique.

Spacer engineering for performance enhancement of junctionless accumulation-mode bulk FinFETs

Abstract: This study investigates the performance of the junctionless accumulation-mode (JAM) bulk FinFETs. Different electrical parameters are simulated and analysed for the device with different gate spacer's lengths and materials. Spacers having dielectric constants between 1 and 22 are used to compare the device performance, whereas different spacer lengths are considered in order to understand the effect of spacer engineering. Importance is given to investigate the analogue and radio frequency (RF) performances by computing transconductance ( g m ), transconductance generation factor ( g m / I d ), cut-off frequency ( f T ), maximum frequency of oscillation ( f max ) and so on. The device under study shows better ON-OFF current ratio, transconductance, transconductance generation factor using gate spacer having high k -value. However, because of increased gate capacitances, its RF performance degrades with increase in dielectric constant of the spacer used. The effects of downscaling of channel length ( L ) on analogue performance of the proposed junctionless accumulation mode device have also been presented. It has been observed that the analogue/RF performance of the device can be improved by reducing the spacer length.

Low-power and high-speed 13T SRAM cell using FinFETs

Abstract: Fin field-effect transistors (FinFETs) are replacing the traditional planar metal-oxide-semiconductor FETs (MOSFETs) because of superior capability in controlling short channel effects, leakage current, propagation delay, and power dissipation. Planar MOSFETs face the problem of process variability but the FinFETs mitigate the device-performance variability due to number of dopant ions. This work includes the design of static-random access memory (SRAM) cell using FinFETs. The performance analysis of the ST11T, proposed ST13T SRAM cell, and with power gating sleep transistors is given in this study using the Cadence Virtuoso Tool (V.6.1). Owing to its improved gate controllability and scalability, the FinFET transistor structure is better than the conventional planar complementary MOS technology. The proposed design aims at the power reduction and speed improvement for the SRAM cell. From the result it is clear that optimised proposed FinFET-based ST13T SRAM cell is 92% more power efficient with the use of power gating technique, i.e. sleep transistors approach and having 12.84% less delay due to the use of transmission gates in the access path.

Double gate symmetric tunnel FET: investigation and analysis

Abstract: In this work, using calibrated 2D simulations, the authors first demonstrate that the OFF-state current and subthreshold swing (SS) are significantly high for the double gate Ge source/drain symmetric p-n-p tunnel field effect transistor (TFET) with a silicon channel without n + pockets at the source- and drain-channel interfaces. They further establish that using $n^{+}$n+ pockets at the source- and drain-channel interface, the Ge source/drain symmetric p-n-p TFET exhibits a 130 times improvement in I ON / I OFF ratio and a 26% reduction in SS due to the two orders of magnitude reduction in its OFF-state current when compared with the one without the n + pockets. The results also indicate that the Ge source/drain symmetric p-n-p TFET suffers from a low output conductance at low drain voltages. Since the proposed device exhibits bidirectional current flow, it can be easily integrated with the conventional complementary metal-oxide semiconductor technology.

On the realisation of canonic single-resistance-controlled oscillators using third generation current conveyors

Abstract: This study presents findings of a search on canonic single-resistance-controlled oscillators (SRCOs) using third generation current conveyors (CCIIIs). From seven identified canonic SRCOs, five are completely new. All seven canonic SRCOs use two CCIIIs, two grounded capacitors and three resistors. The condition of oscillation and frequency of oscillations are decoupled and simple. The workability of the presented oscillator configurations have been confirmed by PSPICE simulation and hardware experiments.

Sensitivity of effective relative permeability for gapped magnetic cores with fringing effect

Abstract: Magnetic component tolerances are caused by variations in air-gap and core relative permeability. This study presents the derivation for sensitivity of effective relative permeability to variations in the relative core permeability and relative gap length for magnetic cores with and without fringing effect. The expressions for the fringing factor and effective relative permeability for the magnetic cores have been derived. The effect of air-gap on the core properties, which includes core power loss density, magnetic flux density, and magnetic field intensity is addressed for cores used in low-frequency and high-frequency applications. An example core is selected to support the theoretical predictions. The expressions to determine the inductor tolerances are presented.

Multiple memristor series–parallel connections with use in synaptic circuit design

Abstract: With the increase of research interest on memristors, various single or multiple memristor configurations have been integrated with advanced complementary metal-oxide-semiconducor technology, which promises efficient implementations of synaptic connections in neuromorphic computing systems, or computing elements in signal processing systems. In this study, multiple memristors, both in series and parallel connections, and their characteristics are further studied including the transient behaviours when asynchronous change happens and the composite electric properties in steady state etc. Particularly, the specific conditions to reach steady state and produce composite memristive effects are presented in detail. Furthermore, several synaptic memristor circuits based on series and parallel connections are also discussed.

Low-voltage commercial super-capacitor response to periodic linear-with-time current excitation: a case study

Abstract: The response of a commercial super-capacitor to an applied periodic current excitation in the form of a triangular waveform is investigated in this study. This waveform has a linear-with-time variation which enables linear charging and discharging of the device. A model consisting of a linear resistance R s and a constant phase element is used to describe the super-capacitor impedance and expressions for the voltage across the device, the power, and stored energy are derived using concepts from fractional calculus. Experimental results are shown and an application of the study to super-capacitor parameter extraction is described.

Shadow filters based on DDCC

Abstract: This study presents a new realisation of voltage-mode shadow filters based on low-voltage low-power differential difference current conveyor (DDCC). Thanks to the attractive features of the DDCC, including its capability of performing arithmetic operations, the proposed filters offer the advantage of circuit simplicity, minimum number of active and passive elements, and no need for additional summing circuit, compared to the previous available shadow filter designs. The DDCC was designed and fabricated in Cadence platform using 0.35 μm CMOS AMIS process with supply voltage and power consumption of 1 V and 37 μW, respectively. The presented simulation and experimental results using a real chip validate the functionality of the proposed filters.

MIPSfpga: using a commercial MIPS soft-core in computer architecture education

Abstract: In this study, the authors introduce MIPSfpga and its accompanying set of learning materials. MIPSfpga is a teaching infrastructure that offers access to the non-obfuscated Register-Transfer Level (RTL) source code of the MIPS microAptiv UP processor. The core is made available by Imagination Technologies for academic use and is targeted to a field-programmable gate array (FPGA), making it ideal for both the classroom and research. The supporting materials and labs focus on hands-on learning that emphasises computer architecture, system on chip (SoC) design and hardware–software codesign. Among other things, students learn to set up the MIPS soft-core processor on an FPGA, run and debug programs on the core in simulation and in hardware, add new peripherals to the system, understand the microarchitecture and extend it to support new features, experiment with different cache sizes and content management policies, add new instructions using the CorExtend interface available in MIPS processors, and understand SoCs in embedded systems and how they are designed and built up in layers to run complex software such as Linux.

Optimal synthesis of QCA logic circuit eliminating wire-crossings

Abstract: Wire-crossing plays a pivotal role toward the progress of non-complementary metal-oxide-semiconductor technology. Hefty amount of wire-crossings leads to many complications including cross-talk, colossal power dissipation and high cost function which in turn makes the fabrication difficult. In this regard, this work presents an efficient method for circuit implementation based on majority logic in quantum-dot cellular automata (QCA) with optimum wire-crossing. The authors' proposed method is able to eliminate wire-crossing by the generation and routing of proper intermediate function in the circuit utilising the orientation of the input variable. An algorithm to minimise the number of wire-crossing is also reported. Experimental results establish the effectiveness of the proposed method in circuit level also. Finally, a concrete framework to design a cost-effective logic circuit in QCA ensuring the least/optimum wire-crossing is established.

Efficient and low-complexity hardware architecture of Gaussian normal basis multiplication over GF(2 m ) for elliptic curve cryptosystems

Abstract: In this paper, an efficient high-speed architecture of Gaussian normal basis (GNB) multiplierover binary finite field GF(2 m ) is presented. The structure is constructed by using some regular modules for computation of exponentiation by powers of 2 and low-cost blocks for multiplication by normal elements of the binary field. For the powers of 2 exponents, the modules are implemented by some simple cyclic shifts in the normal basis representation. As a result, the multiplier has a simple structure with a low critical path delay. The efficiency of the proposed multiplier is examined in terms of area and time complexity based on its implementation on Virtex-4 field programmable gate array family and also its application specific integrated circuit design in 180 nm complementary metal-oxide-semiconductor technology. Comparison results with other structures of the GNB multiplier verify that the proposed architecture has better performance in terms of speed and hardware utilisation.

OTFTs compact models: analysis, comparison, and insights

Abstract: It is challenging to develop a physically based compact model for an organic thin-film transistor (OTFT). Moreover, there is still a lack of a universal model that would cover the huge variety of materials and device structures available for state-of-the-art OTFTs. Different models of charge transport phenomenon in organic semiconductors are briefly explained, since such phenomenon constitutes the basis of a physically based compact model of an OTFT. An introduction to the basic principles dictated on compact models suitable for Computer Aided Design (CAD) simulators is stated. Six reported models are presented and analysed with an emphasis on their primary assumptions and applicability aspects. Furthermore, the selected compact models are compared with experimental results provided by a fabricated OTFT. Finally, the authors conclude recommendations for advancing OTFT compact modelling in order to reach a more enhanced model that could characterise most recently reported OTFTs.

Ultra-low-power, high PSRR CMOS voltage reference with negative feedback

Abstract: Based on negative feedback technique, a complementary metal-oxide semiconductor (CMOS) voltage reference with ultra-low-power, low supply voltage and high-power supply rejection ratio (PSRR) is proposed and simulated using a 0.18 standard micrometre CMOS technology. The operating supply voltage ranges from 0.85 V to 2.5 V and the temperature ranges from -20°C to 80°C. The voltage reference can achieve a temperature coefficient of 16.3 ppm/°C and line sensitivity as low as 0.086 ppm/V, without the use of resistors or special devices, consuming 202 nA current at 27°C. Besides, the PSRR is only -113 dB at 1 Hz, -64 dB at 1 kHz, respectively.

Investigation on dynamic equalisation performance of lithium battery pack management

Abstract: Lithium batteries must be connected in series to achieve large capacity and high-power output. Battery management system (BMS), which is designed to protect battery pack from damage and increase battery life, is important in electrical power system. The present equalisation techniques have many disadvantages: The passive balancing wastes energy and generates heat, while active balancing is complex. This study proposes an intelligent BMS with dynamic equalisation (DBMS) which contains active and passive balancing circuit independently per cell. Experimental results indicate that DBMS can reduce the inconsistency among cells. Moreover, the DBMS can assist battery stack to store and release more energy. Besides, the battery stack with DBMS gives an energy efficiency of 96.5% which is 7.7% higher than that without balancing. In addition, the battery stack with DBMS can reduce the maximum state of charge difference of cells from 10.415% to 4.51% after three charge-discharge cycles. What is more, the DBMS is simple and can decrease the auxiliary power level and the system heat. Such a DBMS will help us to provide a high-performance battery pack.

NeuroMonitor: a low-power, wireless, wearable EEG device with DRL-less AFE

Abstract: Electroencephalography (EEG) is an effective tool to non-invasively capture brain responses. Traditional EEG analogue front end (AFE) requires a driven right leg (DRL) circuit that restricts the number of channels of the device. The authors are proposing a new `DRL-less' AFE design, and have developed a wearable EEG device (NeuroMonitor), which is small, low-power, wireless, and battery operated. The EEG device with two independent channels was fabricated on an 11.35 cm 2 PCB that contained a system-on-a-chip microcontroller, a low-noise instrument amplifier, a low-power Bluetooth module, a microSD, a microUSB, and a LiPo battery. The DRL circuit was eliminated by utilising the high CMRR instrument amplifier with differential inputs, and followed by a modified high-Q active Twin-T notch filter (( f c Notch = 60 Hz, -38 dB). The signal was conditioned with a band-pass filter composed of a two-stage 2nd-order Chebyshev-I Sallen-Key low-pass filter cascaded with a passive 2nd-order low-pass filter ( f c LP = 125 Hz) and a 1st-order passive high-pass filter ( f c HP = 0.5 Hz). Finally, the signal was amplified to achieve an overall gain of 55.84 dB, and digitised with a 16-bit delta-sigma ADC (256 sps). The prototype weighs 41.8 gm, and has been validated against a research-grade EEG system (Neuroscan).

Multi-resonant gate drive circuit of isolating-gate GaN HEMTs for tens of MHz

Abstract: Research of power supplies for megahertz (MHz) class applications such as a semiconductor manufacturing apparatus, induction heater and wireless transfer is carried out. A liner amplifier is generally used for MHz class applications. The loss of the power devices on a liner amplifier is theoretically high. To reduce the loss, the class E and Φ 2 inverters are proposed, and some of the resonant gate drive circuits (GDC) are utilised at those of the gate port. However, the control signal of the GDC becomes complicated due to the additional switches. Moreover, the switches in the GDC perform the hard-switching, and the drive loss can thus be increased. In this study, a multi-resonant gate drive circuit is proposed, and its design method is introduced. It can generate the trapezoidal wave gate-to-source voltage with the simple control signal, and zero voltage switching operation is achieved at the switches of the gate drive circuit. First, its operation is experimentally verified. Secondly, the drive loss is also compared with that of the conventional circuit. Furthermore, its operation with the class E inverter with a cascode GaN high-electron-mobility transistor (HEMT) is confirmed at the switching frequency 13.56 MHz.

Dynamics and control of voltage multiplier cells integrated boost converter

Abstract: This paper presents a reduced order sliding mode controller based on hysteresis modulation for a boost converter with single voltage multiplier cell (VMC) operating in continuous conduction mode. Although VMC integrated boost converter improves the static gain without extreme duty cycle, it increases the number of components which in turn increases the order of the system. Due to complexity in control of higher order converters, a reduced order sliding mode controller is suggested in this study to reduce the number of sensors. Both static and dynamic performances are improved by considering only two control parameters, the input inductor current and the output capacitor voltage of the VMC integrated boost converter. The robustness of SMC over line variation, load variation and parameter variations are revealed through simulation and compared with conventional PI controller. Inrush current of the VMC integrated boost converter is observed to be high and a startup control with an auxiliary diode is incorporated. A prototype model of a 100 W boost converter with single VMC controlled by SMC is designed and implemented to validate the simulated results. A VMC integrated boost converter with SMC approach offers high voltage gain at reduced duty cycle with improved dynamic characteristics.

Positive Feedback Technique and Split-Length Transistors for DC-Gain Enhancement of Two Stage Op-Amps

Abstract: This study presents the design and simulation of a fully differential two-stage op-amp in a 0.18 μm complementary metal-oxide-semiconductor process with a 1.8 V supply voltage. In this op-amp, positive feedback technique and split-length transistors (SLTs) are employed to increase the DC-gain of the op-amp by about 22 dB without affecting the unity-gain bandwidth (UGBW), stability, power dissipation and output voltage swing of the conventional two-stage op-amp. A comprehensive analysis is provided for differential-mode gain, common-mode gain, power supply rejection ratio, input-referred noise, input offset, frequency response and the effect of using SLTs on DC-gain sensitivity. The proposed op-amp is utilised in a flip-around sample-and-hold amplifier (SHA). The output spectrum of the SHA shows the total harmonic distortion of 0.0023%. The post-layout and Monte Carlo simulation results show that the proposed op-amp has better performance than the state-of-the-art designs.

Comparison of conventional and regenerative electrostatic energy harvesters

Abstract: This study presents a performance comparison of two green electrostatic energy harvesters based on force-sensitive mechanically variable capacitors. A startup battery is required in the conventional electrostatic energy harvester to precharge the mechanically variable capacitor. This adds an extra element to the device and increases the harvester's size and weight. The proposed harvester does not need a startup battery, operates in a regenerative mode, and provides a similar output power. It has a compact size and can start from low voltages. The conventional and regenerative harvesters were developed using mechanically variable capacitors fabricated with renewable materials (i.e. nanocellulose and carbon-coated nanocellulose). The flexible nanocellulose films and the cost-effective fabrication process make the energy harvesters suitable for powering low-power and wearable devices. The bio-based materials further reduce the environmental impact of the devices. Prototypes of the two energy harvesters were built, and their performances were compared on the basis of simulation and measurement results. Both simulation and experimental results are shown to demonstrate the startup and scalable energy availability of the proposed regenerative electrostatic energy harvester for driving low-power devices, such as wireless sensor networks.

Design and performance evaluation of two novel linearisation circuits for giant magneto-resistance based sensors

Abstract: This study presents two simple and efficient linearisation circuits for giant magneto-resistance (GMR)-based magnetic field sensors. GMR sensors are commonly available in wheatstone-bridge form, comprising two active GMR and two passive GMR elements. The output of such a sensor possesses a non-linear dependence on the input magnetic field. The proposed linearisation circuits operate on the output of a GMR sensor and provide a linear output with respect to the magnetic field. The first GMR linearisation circuit (GLC1) is based on an enhanced feedback compensation approach, while the second (GLC2) scheme uses a constant current technique. The methodologies of the schemes are described using mathematical derivations. Detailed analyses of the schemes are carried out to bring out the effects of circuit and sensor non-idealities on circuit performance. Further, the circuits were implemented on printed circuit boards and tested. Test results showed the capability of GLC1 and GLC2 to produce linear transfer characteristics. A prototype GMR sensor unit was then fabricated and tested with the developed circuits. Output non-linearity obtained during the experimentation was around 0.7%. Analyses of the results proved the superior performance of GLC1 and GLC2 over the existing schemes.

Heterogeneous energy-sparing reconfigurable logic: spin-based storage and CNFET-based multiplexing

Abstract: Field programmable gate array (FPGA) attributes of logic configurability, bitstream storage, and dynamic signal routing can be realised by leveraging the complementary benefits of emerging devices with complementary metal oxide semiconductor (CMOS)-based devices. A novel carbon/magnet lookup table (CM-LUT) is developed and evaluated by trading off a range of mixed heterogeneous technologies to balance energy, delay, and reliability attributes. Herein, magnetic spintronic devices are employed in the configuration memory to contribute non-volatility and high scalability. Meanwhile, carbon nanotube field-effect transistors (CNFETs) provide desirable conductivity, low delay, and low power consumption. The proposed CM-LUT offers ultra-low power and high-speed operation while maintaining high endurance re-programmability with increased radiation-induced soft-error immunity. The proposed four-input one-output CM-LUT utilises 41 CNFETs and 20 magnetic tunnel junctions for read operations and 35 CNFET to perform write operations. Results indicate that CM-LUT achieves an average four-fold energy reduction, eight-fold faster circuit operation and 9.3% reconfiguration power delay product improvement in comparison with spin-based look-up tables. Finally, additional hybrid technology designs are considered to balance performance with the demands of energy consumption for near-threshold operation.