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JournalISSN: 1751-8601

Iet Computers and Digital Techniques 

Institution of Engineering and Technology
About: Iet Computers and Digital Techniques is an academic journal published by Institution of Engineering and Technology. The journal publishes majorly in the area(s): Field-programmable gate array & Network on a chip. It has an ISSN identifier of 1751-8601. It is also open access. Over the lifetime, 642 publications have been published receiving 5988 citations. The journal is also known as: Institution of Engineering and Technology computers and digital techniques & IET computers and digital techniques.


Papers
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Journal ArticleDOI
TL;DR: A novel SEU/SET-tolerant latch called feedback redundant SEU-tolerance latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are usedto filter SETs.
Abstract: Single event upsets (SEUs) and single event transients (SETs) are major reliability concerns in deep submicron technologies. As technology feature size shrinks, digital circuits are becoming more susceptible to SEUs and SETs. A novel SEU/SET-tolerant latch called feedback redundant SEU/SET-tolerant latch (FERST) is presented, where redundant feedback lines are used to mask SEUs and delay elements are used to filter SETs. Detailed SPICE simulations have been done to evaluate the proposed design and compare it with previous latch designs. The results show that the SEU tolerance of the FERST latch is almost equal to that of a TMR latch (a widely used latch which is the most reliable among the previous latches); however, the FERST latch consumes about 50% less energy and occupies 42% less area than the triple modular redundancy (TMR) latch. Furthermore, the results show that more than 90% of the injected SETs can be masked by the FERST latch if the delay size is properly selected.

109 citations

Journal ArticleDOI
TL;DR: Improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits are demonstrated.
Abstract: This study presents new low-power multiple-valued logic (MVL) circuits for nanoelectronics. These carbon nanotube field effect transistor (FET) (CNTFET)-based MVL circuits are designed based on the unique characteristics of the CNTFET device such as the capability of setting the desired threshold voltages by adopting correct diameters for the nanotubes as well as the same carrier mobility for the P- and N-type devices. These characteristics make CNTFETs very suitable for designing high-performance multiple- V th circuits. The proposed MVL circuits are designed based on the conventional CMOS architecture and by utilising inherently binary gates. Moreover, each of the proposed CNTFET-based ternary circuits includes all the possible types of ternary logic, that is, negative, positive and standard, in one structure. The method proposed in this study is a universal technique for designing MVL logic circuits with any arbitrary number of logic levels, without static power dissipation. The results of the simulations, conducted using Synopsys HSPICE with 32 nm-CNTFET technology, demonstrate improvements in terms of power consumption, energy efficiency, robustness and specifically static power dissipation with respect to the other state-of-the-art ternary and quaternary circuits.

92 citations

Journal ArticleDOI
TL;DR: A three-factor control protocol for universal serial bus (USB) on an elliptic curve cryptosystem (ECC) that improves the security, efficiency and usability of the authentication process and uses much smaller key sizes.
Abstract: This study proposes a three-factor control protocol for universal serial bus (USB) on an elliptic curve cryptosystem (ECC). USB is a universal interface used in an enormous number of devices. It has become the most popular interface standard for computer connections. However, since USB provides high transmission speed and is very convenient to carry, many workplace and commercial establishments have prohibited their employees from using USB devices. This precaution is an important way to prevent confidential data leaks via USB devices, as USB connections lack security management. Therefore the authors use a three-factor control protocol to ensure the security of USB connections. The proposed authentication protocol combines biometric, password and smart card to provide high security on the USB mutual authentication. To provide secure and efficient transmission between the user and the USB server, the proposed protocol adopts ECC to encrypt data. Compared to other encryption methods, the proposed protocol uses much smaller key sizes. As a further benefit, this protocol reduces the smart card computational cost and provides an efficient transmission for USB devices. This new scheme improves the security, efficiency and usability of the authentication process. More studies on USB are needed.

76 citations

Journal ArticleDOI
TL;DR: LBDR (logic-based distributed routing) is proposed as a new routing method that removes the need of using routing tables at all and enables the implementation of many routing algorithms on most of the practical topologies in a multi-core system.
Abstract: Chip multiprocessors (CMPs) are gaining momentum in the high-performance computing domain. Networks-on-chip (NoCs) are key components of CMP architectures, in that they have to deal with the communication scalability challenge while meeting tight power, area and latency constraints. 2D mesh topologies are usually preferred by designers of general purpose NoCs. However, manufacturing faults may break their regularity. Moreover, resource management frameworks may require the segmentation of the network into irregular regions. Under these conditions, efficient routing becomes a challenge. Although the use of routing tables at switches is flexible, it does not scale in terms of latency and area due to its memory requirements. Logic-based distributed routing (LBDR) is proposed as a new routing method that removes the need for routing tables at all. LBDR enables the implementation of many routing algorithms on most of the practical topologies we may find in the near future in a multi-core system. From an initial topology and routing algorithm, a set of three bits per switch/output port is computed. Evaluation results show that, by using a small logic, LBDR mimics the performance of routing algorithms when implemented with routing tables, both in regular and irregular topologies. LBDR implementation in a real NoC switch is also explored, proving its smooth integration in the architecture and its negligible hardware and performance overhead.

73 citations

Journal ArticleDOI
TL;DR: A novel design is provided for the BCD-digit multiplier, which can serve as the key building block of a decimal multiplier, irrespective of the degree of parallelism, in semi- and fully parallel hardware decimal multiplication units.
Abstract: With the growing popularity of decimal computer arithmetic in scientific, commercial, financial and Internet-based applications, hardware realisation of decimal arithmetic algorithms is gaining more importance. Hardware decimal arithmetic units now serve as an integral part of some recently commercialised general purpose processors, where complex decimal arithmetic operations, such as multiplication, have been realised by rather slow iterative hardware algorithms. However, with the rapid advances in very large scale integration (VLSI) technology, semi- and fully parallel hardware decimal multiplication units are expected to evolve soon. The dominant representation for decimal digits is the binary-coded decimal (BCD) encoding. The BCD-digit multiplier can serve as the key building block of a decimal multiplier, irrespective of the degree of parallelism. A BCD-digit multiplier produces a two-BCD digit product from two input BCD digits. We provide a novel design for the latter, showing some advantages in BCD multiplier implementations.

73 citations

Performance
Metrics
No. of papers from the Journal in previous years
YearPapers
202310
202212
202137
202037
201954
201834