Showing papers in "Iet Power Electronics in 2018"

Multi-level inverter with combined T-type and cross-connected modules

Abstract: This study presents a new topology of switched-capacitor (SC) multilevel inverter, which is able to step-up input DC voltage to a multilevel AC waveform. This single source inverter is designed based on series connection of the capacitors that charged by input DC sources through a SC network. The proposed modular inverter uses famous T and cross-connected modules that can be simply extended to higher output voltages without increasing the amount of total standing voltage and peak inverse voltage of switches. It generates positive and negative voltage levels inherently, which eliminates requirements of H-bridge inverters that are traditionally used to achieve a bipolar output voltage. Analysis shows that the voltage stress on components, cost, efficiency and losses are kept in acceptable range especially for higher-voltage levels. Capacitor's voltage self-balancing is another inherent advantage of this modular topology which leads to simplify control strategy and eliminate excess balancing circuit. Performance of a six-step proposed structure is evaluated by theoretical analysis, simulation and experimental results.

Application of swarm optimisation-based modified algorithm for selective harmonic elimination in reduced switch count multilevel inverter

Abstract: Multilevel inverters (MLIs) are nowadays extensively used in integration with renewable energy sources and in drives applications. The converter cost and voltage quality improvement are the utmost importance in such application of MLI. A six-switch seven-level reduced switch symmetrical MLI (6S-7L MLI) is proposed here. Compared to the conventional and similar existing MLI topologies, the proposed MLI uses less active switches and has less driver circuit requirement. A particle swarm optimisation (PSO)-based modified selected harmonic elimination technique is derived and analysed for computing optimal switching angles of proposed 6S-7L MLI to eliminate third- and fifth-order harmonics. Moreover, the performance of the proposed algorithm is compared with the two most commonly used PSO variants. The analysis shows the modified version of PSO is most suitable for optimising the output voltage of proposed MLI through targeted harmonic elimination. The proposed topology is investigated through simulation by applying the calculated switching angles using modified PSO algorithm. Finally, a single-phase experimental prototype is designed to verify the validity of the proposed structure.

Review of recent advancements of direct torque control in induction motor drives – a decade of progress

Abstract: Since the invention of direct torque control (DTC) in later 1980s for alternating current (AC) motor drives, it has undergone many modifications to improve the control strategy. This study provides a comprehensive review of recent advancements of DTC of induction motor (IM) for the past one decade. Strategies adopted to improve the performance of DTC based on switching table, constant switching frequency operation, intelligent control, sensorless control and predictive control are extensively discussed with its key results and algorithms.

Single-phase multilevel inverter topologies with self-voltage balancing capabilities

Abstract: In this study, two new structures of single-phase hybrid multilevel inverter are proposed for both symmetrical and asymmetrical configurations that can be employed in drives and control of electrical machines and connection of renewable energy sources. The proposed configuration uses a less number of semiconductor devices and DC sources as compared with conventional and newly developed topologies which lead to a reduction in cost and installation area. The proposed topology poses a vital advantage of self-voltage balancing of its capacitor voltage regardless of load type, load dynamics and modulation index. Also, the proposed topology is expanded in a cascaded fashion which reduces the complexity and improves the performance significantly. A wide range of comparison is done with conventional and newly developed topologies to show the superior performance of proposed topologies regarding a total number of switches and DC sources. The multi-carrier pulse-width modulation strategy is adopted for generating switching pulses for respective switches. A laboratory prototype is developed for testing the performance of the proposed topology for 9-level and 17-level inverters.

Selective harmonic elimination in multilevel inverter using hybrid APSO algorithm

Abstract: This study presents selective harmonic elimination pulse width modulation technique-based hybrid asynchronous PSO-Newton-Raphson (APSO-NR) algorithm for the elimination of undesired harmonics in cascaded H-bridge multilevel inverter. The proposed algorithm is applicable to all levels of MLI having equal and non-equal DC sources. In the proposed method, ring topology-based APSO algorithm is hybrid with NR method. APSO worked as a global search technique and NR is used for the refinement of best solutions. APSO-NR is applied to the seven-level inverter to eliminate fifth and seventh harmonics. In simulations, the performance of the proposed algorithm is compared with genetic algorithm, bee algorithm and particle swarm optimisation. The results proved that the proposed algorithm is efficient, and gives more precise firing angles in less number of iterations with high capability of tackling local optima. For the 48% of modulation index range, APSO-NR minimised the fitness function value lower than (10 -25 ). The proposed algorithm is validated through the experimental implementation of the three-phase seven-level inverter.

Step-up switched-capacitor module for cascaded MLI topologies

Abstract: This study presents a new module for cascaded multilevel inverters (MLIs) based on switched-capacitor technique. Charging of the capacitors in the proposed switched-capacitor cell is performed in a self-balancing form. Voltage boosting capability and generating bipolar voltage levels without requiring an end-side H-bridge inverter are remarkable benefits of the proposed topology. Thereby, semiconductors with lower-voltage ratings are applied in its circuit. Comparison of the proposed inverter with traditional topologies and other recently introduced MLIs shows that the proposed topology reduces the number of circuit elements and also total blocking voltage by switches. Moreover, the proposed inverter configuration and its operating principle, capacitance, and power loss calculations, and also topology extension to achieve higher levels are investigated in depth. Finally, an experimental prototype is built to verify the theoretical analysis and feasibility of the proposed topology.

Analysis and design of voltage-lift technique-based non-isolated boost dc–dc converter

Abstract: In this study, a new structure is proposed for non-isolated boost dc-dc converters using voltage-lift technique. The increasing voltage gain in the proposed converter is achieved step-to-step by a simple structure. In the proposed converter, there is a direct connection to an inductor in input side which provides free current ripple for the input source. Here, the proposed converter performance analysis and their relations are presented in continuous conduction mode and discontinuous conduction mode as well as voltage gain equations for each mode in detail. Then, switching current stress equations in each mode and critical inductance equations are extracted for design considerations. Finally, the carried theoretical analysis and satisfying operation of the proposed converter are verified via experimental results of laboratory prototype.

Crisscross switched multilevel inverter using cascaded semi-half-bridge cells

Abstract: A new cascaded multilevel inverter (MLI) is presented with the aim of utilising lesser number of switches, better modularity and reduced voltage stress. The new structure configured under symmetric and asymmetric mode, produces all odd and even voltage levels. This structure comprises semi-half-bridge cells connected in series with crisscross switches to generate any target level for synthesising the sinusoidal output voltage waveform. In extension to the proposed topology, subinverters derived from the proposed MLI are cascaded with an objective to produce more voltage levels with reduced standing voltage. Compared with the cascading H-bridge topology, the proposed MLI and the extended version uses lesser number of semi-conductor switches. The MATLAB R2013b-based simulation results along with the experimental results validate the proposed topology.

Single-phase multilevel inverter based on switched-capacitor structure

Abstract: This study proposes a new topology for multilevel inverters based on switched-capacitor structure. The proposed topology uses capacitor charged/discharged characteristic to boost the output voltage without employing magnetic elements. The proposed circuit configuration has fewer components, including switches, voltage sources, and capacitors comparing with the conventional similar topologies. A phase disposition pulse-width modulation method is used to enhance the output waveform quality of the proposed inverter. Nine-level and 17-level configurations are simulated. To verify the operating principle, the experimental results for a nine-level inverter topology are presented.

Modular non-isolated multi-input high step-up dc–dc converter with reduced normalised voltage stress and component count

Abstract: This study proposes a modular high voltage gain structure for non-isolated non-coupled inductor based multi-input (NINCIBMI) dc-dc converters. Proposed topology can produce higher voltage gains per number of components (switch, diode, capacitor and inductor) than other NINCIBMI topologies. In other words, the proposed topology uses less number of components for achieving the same voltage gain. This property can lead to reduced cost, size, weight and complexity of topology. Also, proposed topology benefits from continuous input current. Despite the high voltage gain of proposed topology, it has considerably low normalised voltage stress (NVS) on its switches/diodes. Another important advantage of proposed topology is that, as the number of input units increase, the voltage gain increases too, but the NVS on switches/diodes decreases. The proposed topology is suggested for low and medium power applications. The 2-input version of proposed topology has been studied in detail and different operational modes and steady-state analyses have been presented. For a better evaluation, proposed topology has been compared with recently presented novel multi-input high step-up structures. The 2-input version has also been experimentally implemented. Obtained results confirm appropriate performance of proposed topology.

Quadratic buck–boost converter with positive output voltage and minimum ripple point design

Abstract: This study presents a novel topology of a buck-boost converter that features: (i) quadratic voltage gain; (ii) positive output voltage with respect to the input; (iii) continuous input current. Moreover, as the main contribution, (iv) it features a minimum ripple design, for which input current and output voltage ripples are simultaneously cancelled at the desired operating point. It is also shown that even though the duty cycle deviates from a nominal minimum ripple point, the converter exhibits a significantly low switching ripple percentage within a full operation range. The operation mechanism, steady-state equations and overall analysis are presented. Furthermore, simulations and experiments were performed to validate the theory.

High voltage gain dc–dc converters based on coupled inductors

Abstract: In this study, two new high voltage gain dc-dc converters are proposed. In the proposed converters, two coupled inductors are used to increase and decrease the output voltage more than the traditional dc-dc converters in boost and buck operations, respectively. In these converters, by increasing the turns ratio of the coupled inductors, the voltage conversion ratio is increased for the whole range of duty cycles. The proposed topologies are analysed in all operating modes and the values of current stresses of all switches, voltage stresses on all switches, input current ripples and voltage gains are calculated for boost and buck operations. Finally, the accurate performance of the proposed converters is verified through experimental and Power System Computer Aided Design (PSCAD)/Electro Magnetic Transient Design and Control (EMTDC) simulation results.

Design and implementation of active neutral-point-clamped nine-level reduced device count inverter: an application to grid integrated renewable energy sources

Abstract: Multilevel inverters are one of the preferred choices in medium-voltage and high-power applications in the recent past. Active neutral-point-clamped (ANPC) inverter is the most popular topology, especially in the class of five-level (5L) inverters. In this study, a nine-level topology with improved output waveform quality is proposed based on ameliorating the 5L ANPC inverter with least modifications. The addition of only two switches operating at line frequency to the conventional 5L ANPC inverter while maintaining an identical precursor part count is the proposed modification. A logic form equation-based active voltage balancing scheme that is independent of load current and power factor is developed to regulate the flying capacitor voltage at the reference value. The operating principle, salient features, and the developed control scheme are comprehensively detailed. The operation of the proposed inverter considering a grid integrated case is simulated in MATLAB/Simulink, and the results corresponding to steady-state and dynamic conditions are presented. The benefits of the proposed topology are elucidated by comparing it with other classic topologies considering various prominent viewpoints. This comparison has illustrated the proposed topology's distinctive characteristics and profound advantages. The performance validation, feasibility, and practicability of the proposed inverter are established through the experimental results obtained from a laboratory-scale prototype.

Comparison of SiC MOSFET-based and GaN HEMT-based high-efficiency high-power-density 7.2 kW EV battery chargers

Abstract: As two exemplary candidates of wide-bandgap devices, SiC MOSFETs and GaN HEMTs are regarded as successors of Si devices in medium-to-high-voltage (>1200 V) and low-voltage (<;650 V) domains, respectively, thanks to their excellent switching performance and thermal capability. With the introduction of 650 V SiC MOSFETs and GaN HEMTs, the two technologies are in direct competition in <;650 V domains, such as Level 2 battery chargers for electric vehicles (EVs). This study applies 650 V SiC and GaN to two 240 VAC/7.2 kW EV battery chargers, respectively, aiming to provide a head-to-head comparison of these two devices in terms of overall efficiency, power density, thermal performance, and cost. The charger essentially is an indirect matrix converter with a dual-active-bridge stage handling the power factor correction and power delivery simultaneously. These two chargers utilise the same control strategy, varying the phase-shift and switching frequency to cover the wide input range (80-260 VAC) and wide output range (200 V-450 VDC). Experimental results indicated that at the same efficiency level, the GaN charger is smaller, more efficient and cheaper, while the SiC charger has a better thermal performance.

Active/reactive power control of photovoltaic grid‐tied inverters with peak current limitation and zero active power oscillation during unbalanced voltage sags

Abstract: This paper proposes an analytical expression for the calculation of active and reactive power references of a grid-tied inverter, which limits the peak current of the inverter during voltage sags. The key novelty is that the active/reactive power references are analytically calculated based on the dc-link voltage and grid codes, while they do not depend on the implemented current reference calculation algorithm and, as a general formulation, can be implemented in combination with various current reference calculation algorithms. Furthermore, based on the inverter nominal current and the injected reactive power to the grid during voltage sags, an analytical algorithm is introduced for the calculation of the active power reference, which can be extracted from PV strings. The proposed algorithm ensures that the maximum current capability of the inverter is used for the enhancement of the grid voltages during voltage sags, while it always complies with the reactive power injection requirement of grid codes and avoids increasing the dc-link voltage excessively. An unbalanced current injection algorithm is also applied for the grid-tied inverter which results in zero active power oscillation. Experimental results of a grid-connected 3.3-kVA, three-level, neutral-point-clamped inverter laboratory prototype are presented to demonstrate the effectiveness of the proposed controller.

Comparative study between different optimisation techniques for finding precise switching angle for SHE-PWM of three-phase seven-level cascaded H-bridge inverter

Abstract: Selective harmonic elimination pulse-width modulation (SHE-PWM) works at low-frequency switching, which reduces switching losses, device stress, and increases energy conversion efficiency. So, it can be an effective control strategy for multilevel inverter working on medium-voltage, high-power industrial energy conversion application. It provides desired output voltage by retaining the requested fundamental component as well as eliminating some low-order harmonics. The application of SHE-PWM in industries is having an influence on precise solvability of complex and non-linear equations. This study presents two recently reported optimisation techniques, namely backtracking search algorithm and differential search algorithm (DSA) for obtaining a more accurate solution of the harmonics elimination problem. The superiority of the proposed optimisation algorithms over the well known ancient algorithm such as genetic algorithm, BEE algorithm and particle swarm optimisation have been established by a comparative study with respect to the possibility of attaining global minima, the rank of convergence rate, and inverter performance analysis. Simulation and experimental results validate the efficacy of the DSA optimisation technique for calculating more precise switching angles that totally eliminate 5th- and 7th- order harmonics with fulfilling the requested fundamental component.

High step-up dc/dc converter using switch-capacitor techniques and lower losses for renewable energy applications

Abstract: In this study, a non-isolated high step-up direct current (dc)/dc converter with a diode-capacitor is presented. To obtain high-voltage gain, the voltage multiplier units (diode-capacitor) can be extended to n stages which are used between the phases in up section and down section of the proposed converter. By increasing the number of voltage multiplier units, the nominal value of the components decreases. Therefore, the maximum voltage value of diodes and power switches compared with the output voltage is decreased and finally, the normalised voltage of these devices will decrease, significantly. In addition, the power level of the proposed converter can be increased for different values of duty cycles and voltage multiplier units and also leads to high efficiency. To illustrate the advantages of the proposed converter, comparison results with other topologies are provided. The principle of operation at n = 1, 2 stages, both theoretical analysis and experimental results of two prototypes in 100 and 250 W with operating at 40 kHz are provided.

Non-isolated high gain DC–DC converter with low device stress and input current ripple

Abstract: In this article, a novel DC–DC converter with high voltage gain capability is presented. The proposed converter is synthesised from (i) a basic two-phase interleaved boost converter (IBC) which uses coupled inductors (CIs) instead of discrete inductors and (ii) diode-capacitor multiplier (DCM) cells to achieve higher voltage conversion ratio. The outputs obtained from the interleaved and the DCM stages are judiciously cascaded with the outputs obtained from the secondary winding of the CIs to enhance the voltage gain. The input current is almost ripple free due to the adopted interleaving mechanism. As voltage gain is extended using CIs and DCMs, the voltage stress on the semiconductor devices is minimal and only a fraction (10.5%) of the output voltage. Experimental results obtained from the 18 V/380 V, 150 W prototype converter, operating at a maximum efficiency of 94% under full-load condition, validate the proposed concept. Further, practical results obtained under closed-loop condition confirm that the converter yields a constant output of 380 V DC which is suitable for microgrid application.

Improved dynamic performance of dual active bridge dc–dc converters using MPC scheme

Abstract: Dynamic performance is a key focus of power conversion systems for facing with input and output step-change and disturbance cases. To improve dynamic characteristic of dual-active-bridge dc-dc converters, this study proposes a non-linear model predictive control (MPC) scheme with phase-shift ratio compensation to face with the following extreme conditions: start-up or step change of load resistance, input voltage, and the desired output voltage. Furthermore, in view of the idea of direct current control, MPC scheme using fewer sensors is proposed, which greatly increases the flexibility of control system and reduce the cost. Compared to traditional voltage closed-loop (TVCL) control and model-based phase shift (MPS) control, the salient features of the proposed MPC can be summarised as excellent dynamic performance, weak parameter sensitiveness, in addition, it is also available and effective when the load current sensor is not used. Finally, three control schemes consisting of TVCL, MPS, and the proposed MPC scheme are compared and tested in a scale-down experimental prototype. The above excellent performance of the proposed MPC scheme has been verified by experimental results.

Improved control algorithm for grid-connected cascaded H-bridge photovoltaic inverters under asymmetric operating conditions

Abstract: Here, a single-stage cascaded H-bridge (CHB) inverter is presented for grid-connected photovoltaic (PV) systems. The CHB inverter has separate DC links and allows individual control of PV arrays. The conversion efficiency is high and the harmonic generation is lower than conventional PV inverters. Although the CHB inverter is a good candidate for injection of solar power into grid, its control issues have not been completely solved. One of the main challenges in the CHB inverter is the harmonic generation when the connected PV arrays to the H-bridge cells have different amounts of insolation. This study deals with the asymmetrical operating conditions of PV arrays (or H-bridge cells) in the CHB inverter and presents an analytical equation for determination of cells' modulation indices based on PV arrays data. Then, a control loop is added to the tracking algorithm of conventional control systems to determine whether an H-bridge cell is in the linear modulation or not. In the case of overmodulation, the corresponding DC link voltage is increased by the controller to bring it back to the linear region. The validity of new method is confirmed by simulations and experiments on a seven-level 1.7 kW CHB inverter.

Double-sided CL compensation topology based component voltage stress optimisation method for capacitive power transfer charging system

Abstract: A double-sided capacitor-inductor (CL) compensation topology is proposed for high-power capacitive power transfer (CPT) charging systems with a component voltage stress optimisation to alleviate the voltage stress on passive components and coupling interfaces. First, detailed analysis of the compensation topology characteristic is carried out based on fundamental harmonics approximation analysis method to yield the voltage stress functions against system's parameters. Then, a voltage stress optimisation is presented. Third, system component voltage stress can be reallocated effectively according to the desired requirement by adjusting system parameters accordingly. With the proposed voltage stress optimisation, a CPT prototype is set up to verify the proposed method performance. As per the experiment results, the efficiency of the prototype reaches 87.47% with 1494 W output power from DC to DC at the 1 MHz switching frequency. Besides, the maximum voltage stress is significantly reduced compared to that without optimisation.

Evaluation of bi-directional single-inductor multi-input battery system with state-of-charge balancing control

Abstract: This study presents a bi-directional single-inductor multi-input single-output battery system with state-of-charge (SOC) balancing controller. In the discharging operation mode of the battery system, the SOC balancing between multiple batteries is achieved by adaptively modulating the multipliers of the discharging rate of each battery cell, while maintaining the output voltage regulated at the desired value by modulating the average value of duty cycle of the power converter. The SOC balancing is achieved naturally during the operation of the system without extra energy dissipation or charge transfer between the batteries. In the charging operation mode, each battery can be charged independently by using the same bi-directional power stage. The convergence ability of the SOC balancing controller is discussed and results obtained from a proof of concept experimental prototype are presented and discussed in order to evaluate and validate the operation of the controller and system.

Enhanced boost quasi-Z-source inverters with active switched-inductor boostnetwork

Abstract: This study proposes a new family of high-boost-quasi- Z -source inverters (qZSIs) with combined active switched-inductor boost network. The proposed inverter provides continuous input current and higher-boost voltage inversion capability, shares common ground between the input source and the inverter bridge, which would be applicable for the renewable energy system with low-voltage distributed dc sources. In comparison to the traditional high-boost non-coupled-inductor-type qZSIs, for the same total number of passive/active components used at the impedance network, the proposed topology has higher modulation index with improved output voltage waveform quality, and lower switching voltage stress across the power switches. To produce the same voltage boost factor with the same dc input, the proposed inverter uses smaller inductance values compared with the conventional topologies. Thus, the size and weight of the passive components in the proposed topology can be reduced. This study presents the operating principles, power loss analysis, simulation results and characteristic comparison with those of the traditional high-boost qZSIs. Finally, a laboratory prototype based on the TMS320F28335 digital signal processor with 60 V dc input and 110 Vrms ac output was constructed to verify the effectiveness of the proposed inverter.

Development of fault-tolerant MLI topology

Abstract: Multilevel inverters (MLIs) have developed deep roots in various industrial sectors owing to their advantages over conventional two-level inverters. However, the reliability of the semiconductor devices has been one of the major concerns for the proper functioning of MLI. Therefore, a novel fault-tolerant topology is proposed in this study. The proposed topology is capable to tolerate single- and multi-switch faults. It has lesser device count compared with the most recent work in the field. Moreover, it achieves inherent voltage balancing across capacitors. The proposed fault-tolerant topology is simulated in MATLAB/Simulink and validated experimentally.

Eliminating cross interference between multiple receivers to achieve targeted power distribution for a multi-frequency multi-load MCR WPT system

Abstract: Simultaneous non-contact energy transmission for multiple loads with separate receiving coils is a remarkable advantage of magnetically coupled resonant (MCR) wireless power transfer (WPT). A novel multi-frequency driver configuration for MCR WPT system with multiple loads is proposed, where the receiving resonant tanks are severally tuned at different resonant frequencies to make the loads selective. A methodology of adjusting the resonant frequency of the transmitter is presented to satisfy diverse energy requirements of specific loads. However, the cross interference from non-targeted frequencies inherently exerts an influence between multiple receivers, and thus makes power allocation non-constrained through multi-coupling channels, which increase the difficulty of power control and parameters design. In order to reduce and further eliminate the influences of the cross interference and realise targeted power distribution for selective loads, three types of parallel and series resonant compensation circuits are introduced into receivers. By flexibly utilising the impedance characteristics of parallel and series resonant networks, the proposed compensation circuits are proved to be effective, significantly reducing the cross interference and exclusively delivering power to the selective loads corresponding to pre-tuned resonant frequencies. Finally, the experimental results from a prototype have confirmed the effectiveness of the proposed methods.

Model predictive control methods of leakage current elimination for a three-level T-type transformerless PV inverter

Abstract: This study presents finite control set model predictive control (FCS-MPC) methods to eliminate leakage current for a three-level T-type transformerless photovoltaic (PV) inverter without any modification on topology or any hardware changes. The proposed FCS-MPC methods are capable of eliminating the leakage current in the transformerless PV system by applying the defined candidate voltage vector (VV) combinations with only six medium and one zero VVs (6MV1Z) or three large and three small VVs, which generate constant common-mode voltage to perform the optimisation in every control period. With fewer VVs used for the optimisation, the computational burden can be significantly reduced. Furthermore, comparative analysis is performed to show that among these proposed methods, the 6MV1Z method can achieve satisfactory performances in both grid current tracking and neutral point potentials balance control even with less number of candidate VVs, which exhibits the FCS-MPC as an alternative control strategy to be used in the grid-connected transformerless PV system. Finally, experiments are performed to validate the analysis and the effectiveness of the proposed methods.

Non-isolated high step-up three-port converter with single magnetic element for photovoltaic systems

Abstract: A new non-isolated high-voltage gain three-port converter for standalone photovoltaic systems is proposed. The magnetic element of this converter is only one coupled inductor. The primary winding of the coupled inductor is shared between battery charger circuit and main converter. Leakage inductance energy of the coupled inductor is either transferred to battery or is regenerated via the passive-clamp circuit. Using switched capacitor and voltage lift techniques, the voltage gain is significantly increased for both low-voltage ports. Single magnetic element, high-voltage gain with reasonable duty cycle, low-voltage stress on the switches, low winding turn ratio of coupled inductor and high efficiency are the merits of this converter. The operation principles and the steady-state analysis are described for the three modes of: single-input single-output, single-input dual-output and dual-input single-output. To verify the theoretical analysis, a laboratory prototype with 28 V input, 48 V battery voltage and 380 V output voltage is implemented and tested.

GaN-based complementary metal–oxide–semiconductor inverter with normally off Pch and Nch MOSFETs fabricated using polarisation-induced holes and electron channels

Abstract: Gallium nitride (GaN)-based P-channel (Pch) and N-channel (Nch) metal-oxide-semiconductor field-effect transistors (MOSFETs) with normally off operations were realised. Both Pch and Nch MOSFETs were monolithically fabricated in a polarisation-junction platform wafer. The platform wafer was constructed with a GaN/aluminium GaN/GaN double heterostructure, which has both two-dimensional hole gas (2DHG) and 2D electron gas (2DEG). The drain currents of Pch and Nch MOSFETs flow through 2DHG and 2DEG, respectively. The threshold gate voltages of the fabricated Pch and Nch MOSFETs were -2.7 and 6.7 V, respectively. It was shown that the threshold voltage and the on-state resistance of the Pch MOSFET can be controlled by adjusting the 2DEG potential. Furthermore, using Pch and Nch MOSFETs, complementary MOS inverter operation was demonstrated.

Monolithically integrated power circuits in high-voltage GaN-on-Si heterojunction technology

Abstract: This study presents monolithically integrated power circuits, fabricated in a high-voltage GaN-on-Si heterojunction technology. Different advanced concepts are presented and compared with solutions found in the literature. High switching transition slew rates are demonstrated by means of a monolithic power circuit with integrated gate driver. A highly linear temperature sensor is integrated in a GaN-high-electron-mobility transistor (HEMT) power device for the 600 V class and on-state resistance of 53 mΩ. An area-efficient HEMT structure with integrated freewheeling diodes is presented. This structure is applied in a monolithic multilevel converter chip, as well as in a 600 V class half-bridge chip. The multilevel chip is integrated by an advanced printed circuit board embedding technology and tested in inverter operation with a mains voltage output of 120 V RMS . The performance of the half-bridge is demonstrated in a synchronous buck converter operation from 400 to 200 V and with a switching frequency of 3 MHz.

Design of an advanced PLL for accurate phase angle extraction under grid voltage HIHs and DC offset

Abstract: The presence of direct current (DC) offset and harmonics–interharmonics (HIHs) in grid voltage input signal of phase-locked loop (PLL) results in inaccurate controller response. The inaccuracies are due to the low- and high-frequency oscillations that appear in the PLL estimated phase, amplitude and frequency. The suppression of fundamental frequency oscillations caused by DC offset (DO) in the input voltage signal must be carried out without compromising the dynamic response of the system. The use of low-pass filters, for example, results in undesirable, slow response. This study proposes an accurate and fast decoupling of fundamental frequency oscillations using a mathematic-cancellation decoupling cell. Higher-frequency oscillations generated by HIHs are eliminated by a different harmonic compensation network (HCN) that is also proposed in this study. The performance of conventional techniques is limited because they eliminate only specifically selected harmonics. The proposed PLL, however, eliminates any number of HIHs present in the grid with the least computational complexity and without any prior knowledge. Furthermore, its advanced features provide accurate synchronisation under any abnormal grid condition at the lowest computational complexity when compared with the existing state-of-the-art PLLs. The advanced performance of the proposed HIHDO-PLL is verified through simulation and experimental results.