Integration 

About: Integration is an academic journal published by Nomos. The journal publishes majorly in the area(s): Computer science & CMOS. It has an ISSN identifier of 0720-5120. Over the lifetime, 239 publications have been published receiving 274 citations. The journal is also known as: Integration (Baden-Baden).

A novel dual mode configurable and tunable high-gain, high-efficient CMOS power amplifier for 5G applications

Abstract: This paper presents a novel dual mode configurable and tunable power amplifier (PA) that achieves a wide-bandwidth and high gain across a operational frequency spectrum of 20 to 30 GHz. The proposed PA used two-stage tunable PA which can be configured as a tunable synchronous mode or tunable stagger-tuned mode PA. PA is implemented by using a distortion-free varactor at the input and output tank of PA. The designed PA includes a high-Q CMOS active inductor (CAI) which provides a widely tunable output matching network. The resistive feedback is used for self-biasing in the designed PA which helps to enhance the linearity, stability of common source (CS) amplifier. The inter-stage impedance matching network consists of shunt and series resonance circuits are employed for maximum power added efficiency (PAE). Furthermore, the capacitive coupled reuse technique is implemented in each stage between the cascaded transistor to reduce the power consumption. A proposed PA is designed using a 65 nm CMOS technology. A measured power gain at the synchronous operation of PA is 28.4 ±0.5 dB with 1.31 GHz bandwidth while power gain at staggered operation is 22.1 ±0.5 dB with 3.71 GHz bandwidth. The measured saturated power (Psat) is 14.21 dBm and the noise figure (NF) is 5.2 dB. The group delay (GD) variation for staggered operation is 57 ±10 ps from 20-30 GHz. A proposed PA exhibits good linearity (IIP3) of 14.5 dBm and PAE is 47.5 % at 24 GHz. The power consumption of a designed PA is 48.56 mW with a supply voltage of 1.2 V.

A new adaptive selection strategy for reducing latency in networks on chip

Abstract: Networks on chips (NoCs) are a concept inspired by computer networks for constructing multiprocessor systems that can handle communication across processing cores. One of the most critical applications of NOC is efficient nonstop routing. Different routes exist in these networks to get from one node to another; thus, a function that can assist in determining the optimum route to the target should be available. This paper uses a new hybrid method called Scored Regional congestion aware and DICA (ScRD) to select a better output channel and increase NOC performance. After applying the ScRD algorithm, the traffic packets are examined by an analyzer, which determines if the NoC traffic is local or non-local based on the number of hops. Therefore, if the traffic is local, a scoring mechanism will select a better output channel; otherwise, the best output channel will be chosen using DICA or RCA selection functions, depending on the system state and the introduced parameter. Finally, Nirgam simulation was used to test the suggested method under various traffic conditions and selection criteria. The simulation results demonstrated that the strategy outperformed delay time, throughput, and energy consumption alternatives. It reduced packet delay by 27.10% and increased throughput by 10%. When these two factors were considered, energy consumption dropped by 6.86%. Also, the synthesis results showed that the hardware cost of the proposed approach is 1.2% lower than the two basic methods.

Dynamics analysis, FPGA realization and image encryption application of a 5D memristive exponential hyperchaotic system

Abstract: The exponential function is one of the basic elementary functions, which plays an irreplaceable role in mathematics and is also widely used in practical activities such as life and production. In this paper, a new 5D memristive exponential hyperchaotic system (MEHS) is proposed, which includes an exponential term and a nonlinear flux-controlled memristive model. Fundamental dynamics characteristics of the system are analyzed using phase diagram, Lyapunov exponential spectrum and bifurcation diagram. When appropriate parameter sets are selected, the MEHS exhibits a rich set of dynamic behaviors, including the coexistence of periodic and periodic attractors, periodic and chaotic attractors, chaotic and hyperchaotic attractors. In addition, the Field Programmable Gate Array (FPGA) is used to realize the 5D MEHS, and the experimental results are consistent with the numerical simulation results on MATLAB. Finally, an image encryption application based on the 5D MEHS is presented. The security analysis shows the feasibility and effectiveness of the image encryption algorithm.

High-performance hardware architecture of a robust block-cipher algorithm based on different chaotic maps and DNA sequence encoding

Abstract: Nowadays, secure digital data in store and transmission is an important issue. Cryptographic methods are widely used to provide optimal security for multimedia data. In this paper, a good performance implementation of a strong block-cipher system is proposed. This article's contribution is to develop a new method to block-cipher hardware system based on DNA biological properties and various 3D chaotic maps. In this scheme, the high-level security is achieved by chaotic sequences generated by a robust chaos-based PRNG based on the Lorenz, Chua, Rossler, and Chen chaotic maps. The latter is used to generates high-quality keys that are applied for encryption. Thus, a high-security block cipher approach for encrypting and decrypting images has been developed. To increase the confusion process complexity, several biological operations, such as DNA-XOR, are added to the encryption process. Furthermore, a novel hardware architecture of the proposed block-cipher system is put forward. The latter achieves a low power consumption, good frequency of 192.813 MHz and high throughput of 24,576,153 Mbps built. The security analysis demonstrates that the cryptosystem provides effective security. The proposed PRNG validated successfully both the NIST SP 800–22 test suite and the U01-Test. Various tests are performed, such as statical tests, phase analysis and differential attacks applied to different images. A comparison of the proposed algorithm with several newly developed encryption algorithms demonstrates that our system generates good results.

Agile-AES: Implementation of configurable AES primitive with agile design approach

Abstract: In the data-centric era, interconnected devices must be able to communicate efficiently and securely with their hosts even over untrusted networks. This led to the adoption of several end-to-end security protocols that employ various efficient and elegant encryption algorithms, such as Advanced Encryption Standard (AES), often implemented with hardware modules since there is usually no good solution to install security software on the device itself. State-of-the-art AES hardware implementations typically focus on optimizing a single metric, e.g. throughput or area, and are tedious to adapt to a wider set of design constraints. Applying an agile approach to hardware development is increasingly important, and this is especially critical for hardware security primitives that need to be consumed in various systems. In this work, we develop Agile-AES, an open-source, flexible, parameterizable, hardware implementation of AES, combining many best-known practices. The agile and feature-rich implementation was based on the Chisel framework, through which flexibility is instrumented to support various key length, topology, mode of operation, local memory type, S-box fabric, side-channel attack defense techniques, and interfaces. Despite covering a larger design space, our proposed implementation has 50% fewer lines of code compared to existing Verilog versions — a crucial advantage in terms of maintainability and development productivity. To evaluate the QoR out of this implementation approach, we pick representative configurations and evaluate utilization, power and throughput on both entry level and server-grade FPGAs and compare against the Verilog and HLS counterpart implementations. It shows very comparable results to the Verilog implementation and better QoR compared to the HLS-based implementation.