# Showing papers in "International Journal of Circuit Theory and Applications in 1987"

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TL;DR: In this article, a substitution method for calculating the steady state response of nonlinear circuits such as forced circuits driven by multi-frequency component signals, forced oscillators, and coupled oscillators is presented.

Abstract: In this paper, we present an efficient algorithm for calculating the steady-state response of nonlinear circuits such as forced circuits driven by multi-frequency-component signals, forced oscillators, and coupled oscillators. We call the technique a substitution method because the variation at each step is calculated by solving an associated time-invariant sensitivity circuit at each frequency component of the residual error, whose circuit is derived from a relaxation method. the algorithm is very simple and efficient, and it can be applied to a wide variety of nonlinear circuits.

48 citations

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TL;DR: In this paper, the authors apply Poincare half-maps to the three-region piecewise-linear continuous dynamical system associated with Chua's circuit and derive transfer and return maps, induced by the trajectories inside the intermediate region in state space.

Abstract: Techniques formerly developed in the theory of Poincare half-maps are modified and applied to the three-region piecewise-linear continuous dynamical system associated with Chua's circuit. Both transfer and return maps, induced by the trajectories inside the intermediate region in state space, are formulated as implicit equations. the boundaries of the domains of these maps are determined explicitly, using the method for calculating the initial points of touching trajectories subject to appropriate switching dynamics. A charting of the canonical parameter space of the dynamics that acts on the intermediate region is indicated. Among other things, this chart reveals the existence of new types of chaotic attractors different from the double scroll and Rossler attractors previously discovered from Chua's circuit.

24 citations

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TL;DR: The notion of a generalized minor of a vector space is introduced and made systematic use of, showing how to make the equations of a given network appear to be the ‘bordered version’ of the equation of some other specified network.

Abstract: This paper deals with effects of modifications of network structure that may be studied without reference to the type of devices present in the network. We introduce and make systematic use of the notion of a generalized minor of a vector space. This operation generalizes the usual short and open circuit operations for a graph. Using the generalized minor operation we show how to make the equations of a given network appear to be the ‘bordered version’ of the equations of some other specified network. We also consider the decomposition of a network into several ‘multiports’ and a ‘port connection diagram’, and study the properties of a minimal decomposition (with port connection diagram having a minimum number of edges). In each case we present efficient algorithms wherever appropriate. Although the paper makes use of ideas from elementary matroid theory it is entirely self-contained and requires no more than the knowledge of elementary linear algebra from the reader.

19 citations

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14 citations

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TL;DR: In this article, the problem of 3-ports consisting of the parallel connection, at port 1, of a lowpass ladder of degree n having all its attenuation poles at infinity, with a high passagation poles at DC, the purpose of the design being to achieve a Butterworth (maximally flat) behaviour, simultaneously in the lowpass direction (1-2) at DC and in the highpass direction(1-3) at infinity.

Abstract: The paper deals with the design of 3-ports consisting of the parallel connection, at port 1, of a lowpass ladder of degree n having all its attenuation poles at infinity, with a highpass ladder of degree m having all its attenuation poles at DC, the purpose of the design being to achieve a Butterworth (maximally flat) behaviour, simultaneously in the lowpass direction (1-2) at DC and in the highpass direction (1-3) at infinity. Norton1 has solved the case m = n for constant impedance filter pairs. the much more difficult case where one of the above restrictions is not met is discussed in general terms and some new results are obtained. Although the problem is far from being completely solved, useful explicit design relations are established for a few filter pairs of low degrees.

13 citations

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TL;DR: A necessary and sufficient condition for pseudo-circuit generation is presented for the use of the pseudo-Circuit in the self-test algorithm, and a testability condition is presented with examples to determine the diagnosability of a designed circuit.

Abstract: With the rapidly increasing complexity of circuits and systems, the ability adequately to design a diagnosable circuit or system is a prime requisite for rapid fault location. In the present paper, a necessary and sufficient condition for pseudo-circuit generation is presented for the use of the pseudo-circuit in the self-test algorithm. to determine the diagnosability of a designed circuit, a testability condition is presented with examples. the unique feature of these conditions is that they depend only on the topological structure of a given circuit, not on the component values; therefore, these conditions can be implemented in both linear and non-linear circuits or systems. With the aid of a computer, the test points may be generated automatically by the proposed algorithm. Based on the proposed algorithm, the design of testability can be established.

13 citations

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11 citations

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TL;DR: In this article, a technique for implementing fully integrated continuous time non-switched capacitor filter has been proposed, which uses a balanced structure using op-amps, capacitors and MOS transistors operated in the non-saturated region as voltage-controlled resistors.

Abstract: A technique for implementing fully integrated continuous time non-switched capacitor filter has been recently reported in the literature. the technique uses a balanced structure using op-amps, capacitors and MOS transistors operated in the non-saturated region as voltage-controlled resistors. In order to eliminate the non-linearity of the MOS transistors over an extended voltage range the current techniques use fully balanced circuits. This paper provides a simple technique for cancellation of non-linearities, thereby reducing the number of elements, and proposes several simple circuits. the technique is then used in the design of high-order filters.

11 citations

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TL;DR: In this article, the authors rigorize and systematize the analysis of weakly non-linear oscillator circuits via the method of averaging and give a novel way of simplifying the calculation of averages when we have a potential function representation.

Abstract: The method of averaging has been used for years to prove the existence of oscillations in non-linear circuits. In the past the application of averaging has tended to be ad hoc rather than systematic. In addition the validity of the method was not well established. the purpose of this paper is to rigorize and systematize the analysis of weakly non-linear oscillator circuits via the method of averaging. In particular this paper will put on a rigorous foundation the work of Kuramitsu et al.1-3 on the ‘averaged potential’ and the work of T. Endo and others on the oscillatory modes of coupled oscillator circuits. Furthermore we give a novel way of simplifying the calculation of averages when we have a potential function representation.

9 citations

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9 citations

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TL;DR: In this article, simple and rigorous proofs of results due to various authors on tests for the property that a multivariable polynomial be devoid of zeros in the closed unit polydisc are given.

Abstract: Simple and rigorous proofs of results due to various authors on tests for the property that a multivariable polynomial be devoid of zeros in the closed unit polydisc are given. the proof technique rests largely on a correct and complete formulation of the fact that the zeros of a polynomial are continuous functions of its coefficients. It is shown that almost all other related results can be derived in this manner.

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TL;DR: An algorithm for multiple fault diagnosis of analogue-digital circuits by sequentially partitioning the devices into those ‘assumed good’ and those ’under test’ is developed and a generic condition for diagnosability in terms of the circuit topology is given.

Abstract: This paper develops an algorithm for multiple fault diagnosis of analogue-digital circuits. By sequentially partitioning the devices into those ‘assumed good’ and those ‘under test’, it is possible to develop a set of fault diagnosis equations which account for the special nature of digital components. A modified Newton-Raphson solution is then described which incorporates a digital state hypothesis testing scheme in the solution of the fault diagnosis equations for each partition. After solving for the input-output characteristics of the devices under test, a Boolean decision algorithm is used to analyse the test results of each partition and thus sequentially arrive at the set of faulty elements. A generic condition for diagnosability in terms of the circuit topology is given. Two examples are included to illustrate the technique.

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TL;DR: In this paper, a systematic approach to the design of stray-insensitive switched-capacitor (SC) circuits from active-RC or RLC prototypes employing a parasitic insensitive SC differential voltage-controlled current-source as a basic building block is attempted.

Abstract: A systematic approach to the design of stray-insensitive switched-capacitor (SC) circuits from active-RC or RLC prototypes employing a parasitic insensitive SC differential voltage-controlled current-source as a basic building block is attempted. Procedures for transforming active-RC and RLC circuits into stray-insensitive SC circuits are formulated and illustrated with typical examples. Restrictions on the pole-frequency and pole-Q of the SC biquad are derived so that it closely emulates the frequency response of the original active-RC biquad. the SC biquad and the ladder filter derived by the proposed procedures were simulated with discrete components and tested in the laboratory. Test results agree closely with the theoretical predictions.

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TL;DR: In this paper, necessary and sufficient conditions are given for resistive circuits containing both monotone-increasing nonlinear resistors and non linear resistors, in addition to controlled sources and op-amps, to have a unique solution for all circuit parameters.

Abstract: Necessary and sufficient conditions are given for resistive circuits containing both monotone-increasing non-linear resistors and monotone-decreasing non-linear resistors (called negative non-linear resistors), in addition to controlled sources and op-amps, to have a unique solution for all circuit parameters Several theorems are given for various classes of circuits containing different combinations of active circuit elements the theorems are couched mostly in topological terms and can therefore be checked by inspection

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TL;DR: In this paper, a general procedure is presented to realize a two-port impedance matrix by a generalized transformerless LC ladder network including the classical LC ladder structure as a special case, which consists of repeatedly applying a subnetwork removal cycle for which six different cases are to be considered.

Abstract: A general procedure is presented to realize a two-port impedance matrix by a generalized transformerless LC ladder network including the classical LC ladder structure as a special case. the realization process consists of repeatedly applying a subnetwork removal cycle for which six different cases are to be considered. the feasibility of the various subnetwork removals is characterized by formulating necessary and sufficient conditions on the impedance matrix. the application of the procedure is illustrated by a numerical example.

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TL;DR: In this paper, the authors describe a logarithmic A/D converter (LADC) working with the charge redistribution principle, which uses a serial and a parallel capacitive attenuator and is suitable for manufacturing on a single chip.

Abstract: The present paper describes a logarithmic A/D converter (LADC) working with the charge redistribution principle. the LADC uses a serial and a parallel capacitive attenuator and is suitable for manufacturing on a single chip. Formulae for the values of the capacitors are given in terms of the base of logarithm used. This LADC uses logarithmically spaced voltage comparison levels and therefore eliminates the use of logarithmic analogue signal conditioning circuits.

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TL;DR: This research has given a concrete example of how systems, filter, network, circuit and CAD experience can be effectively combined into a VLSI design.

Abstract: The silicon implementation of a transmultiplexer system, from the high level description up to the floor-plan, is presented. the described realization allows to integrate an entire 12-channel TDM-FDM transmultiplexer system on a silicon area of less than 80 mm2 in a 5 μm single-metal race-free dynamic CMOS technology, making use of an available bit-serial standard-cell library. At the architectural level, a hardware-sharing transformation combined with a number of optimizations for the coefficient quantization and the choice of the data word-length, have allowed for a global area-reduction of almost 50 per cent.
First a mainly manual approach has been investigated, where the hierarchical decomposition has been exploited to perform global and local optimizations in terms of the hardware. Later on, based on this experience, it has been employed as a major test vehicle for the CAD tool-box of the bit-serial silicon compiler1,2 which has been developed during the pilot phase of an ESPRIT research project at our laboratory. Extensive use has been made of programs for filter synthesis, optimization, bit-serial mapping, delay management and standard-cell placement and routing. the results obtained with both design strategies are compared.
This research has given a concrete example of how systems, filter, network, circuit and CAD experience can be effectively combined into a VLSI design.

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TL;DR: In this article, a simple circuit model for the MOS (metal-oxide-semiconductor) structure is presented, consisting of three elements, namely, a linear capacitor, a non-linear capacitor and a C-dynamic element.

Abstract: A new simple circuit model for the MOS (metal-oxide-semiconductor) structure is presented. the model consists of three elements, namely, a linear capacitor, a non-linear capacitor and a C-dynamic element. Each component bears a simple relationship to the physical operating mechanism inside the MOS structure. the model can be used for simulating arbitrary MOS structure circuits under all operating conditions. In particular, it is capable of reproducing the structure's frequency-dependent small-signal characteristics. the model is also shown to exhibit many important and interesting dynamic behaviours under forward, reverse and sinusoidal operating modes.
The model is based mainly upon the device's physical operating principles. But perhaps the most significant implication of this model is that it is the first ever to use a dynamic element to model the MOS structure from a physical approach.

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TL;DR: In this article, the authors identify the topological entities underlying the construction of a complete (not reduced) network model, and show that if a complete network model is to be constructed, the relations among the voltages and those among the currents of the network elements must be written choosing maximal independent sets of loops and cut-sets of Ga.

Abstract: The aim of this paper is to identify the topological entities underlying the construction of a complete (not reduced) network model. Consider an active network as a pair of physically different structures, i.e. a ‘dead network’ and an ‘excitation’. First, we define the general structure of the excitation which can be applied to a dead network; then the graphs Ga and G of the active and dead networks, respectively, are introduced. It is shown that, if a complete network model is to be constructed, the topological relations among the voltages and those among the currents of the network elements must be written choosing maximal independent sets of loops and cut-sets of Ga. It is successively pointed out that the graph G can be obtained from Ga by means of a reduction operation, and the topological entities of G corresponding to the loops and to the cut-sets of Ga are singled out. It has been found that a complete model of an electric network implies the use of four topological entities defined on the set of G-edges, i.e. the closed path, the open path, the cut-set and the pseudo-cut, together with two topological entities defined on a maximal set of independent vertex couples of G, i.e. the ‘junction pair’ extreme of an open path and the ‘family of independent node couples’ split by a cut-set.
Furthermore the different reference frames and the relative topological matrix transformations which allow a complete model of the network to be built up are singled out and discussed.

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ETH Zurich

^{1}TL;DR: In this paper, a simple and elegant method of hand analysis for basic SC circuits using a combination of transmission and transfer matrix parameters is presented, once the considerable simplifications due to the presence of opamps are taken into account.

Abstract: Four-port matrix theory is the foundation for various useful methods of analysing switched-capacitor networks. Thus, for example, signal-flow graph techniques, the link-two-port concept, and nodal computer analysis methods are based on either the four-port transmission or admittance matrix. In the derivation of these analysis techniques transmission, reverse-transmission, and transfer matrices are often used, but the relationship between them has not yet been clearly formulated for four-port networks. In this paper an attempt at formulation and clarification is made. Furthermore, it is shown that, once the considerable simplifications due to the presence of opamps are taken into account, a simple and elegant method of hand analysis for basic SC circuits using a combination of transmission and transfer matrix parameters results.

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TL;DR: In this paper, the problem of determining whether the non-unique solvability depends on the particular values of the components or on their topological interconnections is studied for linear networks with arbitrary, time-invariant, and time-varying n-ports.

Abstract: The problem of knowing whether the non-unique solvability depends on the particular values of the components or on their topological interconnections is studied for linear networks with arbitrary, time-invariant as well as time-varying n-ports.
Within every network, the topological notions of its sockets and of their independence are introduced. Networks with independent sockets are shown-at least when there are no relations among the non-zero coefficients, nor repetitions of the same coefficient are allowed, i.e. under suitable generality assumptions-to be uniquely solvable. Networks with dependent sockets are shown to be never uniquely solvable.
Polynomially bounded algorithms, requiring only integer arithmetic, to test independence are available. When independence fails, a topological configuration of components which shows fewer topologically independent variables than equations, is proved to exist.

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TL;DR: In this paper, it was proved that an n-port composed of ideal transformers, gyrators and ideal rectifiers has a unique solution for the port variables when it is excited by generators in series with strictly positive resistances.

Abstract: It is proved that an n-port composed of ideal transformers, gyrators and ideal rectifiers has a unique solution for the port variables when it is excited by generators in series with strictly positive resistances. the multiplicity of solutions for the internal variables is discussed. Connections are established with the theory of linear inequalities and with the coloured branch theorem of graph theory.

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TL;DR: In this paper, a method is presented to realize a class of 2D IIR digital filters by extension of 2-D FIR structures through feedback paths, while most features of the initial FIR structures remain unchanged (e.g. parallelism, number of delay elements).

Abstract: A method is presented to realize a class of 2-D IIR digital filters by extension of 2-D FIR structures through feedback paths. Most features of the initial FIR structures remain unchanged (e.g. parallelism, number of delay elements). the approach described is applied to a class of 2-D FIR filter structures owning several advantages. the method is generalized to semicausal filters.