Showing papers in "International Journal of Circuit Theory and Applications in 2014"
TL;DR: A four-dimensional system modified from a three-dimensional chaotic circuit by adding a memristor is studied rigorously in detail by the virtue of the topological horseshoe theory and the computer-assisted approach of a Poincare map to verify the existence of hyperchaos and reveal its mechanism.
Abstract: We study a four-dimensional system modified from a three-dimensional chaotic circuit by adding a memristor, which is a new fundamental electronic element with promising applications. Although the system has a line of infinitely many equilibria, our studies show that when the strength of the memristor increases, it can exhibit rich interesting dynamics, such as hyperchaos, long period-1 orbits, transient hyperchaos, as well as non-attractive behaviors frequently interrupting hyperchaos. To verify the existence of hyperchaos and reveal its mechanism, a horseshoe with two-directional expansion is studied rigorously in detail by the virtue of the topological horseshoe theory and the computer-assisted approach of a Poincare map. At last, the system is implemented with an electronic circuit for experimental verification. Copyright © 2013 John Wiley & Sons, Ltd.
107 citations
TL;DR: The introduced transform relationships simplify the synthesis of any NGD circuits from simple elementary low-pass NGD topologies, and the possibility of the ultra-wideband pulse signals propagating in time-advance is verified.
Abstract: This paper deals with the similitude between the behaviours of linear filter gain and negative group delay NGD function. The transposition method of low-pass/high-pass, low-pass/band-pass and low-pass/band-stop NGD circuits is established. To the best of the author knowledge, it acts as the first paper devoted on the NGD function generalized theory. The introduced transform relationships simplify the synthesis of any NGD circuits from simple elementary low-pass NGD topologies. Families of innovative NGD topologies are identified. To verify the relevance of the concept proposed, frequency- and time-domain analysis results from realistic proofs of concept demonstrating the feasibility of developed NGD transforms were performed. Thanks to the NGD phenomenon, the possibility of the ultra-wideband pulse signals propagating in time-advance is verified. Finally, potential applications of NGD circuits are discussed. Copyright © 2013 John Wiley & Sons, Ltd.
82 citations
TL;DR: Experimental results demonstrate that well-designed subthreshold op-amps are a very attractive solution to implement sub-1-V energy-efficient applications for modern portable electronic systems.
Abstract: This work focuses on the subthreshold design of ultra low-voltage low-power operational amplifiers. A well-defined procedure for the systematic design of subthreshold operational amplifiers op-amps is introduced. The design of a 0.5-V two-stage Miller-compensated amplifier fabricated with a 0.18-µm complementary metal-oxide-semiconductor process is presented. The op-amp operates with all transistors in subthreshold region and achieves a DC gain of 70dB and a gain-bandwidth product of 18kHz, dissipating just 75nW. The active area of the chip is i¾?0.057mm2. Experimental results demonstrate that well-designed subthreshold op-amps are a very attractive solution to implement sub-1-V energy-efficient applications for modern portable electronic systems. A comparative analysis with low-voltage, low-power op-amp designs available in the literature highlights that subthreshold op-amps designed according to the proposed design procedure achieve a better trade-off among speed, power, and load capacitance. Copyright © 2013 John Wiley & Sons, Ltd.
79 citations
TL;DR: This paper presents for the first time a family of memristor-based reactance-less oscillators MRLOs that require no reactive components, that is, inductors or capacitors, rather, the 'resistance storage' property of Memristor is exploited to generate the oscillation.
Abstract: In this paper, we present for the first time a family of memristor-based reactance-less oscillators MRLOs. The proposed oscillators require no reactive components, that is, inductors or capacitors, rather, the 'resistance storage' property of memristor is exploited to generate the oscillation. Different types of MRLO family are presented, and for each type, closed form expressions are derived for the oscillation condition, oscillation frequency, and range of oscillation. Derived equations are further verified using transient circuit simulations. A comparison between different MRLO types is also discussed. In addition, detailed fabrication steps of a memristor device and experimental results for the first MRLO physical realization are presented. Copyright © 2013 John Wiley & Sons, Ltd.
74 citations
TL;DR: A memristor-based voltage-controlled reactance-less oscillator VCO is introduced as an application for the proposed circuits which is nano-size and more efficient compared to the conventional VCOs.
Abstract: This paper introduces two voltage-controlled memristor-based reactance-less oscillators with analytical and circuit simulations. Two different topologies which are R-M and M-R are discussed as a function of the reference voltage where the generalized formulas of the oscillation frequency and conditions for oscillation for each topology are derived. The effect of the reference voltage on the circuit performance is studied and validated through different examples using PSpice simulations. A memristor-based voltage-controlled oscillator VCO is introduced as an application for the proposed circuits which is nano-size and more efficient compared to the conventional VCOs. Copyright © 2013 John Wiley & Sons, Ltd.
49 citations
TL;DR: An efficient technique for designing high-performance logic circuits operating in sub-threshold region using a simple gate-level body biasing circuit to change dynamically the threshold voltage of transistors on the basis of the gate status.
Abstract: An efficient technique for designing high-performance logic circuits operating in sub-threshold region is proposed. A simple gate-level body biasing circuit is exploited to change dynamically the threshold voltage of transistors on the basis of the gate status. Such an auxiliary circuit prepares the logic gate for fast switching while maintaining energy efficiency.
48 citations
TL;DR: A closed-form iterative procedure for synthesizing quasi-arbitrary phase responses with cascaded microwave C-section all-pass phasers is presented and is validated by both full-wave analysis and measured multilayer prototypes.
Abstract: A closed-form iterative procedure for synthesizing quasi-arbitrary phase responses with cascaded microwave C-section all-pass phasers is presented. The synthesis consists in mapping the transmission poles of the cascaded C-section structure onto the transmission poles of the specified transfer function, where the latter poles are computed using a closed-form polynomial generation method. The real and complex transmission poles of the specified transfer function are realized using C-sections of different lengths and different couplings coefficients. The proposved synthesis is validated by both full-wave analysis and measured multilayer prototypes. Copyright © 2013 John Wiley & Sons, Ltd.
41 citations
TL;DR: The workability of the proposed simulated inductance is demonstrated through two applications namely, a band pass filter and an oscillator, and results agree well with the theoretical values.
Abstract: In this paper, a method to realize a grounded inductor using single operational transresistance amplifier is presented. The simulated inductance value can be controlled independent of realizability condition. The non-ideality analysis of the circuit is also given. The workability of the proposed simulated inductance is demonstrated through two applications namely, a band pass filter and an oscillator. PSPICE simulation and experimental results agree well with the theoretical values. Copyright © 2013 John Wiley & Sons, Ltd.
38 citations
TL;DR: In this article, a multi-scroll chaotic system from the improved Chua's system is proposed, and non-linear dynamics are analyzed including phase-space trajectories, bifurcation diagrams, Poincare maps and so on.
Abstract: In this paper, a multi-scroll chaotic system from the improved Chua's system is proposed. Moreover, non-linear dynamics are analyzed including phase-space trajectories, bifurcation diagrams, Poincare maps and so on. The most important thing is that we discovered phase-space trajectories, bifurcation diagrams and Poincare maps are unified and closely related, which can describe different aspects of the multi-scroll chaotic system. Furthermore, the corresponding improved module-based circuits are designed for realizing two to four-scroll chaotic attractors, and the experimental results are also obtained, which are consistent with the numerical simulations. Copyright © 2012 John Wiley & Sons, Ltd.
37 citations
TL;DR: This tutorial distills the salient phase-noise analysis concepts and key equations developed over the last 75years relevant to integrated circuit oscillators.
Abstract: This tutorial distills the salient phase-noise analysis concepts and key equations developed over the last 75years relevant to integrated circuit oscillators Oscillator phase and amplitude fluctuations have been studied since at least 1938 when Berstein solved the Fokker-Planck equations for the phase/amplitude distributions of a resonant oscillator
33 citations
TL;DR: A modification to the amplitude clipping method is suggested to produce a novel clipping technique called the side information supported amplitude clipping (SI‐SAC) method, which involves sending certain bits of extra information so that the receiver can recover all of the clipped data.
Abstract: OFDM is an important modulation technique currently in development in the field of communications systems. OFDM signals can combat multipath propagation and fading channels and can support large data rates. However, OFDM systems are multicarrier systems and experience problems due to the required summation of sinusoids when the in-phase subcarriers are combined, which produces high power peaks. The large power envelope fluctuations that occur at the output cause in-band and out-of-band distortions that result in degraded BER performance. The literature contains many qualified approaches to resolving the peak-to-average power ratio problem, including selected mapping, partial transmit sequence, and amplitude clipping techniques. The simplest technique is the amplitude clipping technique, and the selected mapping and partial transmit sequence techniques are excessively complicated for real-time implementation. In this paper, we suggest a modification to the amplitude clipping method to produce a novel clipping technique called the side information supported amplitude clipping SI-SAC method. The SI-SAC technique involves sending certain bits of extra information so that the receiver can recover all of the clipped data. The SI-SAC technique does not add computational complexity to the system, and simulation results show that the proposed method is superior to the conventional method. The peak-to-average power ratio was reduced by i¾?2.5dB, and the magnitude of the mean squared error vector is the same as that of the original signal that is not clipped. In contrast, the conventional amplitude clipping method produces a mean squared error vector with a large magnitude. Copyright © 2012 John Wiley & Sons, Ltd.
TL;DR: The voltage temperature parameter VTP is introduced, which gives a direct measure of the overall percentage variation of the reference voltage on the typical 2D domain of supply voltage and temperature, and is presented as a new figure of merit.
Abstract: A voltage reference consisting of only two nMOS transistors with different threshold voltages is presented. Measurements performed on 23 samples from a single batch show a mean reference voltage of 275.4mV. The subthreshold conduction and the low number of transistors enable to achieve a mean power consumption of only 40pW. The minimum supply voltage is 0.45V, which coincides with the lowest value reported so far. The mean TC in the temperature range from 0 to 120i¾?C is 105.4ppm/i¾?C, while the mean line sensitivity is 0.46%/V in the supply voltage range 0.45-1.8V. The occupied area is 0.018mm2. The power supply rejection rate without any filtering capacitor is -48dB at 20Hz and -29.2dB at 10kHz. Thanks to large area transistors and to a careful layout, the coefficient of variation of the reference voltage is only 0.62%. We introduce as a new figure of merit, the voltage temperature parameter VTP, which gives a direct measure of the overall percentage variation of the reference voltage on the typical 2D domain of supply voltage and temperature. For the proposed circuit, the average VTP is 1.70% with a standard deviation of 0.21%. In order to investigate the effect of transistor area on process variability, a 4X replica of the proposed configuration has been fabricated and tested as well. Except for LS, the 4X replica doesn't exhibit any appreciable improvement with respect to the basic voltage reference. Copyright © 2013 John Wiley & Sons, Ltd.
TL;DR: The presented analysis of the frequency divider dynamics enables us to establish that stable locked oscillations occur on the whole locking range predicted by the well-known Adler's equation and that these are possible also beyond that range.
Abstract: A method for analyzing the nonlinear dynamics of the injection-locked frequency dividers in synchronized operation mode is presented, including the stability analysis of locked states. We use a specific divide-by-two circuit, namely a differential LC CMOS divider with a complementary topology, as a guideline for presentation, showing that the sizing of the devices significantly affects the synchronization mechanism of the divider, which exhibits a very rich dynamical behavior. We provide closed-form expressions to determine the amplitude and the phase in the locked state, as well as the locking range, leading to accurate results, which are validated by numerical simulations. The presented analysis of the frequency divider dynamics enables us to establish that stable locked oscillations occur on the whole locking range predicted by the well-known Adler's equation and that these are possible also beyond that range. Copyright © 2013 John Wiley & Sons, Ltd.
TL;DR: A new topology for realizing arbitrary nth-order current transfer function (TF), consisting of only plus-type second-generation current conveyors (CCII+s), is suggested, which has low-input and high-output impedances and can provide gain at its outputs.
Abstract: In this paper, a new topology for realizing arbitrary nth-order current transfer function (TF), consisting of only plus-type second-generation current conveyors (CCII+s), is suggested. The proposed TF simulator employs only grounded capacitors and is free from the passive element matching requirements. The developed TF simulator can be constructed directly with commercially available active components such as AD844s. It has low-input and high-output impedances, a feature which makes it fully cascadable with other current-mode topologies. Moreover, the proposed simulator can provide gain at its outputs. Simulation and experimental test results for various filter examples are included to confirm the claimed theory. Copyright © 2012 John Wiley & Sons, Ltd.
TL;DR: This paper studies an IBC and demonstrates the first instability through a Neimark-Sacker bifurcation, resulting in a torus, and reveals that the torus has a rather strange form as the complex Floquet multipliers that became unstable have a real value close to -1.
Abstract: Interleaved boost converters IBCs are used when energy conversion is required at high current levels. Such converter systems may undergo various nonlinear phenomena which can affect their performance adversely. In this paper, we study an IBC and demonstrate the first instability through a Neimark-Sacker bifurcation, resulting in a torus. An analysis based on the calculation of the monodromy matrix reveals that the torus has a rather strange form as the complex Floquet multipliers that became unstable have a real value close to -1. We show that further variation in a parameter can result in novel nonlinear phenomena where the torus itself folds and grazes a switching manifold, resulting in a 'wobbling' of the closed loop that represents the torus in discrete time. Numerical and analytical results validate our work. Copyright © 2013 John Wiley & Sons, Ltd.
TL;DR: Ant colony optimization (ACO) algorithm is presented, as a tool to find transistor sizes in digital circuits, and results show that, ACO performs better than GA, for all the four circuits, in finding optimized transistor sizes.
Abstract: In this paper, ant colony optimization ACO algorithm is presented, as a tool to find transistor sizes in digital circuits. Performance of ACO has been tested on four digital circuits, of different complexity, to find optimum balance between power and delay of circuits. Optimization problem has been set up by first, formulating an objective function, to be minimized, for each circuit and then finding the values of variables of circuits, using optimization algorithm. For the purpose of examining the results, circuits are optimized using genetic algorithm GA also. Results show that, ACO performs better than GA, for all the four circuits, in finding optimized transistor sizes. Copyright © 2012 John Wiley & Sons, Ltd.
TL;DR: A closed-loop gain/efficiency-enhanced bidirectional switched-capacitor converter BSCC is proposed by combining an adaptive-conversion-ratio ACR phase generator and pulse-width-modulation PWM controller for biddirectional step-up/down DC-DC conversion and regulation.
Abstract: A closed-loop gain/efficiency-enhanced bidirectional switched-capacitor converter BSCC is proposed by combining an adaptive-conversion-ratio ACR phase generator and pulse-width-modulation PWM controller for bidirectional step-up/down DC-DC conversion and regulation. For realizing gain-enhanced, the power part consists of one mc-stage cell and one nc-stage cell in cascade between low-voltage LV and high-voltage HV sides to boost HV voltage into mc×nc times voltage of LV source at most, or convert LV voltage into 1/mc×nc times voltage of HV source at most. For realizing efficiency-enhanced, the ACR idea with adapting stage number m,n is built in the phase generator to obtain a suitable step-up/down gain: m×n or 1/m×nm=1,2,',mc, n=1,2,',nc. Further, the output regulation and robustness to source/loading variation can be enhanced by PWM on the LV/HV sides. Some theoretical analysis and control design are included as: modeling, steady-state analysis, conversion ratio, efficiency, capacitance selection, and control design. Finally, the performance of this scheme is verified experimentally on a BSCC prototype, and all results are illustrated to show the efficacy of this scheme. Copyright © 2012 John Wiley & Sons, Ltd.
TL;DR: A low-power, low-noise logarithmic preamplifier for biopotential and neural recording application is presented, and an active filter as a DC cancellation filter has been included to its input in order to eliminate DC offsets, which are produced at the electrode-tissue interface.
Abstract: In this work, a low-power, low-noise logarithmic preamplifier for biopotential and neural recording application is presented. The amplifier is based on a linear limit logarithmic amplifier technique, and an active filter as a DC cancellation filter has been included to its input in order to eliminate DC offsets, which are produced at the electrode-tissue interface. This system has been simulated in a UMC standard 90-nm 1P9M CMOS process. Five dual gain stages are used to produce the required linear limit logarithmic amplifier. The dynamic range of the amplifier is measured to be 48 dB which covers the signals with amplitude from 20µV to 5 mV. The amplifier consumes 23.5µW from a 1.2-V power supply and has a maximum gain of 69.8 dB. The simulated input referred noise is 5.3µV over 0.1 Hz to 20 kHz. Copyright © 2012 John Wiley & Sons, Ltd.
TL;DR: The proposed MTJ-based non-volatile semidynamic flip-flop NVSDFF has a semid dynamic structure that ensures a fast D-Q delay and separates the sensing circuit from the D- Q signal path to reduce the sensing current without affecting the D -Q delay.
Abstract: The conventional magnetic tunneling junction MTJ-based non-volatile D flip-flop NVDFF has a slow D-Q delay and a tradeoff between its D-Q delay and its sensing current. In addition, a sufficient write current cannot be obtained with the core device, since two MTJs exist in the write path and a write current degradation problem occurs due to the precharge transistors. The proposed MTJ-based non-volatile semidynamic flip-flop NVSDFF has a semidynamic structure that ensures a fast D-Q delay and separates the sensing circuit from the D-Q signal path to reduce the sensing current without affecting the D-Q delay. The proposed NVSDFF also provides a sufficient write current by merely using the core device, since only one MTJ exists in the write path. In addition, the head switch, which is added to remove the write current degradation problem, further reduces the sensing current. Thus, the proposed NVSDFF has a higher read disturbance margin than the previous NVDFF with an IO device. The HSPICE simulation results with the industry-compatible 45nm model parameter show that the D-Q delay in the proposed NVSDFF is 50.5% of that of the previous NVDFF with an IO device, and the sensing current, 32.3%. In the proposed NVSDFF, the read disturbance margin is 15.9% larger than in the previous NVDFF with an IO device, and the area is 17.8% smaller. Copyright © 2012 John Wiley & Sons, Ltd.
TL;DR: This paper studies the design and implementation of a non-isolated dual-half-bridge bidirectional DC-DC converter for DC micro-grid system applications and finds high efficiency can be achieved under wide-range load variations by the zero-voltage-switching features and an adaptive phase-shift control method.
Abstract: This paper studies the design and implementation of a non-isolated dual-half-bridge bidirectional DC-DC converter for DC micro-grid system applications. High efficiency can be achieved under wide-range load variations by the zero-voltage-switching features and an adaptive phase-shift control method. A three-stage charging scheme is designed to meet the fast-charging demand and prolong the lifetime of LiFePO4 batteries. A digital-signal-processing control IC is used to realize the power flow control, DC-bus voltage regulation, and battery charging/ discharging of the studied bidirectional DC-DC converter. Finally, a 10kW prototype converter with Enhanced Controller Area Network communication function is built and tested for micro-grid system applications. A light-load efficiency over 96% and a rated-load efficiency over 98% can be achieved. Copyright © 2013 John Wiley & Sons, Ltd.
TL;DR: The proposed converter is derived from the conventional single-ended primary inductor converter SEPIC topology, and it can operate as a capacitor-diode voltage multiplier, which offers simple structure, reduced electromagnetic interference EMI, and reduced semiconductor voltage stress.
Abstract: A novel single switch two diode wide conversion ratio step down/up converter is presented. The proposed converter is derived from the conventional single-ended primary inductor converter SEPIC topology, and it can operate as a capacitor-diode voltage multiplier, which offers simple structure, reduced electromagnetic interference EMI, and reduced semiconductor voltage stress. The main advantages of the proposed converter are the continuous input/output current, higher voltage conversion ratio, and near-zero input and output current ripples compared with the conventional SEPIC converter. The absence of both a transformer and an extreme duty cycle permits the proposed converter to operate at high switching frequencies. Hence, the overall advantages will be: higher efficiency, reduced size and weight, simpler structure and control. The theoretical analysis results obtained with the proposed structure are compared with the conventional SEPIC topology. The performance of the proposed converter is verified through computer simulations and experimental results. Copyright © 2012 John Wiley & Sons, Ltd.
TL;DR: A novel four-phase oscillator employing two Dual-Output Controlled Gain Current Follower Buffered Amplifiers DO-CG-CFBAs, single Current Amplifier, three resistors, and two grounded capacitors suitable for differential quadrature signal production floating outputs is introduced.
Abstract: This paper introduces novel four-phase oscillator employing two Dual-Output Controlled Gain Current Follower Buffered Amplifiers DO-CG-CFBAs, single Current Amplifier, three resistors, and two grounded capacitors suitable for differential quadrature signal production floating outputs. To control the frequency of oscillation FO and condition of oscillation CO, only the current gain adjustment of active elements is used. The circuit was designed by well-known state variable approach. The oscillator employs three active elements for linear control of FO and to adjust CO and provides low-impedance voltage outputs. Furthermore, two straightforward ways of automatic amplitude gain control were used and compared. Active elements with very good performance are implemented to fulfill required features. Suitable CMOS implementation of introduced DO-CG-CFBA was shown. Important characteristics of the designed oscillator were verified experimentally and by PSpice simulations to confirm theoretical and expected presumptions. Copyright © 2013 John Wiley & Sons, Ltd.
TL;DR: The paper offers an algorithm for local and global parametric diagnosis in nonlinear analog circuits, including both identification of the faulty parameters and determination their values, and the homotopy concept is applied.
Abstract: The paper offers an algorithm for local and global parametric diagnosis in nonlinear analog circuits, including both identification of the faulty parameters and determination their values. The algorithm exploits a nonlinear algebraic type test equations which may possess multiple solutions, corresponding to different sets of the parameters values which meet the test. To find the solutions, the homotopy concept is applied. Since the test equation is not given in explicit analytical form, the simplicial method is used to trace the homotopy path. The proposed approach can be applied to a broad class of analog circuits, including the complementary metal-oxide-semiconductor circuits fabricated in nanometer technology. The developed diagnostic procedure has been implemented in DELPHI, whereas the required by the algorithm repeated circuit analyses are carried out using IsSPICE 4 and both environments have been joined together. For illustration, two numerical examples are given. Copyright © 2013 John Wiley & Sons, Ltd.
TL;DR: A high power-factor (PF) single-stage bridgeless AC/AC converter is proposed with higher efficiency, greater power factor, less harmonics to pass IEC 61000-3-2 class C, and better regulation of output current.
Abstract: An alternating-current light-emitting diode AC-LED driver is implemented between the grid and lamp to eliminate the disadvantages of a directly grid-tied AC-LED lamp. In order to highlight the benefits of AC-LED technology, a single-stage converter with few components is adopted. A high power-factor single-stage bridgeless AC/AC converter is proposed with higher efficiency, greater power factor, less harmonics to pass IEC 61000-3-2 class C, and better regulation of output current. The brightness and flicker frequency issues caused by a low-frequency sinusoidal input are surpassed by the implementation of a high-frequency square-wave output current. In addition, the characteristics of the proposed circuit are discussed and analyzed in order to design the AC-LED driver. Finally, some simulation and experimental results are shown to verify this proposed scheme. Copyright © 2012 John Wiley & Sons, Ltd.
TL;DR: A new tunable current-mode CM biquadratic filter with three inputs and three outputs using three dual-output inverting second-generation current conveyors, three grounded resistors and two grounded capacitors is proposed, which exhibits low-input impedance and high-output impedance which is important for easy cascading in the CM operations.
Abstract: A new tunable current-mode CM biquadratic filter with three inputs and three outputs using three dual-output inverting second-generation current conveyors, three grounded resistors and two grounded capacitors is proposed. The proposed circuit exhibits low-input impedance and high-output impedance which is important for easy cascading in the CM operations. It can realize lowpass, bandpass, highpass, bandreject and allpass biquadratic filtering responses from the same topology. The circuit permits orthogonal controllability of the quality factor Q and resonance angular frequency ωo, and no component matching conditions or inverting-type input current signals are imposed. All the passive and active sensitivities are low. Hspice simulation results are based on using TSMC 0.18µm 1P6M process complementary metal oxide semiconductor technology and supply voltages ±0.9V to verify the theoretical analysis. Copyright © 2012 John Wiley & Sons, Ltd.
TL;DR: A new SRAM cell with body-bias actively controlled by a control circuit and word line is introduced to realize low-power and high-speed applications and reduces the static power consumption and improves the read and write performance.
Abstract: In this paper, a new SRAM cell with body-bias actively controlled by a control circuit and word line is introduced to realize low-power and high-speed applications. The cell uses two word lines, which vary between positive and negative voltage levels to control the body bias of cell's transistors. In this design, using a peripheral control circuit with the least possible number of transistors, the access time is decreased and also a trade-off between static and dynamic power consumption is provided. Compared to a conventional SRAM cell, the proposed cell reduces the static power consumption by 82% and improves the read performance by 40% and the write performance by 27%. Copyright © 2013 John Wiley & Sons, Ltd.
TL;DR: Since asymmetrical PWM is used to control active switches, the leakage inductance and output capacitance of active switches are resonant in the transition interval and both active switches can be turned on at zero voltage switching.
Abstract: An interleaved DC-DC converter with soft switching technique is presented. There are two converter modules in the adopted circuit to share the load power. Since the interleaved pulse-width modulation PWM is adopted to control two circuit modules, the ripple currents at input and output sides are naturally reduced. Therefore the input and output capacitances can be reduced. In each circuit module, a conventional boost converter and a voltage doubler configuration with a coupled inductor are connected in series at the output side to achieve high step-up voltage conversion ratio. Active snubber connected in parallel with boost inductor is adopted to limit voltage stress on active switch and to release the energy stored in the leakage and magnetizing inductances. Since asymmetrical PWM is used to control active switches, the leakage inductance and output capacitance of active switches are resonant in the transition interval. Thus, both active switches can be turned on at zero voltage switching. The resonant inductance and output capacitances at the secondary side of transformer are resonant to achieve zero current switching turn-off for rectifier diodes. Therefore, the reverse recovery losses of fast recovery diodes are reduced. Finally, experiments based on a laboratory prototype rated at 400W are presented to verify the effectiveness of the proposed converter. Copyright © 2012 John Wiley & Sons, Ltd.
TL;DR: A four-stage amplifier with a new and efficient frequency compensation topology is presented in this paper and it is shown that when driving a 500 pF load, the amplifier has a gain-bandwidth product of 18 MHz consuming only 40.9 µW and dissipating 55.2 µW from a single 0.9 V power supply.
Abstract: A four-stage amplifier with a new and efficient frequency compensation topology is presented in this paper. The new compensation scheme applies a Miller capacitor as the main negative feedback, a resistor and a capacitor in series as a load for one of the intermediate stages, and two feedforward paths. In order to design the amplifier and acquire circuit parameters, small signal analyses have been carried out to derive the signal transfer function and the pole-zero locations. The proposed amplifier was designed and implemented in a standard 90 nm CMOS process with two heavy capacitive loads of 500 pF and 1 nF. The simulation results show that when driving a 500 pF load, the amplifier has a gain-bandwidth product of 18 MHz consuming only 40.9 µW. With a 1 nF capacitive load, the proposed amplifier achieves 15.1 MHz gain-bandwidth product and dissipates 55.2 µW from a single 0.9 V power supply. Copyright © 2013 John Wiley & Sons, Ltd.
TL;DR: The proposed analysis shows that the output phase error is a function of injection current and the current of source equivalent capacitor, and it is shown that increasing of tail current and LC tank quality factor decreases the phase error.
Abstract: This paper presents a novel approach to study the phase error in source injection coupled quadrature oscillators QOs. Like other LC QOs, the mismatches between LC tanks are the main source of phase error in this oscillator. The QO is analyzed where the phase error and oscillation frequency are derived in terms of circuit parameters. The proposed analysis shows that the output phase error is a function of injection current and the current of source equivalent capacitor. As a result, it is shown that increasing of tail current and LC tank quality factor decreases the phase error. Derived equations show that the phase error can be cancelled and even controlled by adjusting bias currents. To evaluate the proposed analysis and consequent designed QO, a 5.5 GHz CMOS QO is designed and simulated using the practical 0.18 µm TSMC CMOS technology. The experiments show good agreement between analytical equations and simulation results. Copyright © 2013 John Wiley & Sons, Ltd.
TL;DR: This paper presents a module-integrated isolated solar micro-inverter that can individually extract the maximum solar power from each photovoltaic (PV) panel and transfer to the AC utility system.
Abstract: This paper presents a module-integrated isolated solar micro-inverter. The studied grid-tied micro-inverters can individually extract the maximum solar power from each photovoltaic PV panel and transfer to the AC utility system. A harmonic suppression technique is used to reduce the DC-bus capacitance. Electrolytic capacitors are not needed in the studied solar micro-inverter. High conversion efficiency, high maximum power point tracking accuracy and long lifespan can be achieved. The operation principles and design considerations of the studied PV inverter are analyzed and discussed. A laboratory prototype is implemented and tested to verify its feasibility. Copyright © 2012 John Wiley & Sons, Ltd.