Showing papers in "International Journal of High Speed Electronics and Systems in 2017"

Scaling Challenges for Advanced CMOS Devices

Abstract: The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.

Carbon Nanotubes, Nanofibers and Nanospikes for Electrochemical Sensing: A Review

Abstract: The structural and material properties of carbon based sensors have spurred their use in biosensing applications. Carbon electrodes are advantageous for electrochemical sensors due to their increased electroactive surface areas, enhanced electron transfer, and increased adsorption of target molecules. The bonding properties of carbon allows it to form a variety of crystal structures. This paper performs a comparative review of carbon nanostructures for electrochemical sensing applications. The review specifically compares carbon nanotubes (CNT), carbon nanofibers (CNF), and carbon nanospikes (CNS). These carbon nanostructures possess defect sites and oxygen functional groups that aid in electron transfer and adsorption processes.

Integrated On-Chip Nano-Optomechanical Systems

Abstract: Recent developments in integrated on-chip nano-optomechanical systems are reviewed. Silicon-based nano-optomechanical devices are fabricated by a two-step process, where the first step is a foundry ...

Fabrication of Robust Nano-Signatures for Identification of Authentic Electronic Components and Counterfeit Avoidance

Abstract: In this paper, a novel approach for marking integrated circuit packages with authentication nanosignatures is introduced. In this work, the signatures patterns are fabricated using electron beam lithography. Moreover, the robustness of these signatures against aging and humidity is investigated. A recipe comprising image processing techniques and measurement of similarity indices has been developed. These signatures are proposed to be fabricated at the manufacturer side of the supply chain. Then, they are decoded at the consumer end. Thus, robustness against ambient environment and aging is a requirement for these signatures to survive in the global supply chain. Calculated Mean Square Error and Structural SIMilarity Index confirmed that the reflected patterns of the signatures remain unchanged against aging and humidity.

High-Speed SiGe BiCMOS Technologies and Circuits

Abstract: This work reports on the development of SiGe-BiCMOS technologies for mm-wave and THz high frequency applications. We present state-of-the-art performances for different SiGe heterojunction bipolar transistor (SiGe-HBT) developments as well as the evolution of complex BiCMOS technologies. With respect to different technology generations of high-speed SiGe-BiCMOS processes at IHP we discuss selected device modifications of the SiGe-HBT to achieve high frequency performances of a complex BiCMOS technology towards the 0.5 THz regime. We show the difference of high-frequency performance difference with respect to maximum achievable transit frequencies fT and oscillation frequencies fmax in comparison to RF-CMOS technologies and depict the required increase of additional process effort for the HBT-module integration for a 0.5 THz SiGe-BiCMOS technology. Moreover different high speed circuits are presented like broadband ICs for optical communication, high frequency circuits for wireless communication at 60 and 240 GHz, mm-wave radar circuits at 60 and 120 GHz as well as THz circuits operating at 245 GHz and 500 GHz for spectroscopic applications. All reviewed circuit examples are based on the discussed 130nm-SiGe-BiCMOS technologies and show their potential for a broad range of high-speed applications.

Pixel Characterization of a Protein-Based Retinal Implant Using a Microfabricated Sensor Array

Abstract: Retinal degenerative diseases are characterized by the loss of photoreceptor cells within the retina and affect 30-50 million people worldwide. Despite the availability of treatments that slow the progression of degeneration, affected patients will go blind. Thus, there is a significant need for a prosthetic that is capable of restoring functional vision for these patients. The protein-based retinal implant offers a high-resolution option for replacing the function of diseased photoreceptor cells by interfacing with the underlying retinal tissue, stimulating the remaining neural network, and transmitting this signal to the brain. The retinal implant uses the photoactive protein, bacteriorhodopsin, to generate an ion gradient in the subretinal space that is capable of activating the remaining bipolar and ganglion cells within the retina. Bacteriorhodopsin can also be photochemically driven to an active (bR) or inactive (Q) state, and we aim to exploit this photochemistry to mediate the activity of pixels within the retinal implant. In this study, we made use of a novel retinomorphic foveated image sensor to characterize the formation of active and inactive pixels within a protein-based retinal implant, and have measured a significant difference between the output frequencies associated with the bR and Q states.

LP-HS Logic Evaluation on TSMC 0.18μm CMOS Technology

Abstract: Present paper analyses different aspects of “Low Power-High Speed” (LP-HS) logic in favour of present day ULSI system focus. At first, the speed-power efficiency of LP-HS logic is investigated by d...

Denoising and Beat Detection of ECG Signal by Using FPGA

Abstract: This paper introduces an efficient digital system design using hardware concepts to filter the Electrocardiogram (ECG) signal and to detect QRS complex (beats). The system implementation has been done using a Field Programmable Gate Array (FPGA) in two phases. In the first phase, Finite Impule Response (FIR) filters are designed for preprocessing and denoising the ECG signal. The filtered signal is then used as the input of the second phase to detect and classify the ECG beats. The entire system has been implemented on ALTERA DE II FPGA by desinging synthesizable finite state machines. The design has been tested on ECG waves from the MIT-BIH Arrhythmia database by windowing the signal and applying adaptive signal and noise theresholds in each window of processing. The hardware system has achieved an overall accuracy of 98% in the beat detection phase, while providing the detected beats and the classification of irregular heat-beat rates in real-time. The synthesized hardware of the ECG denoising and beat detection system yields reasonable hardware resources, making the system attractive to be eventually fabricated as a stand alone hardware system or integrated/embedded within a portable electronic device for monitoring patients’ conditions on a daily basis conveinently.

Encrypted Electron Beam Lithography Nano-Signatures for Authentication

Abstract: In this work, engineered nanostructures (ENS) have been fabricated on the packed integrated circuits. Coding lookup tables were developed to assign different digits in numerical matrices to different fabricated nano-signatures. The numerical matrices are encrypted according to advanced encryption standard (AES). The encrypted numerical matrix is ink printed on the components, and the nanosignatures are fabricated on the packaged of the chips via electron beam lithography (EBL). This process is to be done in the manufacturer side of the supply chain. The numerical matrix and the nanosignature accompany the product in its long journey in the global supply chain. The global supply chain is proved to be susceptible to counterfeiters. For keeping counterfeiters‘ hands out of the process, the cipher key and the coding lookup tables are provided to the consumer using a secure direct line between the authentic manufacturer and the consumer. In the consumer side, the printed numerical matrix is decrypted. Having the decrypted numerical matrix makes it possible to extract the nanosignature from the laser speckle pattern shined on the packaged product. In this work, an algorithm is developed to extract the nano-signature by having the decrypted matrix and reflected laser speckle patterns as inputs. Confirming the existence of the nano-signature confirms the authenticity of the component. Imitating the nano-signatures by the counterfeiters is not possible because there is no way for them to observe the shape of these signatures without having access to the cipher key.

A Low-Power Low-Data Rate Impulse Radio Ultra-Wideband (IR-UWB) Transmitter

Abstract: A low-power and low-data-rate (100 kbps) fully integrated CMOS impulse radio ultra-wideband (IR-UWB) transmitter for biomedical application is presented in this paper. The transmitter is designed using a standard 180-nm CMOS technology that operates at the 3.1-5 GHz frequency range with more than 500 MHz of channel bandwidth. Modulation scheme of this transmitter is based on on-off keying (OOK) in which a short pulse represents binary “1” and absence of a pulse represents binary “0” transmission. During the ‘off’ state (sleep mode) the transmitter consumes only 0.4 μW of power for an operating voltage of 1.8 V while during the impulse transmission state it consumes a power of 36.29 μW. A pulse duration of about 3.5 ns and a peak amplitude of the frequency spectrum of about -47.8 dBm/MHz are obtained in the simulation result which fully complies with Federal Communication Commission (FCC) regulation.

Optimization of Selective Growth of SiGe for Source/Drain in 14nm and Beyond Nodes FinFETs

Abstract: In this work, optimization of selective epitaxy growth (SEG) of SiGe layers on source/drain (S/D) areas in 14nm node FinFETs with high-k & metal gate has been presented. The Ge content in epilayers was in range of 30%-40% with boron concentration of 1-3 × 1020 cm−3. The strain distribution in the transistor structure due to SiGe as stressor material in S/D was simulated and these results were used as feedback to design the layer profile. The epitaxy parameters were optimized to improve the layer quality and strain amount of SiGe layers. The in-situ cleaning of Si fins was crucial to grow high quality layers and a series of experiments were performed in range of 760-825 °C. The results demonstrated that the thermal budget has to be within 780-800 °C in order to remove the native oxide but also to avoid any harm to the shape of Si fins. The Ge content in SiGe layers was directly determined from the misfit parameters obtained from reciprocal space mappings using synchrotron radiation. Atomic layer deposition (ALD) technique was used to deposit HfO2 as high-k dielectric and B-doped W layer as metal gate to fill the gate trench. This type of ALD metal gate has decent growth rate, low resistivity and excellent capability to fill the gate trench with high aspect-ratio. Finally, the electrical characteristics of fabricated FinFETs were demonstrated and discussed.

Evolutionary Computation Based Sizing Technique of Nulling Resistor Compensation Based CMOS Two-Stage Op-Amp Circuit

Abstract: This article explores the comparative optimizing efficiency between two PSO variants, namely, Craziness based PSO (CRPSO) and PSO with an Aging Leader and Challengers (ALC-PSO) for the design of nulling resistor compensation based CMOS two-stage op-amp circuit. The concept of PSO is simple and it replicates the nature of bird flocking. As compared with Genetic algorithm (GA), PSO deals with less mathematical operators. Premature convergence and stagnation problem are the two major limitations of PSO technique. CRPSO and ALC-PSO techniques individually have eliminated the disadvantages of the PSO technique. In this article, CRPSO and ALC-PSO are individually employed to optimize the sizes of the MOS transistors to reduce the overall area taken by the circuit while satisfying the design constraints. The results obtained individually from CRPSO and ALC-PSO techniques are validated in SPICE environment. SPICE based simulation results justify that ALC-PSO is much better technique than CRPSO and other formerly ...

Influence on Characteristics of RTD Due to Variation of Different Parameters and Material Properties

Abstract: In this paper, novel features offered by Resonant Tunneling Diode (RTD) are reviewed by simulating it under different conditions. GaAs/AlGaAs based RTD is used as the reference one to obtain the characteristics due to parametric variations. To fulfil this purpose a simple model of resonant electronic transport through a double-barrier structure is developed. I-V characteristics are studied by varying barrier parameters and well width. Different peak and valley currents are measured under these conditions. For the same set of parameters both symmetric and asymmetric cases are considered. Different materials of lower effective mass are also taken into consideration to improve Peak to Valley Ratio (PVR). The Indium (In) based materials are considered to compare the characteristics obtained from the conventional GaAs based RTD structure. All these proposed structures are simulated using Silvaco Atlas software.

Spatial Wavefunction Switched (SWS) FET SRAM Circuits and Simulation

Abstract: This paper presents the design and simulation of static random access memory (SRAM) using two channel spatial wavefunction switched field-effect transistor (SWS-FET), also known as a twin-drain met...

Dynamical X-Ray Diffraction Analysis of Triple-Junction Solar Cells on Germanium (001) Substrates

Abstract: We demonstrate the dynamical x-ray diffraction analysis of metamorphic triple-junction solar cells grown on Ge (001) substrates. The solar cells investigated involve an In0.67Ga0.33P top cell, an In0.17Ga0.83As middle cell, and a Ge bottom cell. A graded buffer layer is inserted between the bottom and middle cells for the purpose of accommodating the lattice mismatch. Linearly-graded, step-graded, and S-graded compositional profiles were considered for this buffer layer. The x-ray rocking curve analysis for a number of hkl reflections including 004, 113, 116, 044, 026, and 117 was conducted for the case of Cu Kα1 radiation. We show that the use of non-destructive x-ray analysis allows determination of the threading dislocation densities in the top two cells. In the cases of S-graded or step-graded buffer layers, the buffer threading dislocation density could also be estimated.

Critical Layer Thickness: Theory and Experiment in the ZnSe/GaAs (001) Material System

Abstract: The critical layer thickness (CLT) determines the criteria for dislocation formation and the onset of lattice relaxation. Although several theoretical models have been developed for the critical layer thickness, experimentally-measured CLTs in ZnSe/GaAs (001) heterostructures are often at variance with one another as well as with established theories. In a previous work [T. Kujofsa et al., J. Vac. Sci. Technol. B, 34, 051201 (2016)], we showed that the experimentally measured CLT may be much larger than the equilibrium value when using finite experimental resolution. In this work, we apply a general dislocation flow model to determine the apparent critical layer thickness as a function of the experimental resolution for ZnSe/GaAs (001) heterostructures. More importantly, we compare the results utilizing different equilibrium theories and therefore varying driving forces for the lattice relaxation in order to determine which established models are consistent with several measured values of CLT for ZnSe/GaAs (001) once kinetically-limited relaxation and finite experimental strain resolution are taken into account.

Multi-Bit NVRAMs Using Quantum Dot Gate Access Channel

Abstract: This paper presents a quantum dot access channel nonvolatile random access memory (QDAC-NVRAM) which has comparable write and erase times to conventional random access memories but consumes less power and has a smaller footprint. We have fabricated long-channel (W/L=15μm/10μm) nonvolatile random access memories (NVRAMs) with 4μs erase times. These devices are CMOS-compatible and employ novel quantum dot access channel (QDAC) which enables fast storage and retrieval of charge from the floating gate layer. In addition, QDNVRAMs are shown to be capable of storing multiple-bits and potentially scalable to sub 22nm. We are also presenting the simulation results. This paper also presents a memory array architecture using QDAC-NVRAMs.

Quantum Dot Channel (QDC) Field Effect Transistors (FETs) Configured as Floating Gate Nonvolatile Memories (NVMs)

Abstract: This paper presents quantum dot channel (QDC) Field Effect Transistors (FETs) which are configured as nonvolatile memories (NVMs) by incorporating cladded GeOx-Ge quantum dots in the floating gates as well as the transport channels. The current flow and the threshold characteristics were significantly improved when the gate dielectric was changed from silicon dioxide (SiO2) to hafnium aluminum oxide (HfAlO2), and the control dielectric was changed from silicon nitride (Si3N4) to hafnium aluminum oxide (HfAlO2). The device operations are explained by carrier transport in narrow energy mini-bands which are manifested in a quantum dot transport channel.

Topological Insulators: Electronic Structure, Material Systems and Applications

Abstract: Topological insulators are a new class of materials characterized by fully spin-polarized surface states, a linear dispersion, imperviousness to external non-magnetic perturbations, and a helical character arising out of the perpendicular spin-momentum locking. This article answers in a pedagogical way the distinction between a topological and normal insulator, the role of topology in band theory of solids, and the origin of these surface states. Numerical techniques including diagonalization of the TI Hamiltonians are described to quantitatively evaluate the behaviour of topological insulator states. The Hamiltonians based on continuum and tight binding approaches are contrasted. The application of TIs as components of a fast switching environment or channel material for transistors is examined through I-V curves. The potential pitfall of such devices is presented along with techniques that could potentially circumvent the problem. Additionally, it is demonstrated that a strong internal electric field can also induce topological insulator behaviour with wurtzite nitride quantum wells as representative materials.

Carbon Nanotube Synthesis from Block Copolymer Deposited Catalyst

Abstract: A block copolymer/metal-salt solution was used to deposit metal nanoparticles on substrates, from which carbon nanotubes (CNTs) were grown in a chemical vapor deposition (CVD) chamber. Mono and hybrid catalysts of Fe, Ni, and Co-nitrates were tested, and separately Co, Ni, and Cu-chlorides. In both cases cobalt/cobalt-hybrids produced the highest density of multi-wall carbon nanotubes (MWCNTs). Slight vertical growth, though sparse, was observed after growth at 800°C from a nickel catalyst on single-crystal aluminium oxide (~130nm diameter).

Dynamic Conductivity and Two-Dimensional Plasmons in Lateral CNT Networks

Abstract: We study theoretically the carrier transport and the plasmonic phenomena in the gated structures with dense lateral carbon nanotube (CNT) networks (CNT “felt”) placed between the highly-conducting slot line electrodes. The CNT networks under consideration consist of a mixture of semiconducting and metallic CNTs. We find the dispersion relations for the two-dimensional plasmons, associated with the collective self-consisted motion of electrons in the individual CNTs, propagating along the electrodes as functions of the net electron density (gate voltage), relative fraction of the semiconducting and metallic CNTs, and the spacing between the electrodes. In a wide range of parameters, the characteristic plasmonic frequencies can fall in the terahertz (THz) range. The structures with lateral CNT networks can used in different THz devices.

Progression of Strain Relaxation in Linearly-Graded GaAs1-yPy/GaAs (001) Epitaxial Layers Approximated by a Finite Number of Sublayers

Abstract: We have investigated the residual in-plane strain and width of the surface misfit dislocation free zone in linearly-graded GaAs1-yPy metamorphic buffer layers as approximated by a finite number of ...

Design Issues in Beam Structures for Performance Enhancement of MEMS Based Capacitive Accelerometer

Abstract: Structure of a MEMS based Capacitive Accelerometer has been analyzed in this paper. The symmetrical beam-mass structure with different interconnection has been investigated using Finite Element met...

Mosaic Crystal Model for Dynamical X-Ray Diffraction from Step-Graded InxGa1-xAs and InxAl1-xAs/GaAs (001) Metamorphic Buffers and Device Structures

Abstract: In this paper we apply a mosaic crystal model for dynamical x-ray diffraction to step-graded metamorphic semiconductor device structures containing dislocations. This model represents an extension of the previously-reported phase-invariant model, which is broadly applicable and serves as the basis for the x-ray characterization of metamorphic structures, allowing determination of the depth profiles of strain, composition, and dislocation density. The new model has more general applicability and is more appropriate for step-graded metamorphic device structures, which are of particular interest for high electron mobility transistors and light emitting diodes. Here we present the computational details of the mosaic crystal model and demonstrate its application to step-graded InxGa1-xAs/GaAs (001) and InxAl1-xAs/GaAs (001) metamorphic buffers and device structures.