Showing papers in "Journal of Circuits, Systems, and Computers in 1998"

The application of Petri-nets to workflow management

Abstract: Workflow management promises a new solution to an age-old problem: controlling, monitoring, optimizing and supporting business processes. What is new about workflow management is the explicit representation of the business process logic which allows for computerized support. This paper discusses the use of Petri nets in the context of workflow management. Petri nets are an established tool for modeling and analyzing processes. On the one hand, Petri nets can be used as a design language for the specification of complex workflows. On the other hand, Petri net theory provides for powerful analysis techniques which can be used to verify the correctness of workflow procedures. This paper introduces workflow management as an application domain for Petri nets, presents state-of-the-art results with respect to the verification of workflows, and highlights some Petri-net-based workflow tools.

Continuous and hybrid Petri nets

Abstract: Petri nets are widely used to model discrete event dynamic systems (computer systems, manufacturing systems, communication systems…). When a PN contains a large number of tokens, the number of reachable states explodes. This is a practical limitation to the use of Petri nets. Continuous models may provide very good approximations for discrete event systems: this is the basic idea leading to the definition of continuous Petri nets. A continuous PN is a model in which the marking of each place is a real number. In a timed continuous PN, a firing speed is associated with each transition (this basic model is unique although the firing speed may be defined in several ways). Various timed continuous PN models have been defined and they correspond to a specific calculation of the firing speeds. They provide good approximations for performance evaluation when a PN contains a large number of tokens. Modeling a number of parts in a buffer by a real number may generally be an acceptable approximation. However, the s...

Recent developments in non-markovian stochastic petri nets

Abstract: Analytical modeling plays a crucial role in the analysis and design of computer systems. Stochastic Petri Nets represent a powerful paradigm, widely used for such modeling in the context of dependability, performance and performability. Many structural and stochastic extensions have been proposed in recent years to increase their modeling power, or their capability to handle large systems. This paper reviews recent developments by providing the theoretical background and the possible areas of application. Markovian Petri Nets are first considered together with very well established extensions known as Generalized Stochastic Petri Nets and Stochastic Reward Nets. Key ideas for coping with large state spaces are then discussed. The challenging area of non-Markovian Petri nets is considered, and the related analysis techniques are surveyed together with the detailed elaboration of an example. Finally new models based on Continuous or Fluid Stochastic Petri Nets are briefly discussed.

Handwritten chinese character recognition with directional decomposition cellular features

Abstract: A new feature extraction approach based on elastic meshing and directional decomposition techniques for handwritten Chinese character recognition (HCCR) is proposed in this letter. It is found that decomposing a Chinese character into horizontal, vertical stroke, left slant and right slant directional sub-patterns is very helpful for feature extraction and recognition. Three kinds of decomposition methods are proposed. A minimum distance classifier is trained by 3755 categories of characters using the new features. Testing on a total of 37,550 untrained handwritten samples produces the recognition rate of 92.36%, showing the effectiveness of the proposed approach.

On linear algebraic techniques for liveness analysis of p/t systems

Abstract: Liveness is a basic property that in many discrete event dynamic systems is considered essential for their correct behavior. It expresses that no action (transition in P/T models) will ever become unattainable. A polynomial time necessary condition for the existence of a live and bounded marking of a P/T net is given. This condition is shown to be also sufficient for some subclasses. The applicability of these results is extended by the use of transformation techniques that allow for their exploitation in the analysis of more general nets. Some results for the structural analysis of actual liveness are also overviewed, in particular, sufficient conditions for deadlock-freeness and absence of dead transitions.

An approach to object system modeling by state-based object petri nets

Abstract: For many years, Petri nets have been used for modeling the behavior of various types of concurrent systems. While these net models are especially well suited to capture the behavior of concurrent systems, it is still the case that net models do not easily capture some important structural aspects of a system, such as modularity. In terms of software systems for distributed applications, the object-oriented paradigm has become a standard for defining modularity and reuse of software. Thus, an evolving direction in Petri net technology is the blending of net features with object-oriented capability. This paper discusses one such approach for state-based object systems.

The use of petri nets for the design and verification of asynchronous circuits and systems

Abstract: Petri nets46,37,45,48 are a powerful formalism for modeling concurrent systems. They are capable of implicitly describing a vast state space by a succinct representation which gracefully captures the notions of causality, concurrency and conflict between events. Petri nets have also been chosen by many authors as a formalism to describe the behavior of asynchronous circuits by interpreting the events as signal transitions, thus coining the term Signal Transition Graph (STG).50,4 A design framework for asynchronous systems involves three main aspects: formal specification, verification and synthesis. In this paper we review the main techniques we have used to cover these aspects in recent years, with a special focus on asynchronous circuits.

New grounded-capacitor current-mode oscillators using single-output cciis

Abstract: In this paper five novel minimal-C and grounded-C current-mode oscillators, using single output CCIIs are reported. The proposed oscillators are classified into three classes based on the number of CCIIs used. The oscillator circuits of class I employ two CCII+s, whereas the class II oscillator employs three CCII+s and those of the class III employ four CCII+s. PSpice simulation results demonstrating the performance of the proposed oscillators are included.

Two cellular architectures for integrated image sensing and processing on a single chip

Abstract: Two architectures for a programmable image processor with on-chip light sensing capability are described. The first is a VLSI implementation of a cellular neural network. The second is a distributed dual-structure mutation of the first architecture. The distributed dual architecture leverages the speed of silicon against the large silicon area requirements. Moreover, the innovative integrated nature of the dual-structure design significantly reduces the bottleneck and computational overload caused by data transfer from sensory focal plane to the image processor. The paper also describes VLSI chip prototypes and test results.

A learning parallel analog-to-digital vector quantizer

Abstract: A mixed-mode VLSI architecture for learning vector quantization (LVQ), with on-chip adaptation and dynamic storage of the analog templates, converts analog vectorial data in parallel to digital for...

Digital arithmetic using analog cellular neural networks

Abstract: We discuss the realization of digital arithmetic using analog arrays in the form of Cellular Neural Networks (CNNs). These networks replace the fast switching nodes of logic gates with slewing nodes using current sources driving into capacitors; this provides both low current spikes and low voltage slewing rates, reducing system noise and cross-talk in low-voltage mixed-signal applications. In this paper we generalize the design methodology using a Symbolic Substitution (SS) technique, and we use a recently developed Double-Base Number System (DBNS) to illustrate our design technique. This choice is predicated on the fact that the DBNS representation is naturally 2-dimensional and excites more degrees of freedom in the design space. Spatial configurations of the recognition/replacement patterns used in SS are defined based on the properties of the DBNS arithmetic operation. The SS recognition phases are implemented by dynamic evaluation of simple conditions defined based on an analysis of the cell dynamic routes. The replacement phases are automatically executed through switching current which force the transition of cell state voltage between logic levels. In effect, we build self-timed logic arrays with all nodes in the system under controlled slew. Simulation results from schematic level designs are provided to demonstrate the effectiveness of the technique.

A cmos low-voltage transconductor for vhf continuous-time filters

Abstract: A new CMOS low-voltage transconductor suitable for VHF continuous-time filters is proposed. The transconductance is tunable with the tunable input common-mode voltage. The output resistance of the transconductor is compensated and the resulting output resistance can be fine-tuned by means of a separate voltage. The transconductor has a large bandwidth due to excess phase compensation. Further, it exhibits low distortion due to the square-law linearization technique used. The performance of the transconductor is shown by simulation results.

Active rc filters using operational transresistance amplifiers

Abstract: A new generalized universal filter configuration using the Operational Transresistance Amplifier is proposed. Twelve different filter circuits are derived from the general configuration. The circuits are designed to provide Low-pass, Band-pass, High-pass, All-pass and Notch responses through appropriate choice of admittances. The feasibility of this configuration in operating at high frequencies is presented. A detailed analysis taking the effect of the finite transresistance gain into consideration is presented. Self-compensation that requires no additional elements of some of the proposed filters is presented. The effectiveness of the proposed configuration is demonstrated by HSpice simulations.

Implementation issues for high-bandwidth field-programmable analog arrays

Abstract: This paper is a tutorial introduction to field-programmable analog arrays, as well as a review of existing field-programmable analog array architectures, of both educational and industrial origin. Circuit issues relevant to the development of high-bandwidth FPAAs are presented. A current conveyor-based architecture, which promises to achieve video bandwidths, is described. Test results are presented for the CMOS current conveyor-based FPAA building block, with programmable transconductors and capacitors. Measurements indicate bandwidths in excess of 10 MHz, and functionality of amplifiers, integrators, differentiators, and adders. The die area is 1.5 mm× 3.5 mm in a 0.8 μm CMOS technology.

A constructive method for finding legal transition sequences in petri nets

Abstract: This paper considers the Petri net reachability problem formulated in terms of nonnegative integer solutions of the state equation and their net representation systems. Our main contributions are twofold. First, we show that algorithms for finding legal transition sequences can be easily given for subclasses of Petri nets where reachability criteria are known or can be formulated by our method. Second, for the general reachability problem where reachability theorems or criteria are not known, and thus an exhaustive search for legal transition sequences is inevitable, we introduce the notion of non-crucial sequences to reduce the search effort.

Realization of analog fuzzy logic control for pwm boost converters

Abstract: Fuzzy logic controllers (FLCs) have been widely used in many applications. However, they are usually implemented digitally by expensive digital signal processors (DSPs), and the performance is restricted by the sampling period. These disadvantages have limited the applications of FLCs to industrial systems such as switch mode power converters. In this paper, an analog FLC implemented by low-cost devices is proposed. Through analog circuitry, features such as membership function shaping, rule inference and defuzzification are realized. The controller is successfully applied to regulate a PWM boost converter with satisfactory performance.

A low-variation nonlinear neuron circuit

Abstract: A resistive-type neuron circuit is presented that combines nonlinear characteristics of four MOS transistors to realize a saturating function. Despite circuit simplicity, characteristic variations are found to be small based on circuit analyses and fabrication measurements. Maximum variation between neurons within one chip is 1.3%, while worst-case chip-to-chip variation from 10 fabrications is 2.2%.

Mathematical modeling of analog controlled voltage source converters for improved dynamic response

Abstract: Increases in the occurrence of nonlinear loads have resulted in the need to reduce or minimize the levels of harmonic currents being injected into the power supply As a consequence, active current waveshaping and pulse-width modulation have now replaced conventional phase-controlled and diode bridge rectifiers in many applications In this paper, mathematical models are developed for the power circuits of analog controlled single-phase and three-phase voltage source converters, and then used to analyse the performance of current- and voltage-control loops for the converters Analytical expressions are derived for the gains and time constants of the current and voltage controllers, and it is shown that the bandwidth of the current-loop is a function of the switching frequency, and that of the voltage-loop is a function of the DC-busbar capacitance and the voltage filter cut-off frequency To illustrate the application of the models, simulation results are presented from investigations into the control of a 5 kW single-phase voltage-source converter and a 100 kW three-phase boost converter

Filtering applications of field programmable analog arrays

Abstract: A Field Programmable Analog Array (FPAA), built in CMOS technology, contains uncommitted operational amplifiers, switches, and capacitors. A FPAA containing banks of programmable switched capacitors (SC) can be used to build filters for analog signals as well as a large number of diverse analog applications. The parameters of a given application, such as a filter, are functions of the capacitor values. Manufacturing and quantization errors may result in capacitor values in the FPAA other than those required by the application. For an FPAA to be a viable substitute for dedicated devices we must examine the error performance of the implementation. Such performance analysis can be built into the software to provide circuit designers with additional information. A methodology is described for determining a bound for the filter error as a function of capacitor errors and capacitor sizes. An example of detailed analysis for a low pass filter is included. Measurements of a low-pass filter implemented using Motorola's prototype FPAA compared favorably with the model predictions.

Chebyshev-family of transitional filters

Abstract: The TCC (Transitional-Chebyshev-Chebyshev)-filters are examined in some detail. Closed-form expressions for pole-locations are obtained, where possible. In cases where it is not possible, algorithms or geometrical iterative methods have been enunciated in order to determine the pole-locations. Performance indices for certain low-order transitional filters have been computed and tabulated. These clearly illustrate the transitional nature of these filters.

A symbolic circuit modeling program for dc/dc power converter circuits

Abstract: In this letter a computer-based symbolic circuit modeling program, applicable to any arbitrary PWM dc/dc converter circuit, is presented. From the circuit description, this program automatically ge...

On the correctness of hardware scheduling mechanisms for out-of-order execution

Abstract: Hardware scheduling mechanisms are commonly used in current processors in order to make better use of instruction level parallelism. So far, such a mechanism is considered to be correct, if it avoids the standard structural and data hazards. However, based on two classical scheduling mechanisms, it will be shown that this condition is neither sufficient nor necessary for the correctness of such a mechanism, and that deadlocks are a serious matter in out-of-order execution as well. In addition, the paper provides sufficient conditions for the correctness of scheduling mechanisms.

Correct diagnosis of almost all faulty units in a multiprocessor system

Abstract: In a t/t-diagnosable system, all faulty units can be located to within a set of no more than t units as long as the number of faulty units present does not exceed t. Furthermore, a unique doubtful unit can be identified; in other words, all faulty units, except possibly for one, can be correctly identified in a t/t-diagnosable system. An open question is "Is t/t-diagnosability necessary for correctly identifying all but one faulty unit?" In this paper, we address the above question and provide an answer. We establish necessary and sufficient conditions for correct diagnosis of all except possibly one faulty unit. In addition, we show that the fault-free state is indistinguishable from a faulty state in a t/t-diagnosable system and propose a remedy. These considerations result in the definition and characterization of a new class of systems called t/-1 diagnosable systems.

Upper bound on snr gain in wavelet transform predictive-entropy image coding

Abstract: Using the rate-distortion theory approach and assuming the Laplacian probability density function of the quantizer input signal, we propose a function which gives the signal-to-quantizing-noise ratio (SNR) gain in discrete wavelet transform predictive-entropy coding over fullband predictive image coding. The upper bound on SNR gain is determined as a function of the subband number only. The practical SNR performances of realizable wavelet still image coders are compared with their theoretical bounds. The computer simulation results of wavelet based predictive coded test images show that the SNR gain grows faster with the subband number increment than its theoretical upper bounds do.

Generalised split-radix algorithms for dft

Abstract: This letter presents a general split-radix algorithm based on the decimation-in-time decomposition. It can flexibly compute the discrete Fourier transforms of length-q*2m where q is an odd integer....

Neural network integrated circuits with single-block mixed signal arrays

Abstract: This paper discusses the design and implementation of a family of mixed-signal neural network integrated circuits for general and application-specific purposes. Regular Arrays of a nonlinearly-loaded multiplier block form the core of multi-layer neural networks. Input-output circuitry and network size, however, vary depending on design applications. Salient features of the present architecture, such as modularity and reduced interconnection problems and areas are highlighted and circuit design and improvements are presented for its universal building block. Other design issues such as supply voltage and power reduction and pin limitations are discussed together with experimental results.