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Showing papers in "Journal of Circuits, Systems, and Computers in 2017"


Journal ArticleDOI
TL;DR: A hybrid OFBAT-RBFL heart disease diagnosis system is designed and the experimentation result proves that the RBFL prediction algorithm outperformed the existing approach by attaining the accuracy of 78%.
Abstract: The objective of the work is to predict heart disease using computing techniques like an oppositional firefly with BAT and rule-based fuzzy logic (RBFL) The system would help the doctors to automate heart disease diagnosis and to enhance the medical care In this paper, a hybrid OFBAT-RBFL heart disease diagnosis system is designed Here, at first, the relevant features are selected from the dataset using locality preserving projection (LPP) algorithm which helps the diagnosis system to develop a classification model using the fuzzy logic system After that, the rules for the fuzzy system are created from the sample data Among the entire rules, the important and relevant group of rules are selected using OFBAT algorithm Here, the opposition based learning (OBL) is hybrid to the firefly with BAT algorithm to improve the performance of the FAT algorithm while optimizing the rules of the fuzzy logic system Next, the fuzzy system is designed with the help of designed fuzzy rules and membership functions so that classification can be carried out within the fuzzy system designed At last, the experimentation is performed by means of publicly available UCI datasets, ie, Cleveland, Hungarian and Switzerland datasets The experimentation result proves that the RBFL prediction algorithm outperformed the existing approach by attaining the accuracy of 78%

80 citations


Journal ArticleDOI
TL;DR: A novel method for Bat Algorithm (BA) based on optimal tuning of Fractional-Order Proportional Integral Derivative (FOPID) controller for governing the rotor speed of sensorless Brushless Direct Current (BLDC) motor is proposed.
Abstract: This paper deals with a novel method for Bat Algorithm (BA) based on optimal tuning of Fractional-Order Proportional Integral Derivative (FOPID) controller for governing the rotor speed of sensorless Brushless Direct Current (BLDC) motor. The BA is used for developing a novel optimization algorithm which can generate five degrees of freedom parameters namely Kp, Ki, Kd, λ and μ of FOPID controller. The desired speed control and robust performance are achieved by using the FOPID closed loop speed controller with the help of BA for optimal tuning. The time domain specifications of a dynamic system for unit step input to FOPID controller for speed response such as peak time (tr), Percentage of overshoot (PO), settling time (ts), rise time (tr) have been evaluated and the steady-state error (ess) of sensorless speed control of BLDC motor has been measured. The simulation results are compared with Artificial Bee Colony (ABC) optimization method and Modified Genetic Algorithm (MGA) for evaluation of transient a...

62 citations


Journal ArticleDOI
TL;DR: This paper presents a generalization of six well-known quadrature third-order oscillators into the fractional-order domain and eight special cases including the integer case are illustrated with their numerical discussions.
Abstract: This paper presents a generalization of six well-known quadrature third-order oscillators into the fractional-order domain. The generalization process involves replacement of three integer-order capacitors with fractional-order ones. The employment of fractional-order capacitors allows a complete tunability of oscillator frequency and phase. The presented oscillators are implemented with three active building blocks which are op-amp, current feedback operational amplifier (CFOA) and second generation current conveyor (CCII). The general state matrix, oscillation frequency and condition are deduced in terms of the fractional-order parameters. The extra degree of freedom provided by the fractional-order elements increases the design flexibility. Eight special cases including the integer case are illustrated with their numerical discussions. Three different phases are produced with fixed sum of 2π which can be completely controlled by fractional-order elements. A general design procedure is introduced to des...

60 citations


Journal ArticleDOI
TL;DR: This study aims toward a new methodology for evaluation and benchmarking using multi-criteria analysis for software and hardware “FPGA”-based digital watermarking or steganography.
Abstract: Evaluating and benchmarking software and hardware field programmable gate array (FPGA)-based digital watermarking are considered challenging tasks because of multiple and conflicting evaluation criteria. A few evaluation and benchmarking techniques/frameworks have been implemented to digital watermarking or steganography; however, these approaches still present certain limitations. In particular, fixing some attributes on account of other attributes and well-known benchmarking approaches are limited to robust watermarking techniques. Thus, this study aims toward a new methodology for evaluation and benchmarking using multi-criteria analysis for software and hardware “FPGA”-based digital watermarking or steganography. To achieve this objective, two iterations are conducted. The first iteration consists of two stages: discussing software and hardware “FPGA”-based digital watermarking or steganography to create a dataset with various samples for benchmarking and discussing the evaluation method and then disc...

58 citations


Journal ArticleDOI
TL;DR: Five main types are provided to provide systematic reviews about the QCA-based memories; including read only memory (ROM), register, flip-flop, content addressable memory (CAM) and random access memory (RAM).
Abstract: Quantum-dot cellular automata (QCA) has come out as one of the potential computational structures for the emerging nanocomputing systems It has a large capacity in the development of circuits with high space density and dissipation of low heat and allows faster computers to develop with lower power consumption The QCA is a new appliance to realize nanolevel digital devices and study and analyze their various parameters It is also a potential technology for low force and high-density memory plans Large memory designs in QCA show unique features because of their architectural structure In QCA-based architectures, memory must be maintained in motion, ie, the memory state has to be continuously moved through a set of QCA cells These architectures have different features, such as the number of bits stored in a loop, access type (serial or parallel) and cell arrangement for the memory bank However, the decisive features of the QCA memory cell design are the number of cells, to put off the use of energy Although the review and study of the QCA-based memories are very important, there is no complete and systematic literature review about the systematical analyses of the state of the mechanisms in this field Therefore, there are five main types to provide systematic reviews about the QCA-based memories; including read only memory (ROM), register, flip-flop, content addressable memory (CAM) and random access memory (RAM) Also, it has provided the advantages and disadvantages of the reviewed mechanisms and their important challenges so that some interesting lines for any coming research are provided

56 citations


Journal ArticleDOI
TL;DR: Results show that proposed simulator circuit provides frequency dependent pinched hysteresis loop and nonvolatility features, and is validated with PSPICE simulation and experimental results.
Abstract: In this paper, a new floating analog memristance simulator circuit based on second generation current conveyors and passive elements is proposed. Theoretical derivations are presented which decribe the circuit characteristics. The hardware of proposed simulator circuit is built using commercially available components. Theoretical derivations are validated with PSPICE simulation and experimental results. Performance of circuit was tested with simple example circuits. All results show that proposed simulator circuit provides frequency dependent pinched hysteresis loop and nonvolatility features. Exciting frequency, minimum and maximum memristance values and memristance range can be adjustable with simple passive element values. Simulator circuit has a frequency range of 1Hz to 40kHz.

49 citations


Journal ArticleDOI
TL;DR: An exhaustive analysis of a four-wing chaotic system is presented and it is proved that the evolution range of some variables can be modulated easily by one coefficient of a cross product term.
Abstract: An exhaustive analysis of a four-wing chaotic system is presented in this paper. It is proved that the evolution range of some variables can be modulated easily by one coefficient of a cross product term. An amplitude-adjustable chaotic circuit is designed, which shows a good agreement with the theoretical analysis. Also, in this paper a microcontroller-based random number generator (RNG) was designed with a nonlinear four-wing chaotic system. RNG studies of the current time have been usually carried out with complicated structures that are costly and difficult to use in real time implementations and that require so much energy consumption. On the other hand, in this paper, as opposed to the disadvantages mentioned here, a microcontroller-based RNG was designed with a four-wing chaotic system (also discussed in the paper) and this was introduced to literature. Microcontroller-based random numbers that passed randomness tests will be available for use in many fields in real life, particularly in encryption.

48 citations


Journal ArticleDOI
TL;DR: This paper explains how reconfigurable third-order FLF topology is used in order to approximate both FLPF and FHPF in concerned frequency band of interest.
Abstract: This paper presents design of electronically reconfigurable fractional-order filter that is able to be configured to operate as fractional-order low-pass filter (FLPF) or fractional-order high-pass filter (FHPF). Its slope of attenuation between pass band and stop band, i.e., order of the filter, is electronically adjustable in the range between 1 and 2. Also, pole frequency can be electronically controlled independently with respect to other tuned parameters. Moreover, particular type of approximation can be also controlled electronically. This feature set is available both for FLPF and FHPF-type of response. Presented structure of the filter is based on well-known follow-the-leader feedback (FLF) topology adjusted in our case for utilization with just simple active elements operational transconductance amplifiers (OTAs) and adjustable current amplifiers (ACAs), both providing possibility to control its key parameter electronically. This paper explains how reconfigurable third-order FLF topology is used in order to approximate both FLPF and FHPF in concerned frequency band of interest. Design is supported by PSpice simulations for three particular values of order of the filter (1.25, 1.5, 1.75), for several values of pole frequency and for two particular types of approximation forming the shape of both the magnitude and phase response. Moreover, theoretical presumptions are successfully confirmed by laboratory measurements with prepared prototype based on behavioral modeling.

48 citations


Journal ArticleDOI
TL;DR: The proposed hierarchical control scheme adds new control loop to control the reactive power reference by a fuzzy logic controller to have the benefit of increasing the system stability margins and moreover, eigenvalue, robustness and time delay analysis of proposed control scheme are presented.
Abstract: In this paper, the proposed hierarchical control scheme adds new control loop to control the reactive power reference by a fuzzy logic controller to have the benefit of increasing the system stability margins and moreover, eigenvalue, robustness and time delay analysis of proposed control scheme are presented. The reported droop-based control methods of VSI-based microgrids including hierarchical droop-based control scheme are limited to primary and secondary control levels while the proposed control scheme is completely analyzed so that the three hierarchical control levels modeled for both grid-connected mode and islanded mode. This scheme maintains the stability of microgrids not only for the small-signal events, but also for large-signal disturbances such as three phase and single phase to ground faults, heavy motor starting, etc. However, power sharing to loads and network is sufficiently done. To demonstrate the effectiveness of the proposed hierarchical controller, simulation studies have been performed on a microgrid consisting of four units of distributed generation with local loads and in presence of main grid using MATLAB/SIMULINK software and validated using OPAL RT real-time digital simulator.

40 citations


Journal ArticleDOI
TL;DR: This paper addresses the scheduling of fault-tolerant mixed-criticality systems to ensure the safety of tasks at different levels of criticalities in the presence of transient faults by adopting task re-execution as the fault-Tolerant technique.
Abstract: Integration of safety-critical tasks with different certification requirements onto a common hardware platform has become a growing tendency in the design of real-time and embedded systems. In the past decade, great efforts have been made to develop techniques for handling uncertainties in task worst-case execution time, quality-of-service, and schedulability of mixed-criticality systems. However, few works take fault-tolerance as a design requirement. In this paper, we address the scheduling of fault-tolerant mixed-criticality systems to ensure the safety of tasks at different levels of criticalities in the presence of transient faults. We adopt task re-execution as the fault-tolerant technique. Extensive simulations were performed to validate the effectiveness of our algorithm. Simulation results show that our algorithm results in up to 15.8% and 94.4% improvement in system reliability and schedule feasibility as compared to existing techniques, which contributes to a more safe system.

36 citations


Journal ArticleDOI
TL;DR: This paper presents an energy-efficient clustering algorithm based on fuzzy c-means algorithm and genetic fuzzy system (ECAFG) and by using FCM algorithm, the clusters are formed, and then cluster heads (CHs) are selected utilizing GFS.
Abstract: The energy efficiency in wireless sensor networks (WSNs) is a fundamental challenge. Cluster-based routing is an energy saving method in this type of networks. This paper presents an energy-efficient clustering algorithm based on fuzzy c-means algorithm and genetic fuzzy system (ECAFG). By using FCM algorithm, the clusters are formed, and then cluster heads (CHs) are selected utilizing GFS. The formed clusters will be remaining static but CHs are selected at the beginning of each round. FCM algorithm forms balanced clusters and distributes the consumed energy among them. Using static clusters also reduces the data overhead and consequently the energy consumption. In GFS, nodes energy, the distance from nodes to the base station and the distance from each node to its corresponding cluster center are considered as determining factors in CHs selection. Then, genetic algorithm is also used to obtain fuzzy if–then rules of GFS. Consequently, the system performance is improved and appropriate CHs can be selecte...

Journal ArticleDOI
TL;DR: The expressions presented are computationally simple and do not require inversion of denominator of the system transfer function unlike other techniques, and retain not only the time moments but also some Markov parameters of high-order interval system.
Abstract: In this paper, two expressions are derived for calculating the time moments and Markov parameters of continuous interval systems. The expressions presented are computationally simple and do not require inversion of denominator of the system transfer function unlike other techniques. The usefulness of expressions derived is shown with the help of Routh–Pade approximation of interval systems. The derived Routh–Pade approximants retain not only the time moments but also some Markov parameters of high-order interval system. Some improvement is also found in system approximation when these time moments/Markov parameters are used. One numerical example is included to illustrate the effectiveness and simplicity of proposed method.

Journal ArticleDOI
TL;DR: A new interleaved nonisolated bidirectional zero voltage switching (ZVS) dc–dc converter by using one three-windings coupled inductor is proposed and a comprehensive comparison between the proposed converter and conventional topologies is presented.
Abstract: In this paper, a new interleaved nonisolated bidirectional zero voltage switching (ZVS) dc–dc converter by using one three-windings coupled inductor is proposed. The proposed topology can provide high step-up and high step-down conversion ratios for boost and buck operations, respectively. Moreover, because of interleaving, the proposed converter has low input current ripple at low voltage side in both buck and boost operations. The proposed converter uses lower number of switches to have bidirectional power flow in comparison with other interleaved bidirectional converters. All used switches in the proposed converter are turned on under ZVS. The advantages of the proposed converter in comparison with the conventional interleaved converters are included in the capability of bidirectional power flow, ZVS operation for all switches and high step-up and high step-down voltage gain for boost and buck operations. In this paper, the proposed converter is analyzed completely and all equations of components are extracted as well as the ZVS conditions of all switches. Moreover, a comprehensive comparison between the proposed converter and conventional topologies is presented. To verify the accuracy performance of the proposed converter, the experimental results are given.

Journal ArticleDOI
TL;DR: This paper presents a novel inexact full adder based on carbon nanotube field-effect transistors (CNTFET) for approximate computations, which has soared in popularity especially for image processing applications and has the least relative error distance.
Abstract: This paper presents a novel inexact full adder based on carbon nanotube field-effect transistors (CNTFET) for approximate computations, which has soared in popularity especially for image processing applications. The proposed design generates the output carry without error. Therefore, the propagation of incorrect value to higher bit positions is avoided. It has the least relative error distance (Relative ED) compared to other approximate full adders reported in the literature. Practical simulations by using MATLAB demonstrate higher peak signal to noise ratio (PSNR) and image quality for motion detector image processing application. HSPICE simulations also confirm the efficiency of the proposed design. Moreover, area occupation is investigated by using electric tool. Power consumption, delay, area and ED are important evaluating factors in this subject. Comparisons are made by a comprehensive parameter (PDAEDP), based on which the new design has 23.8%, 41.5%, 70.5%, 78% and 83.6% higher performance than TGA1, TGA2, AXA1, AXA2 and AXA3, respectively.

Journal ArticleDOI
TL;DR: Some simple but effective design rules are emphasized to solve the problem of compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits.
Abstract: Despite its important existing challenges, quantum-dot cellular automata (QCA) is one of the promising replacement candidates of the traditional VLSI technology. Practical implementation issues such as fault tolerance and lack of customized CAD tools and algorithms for automatic synthesis of large complex systems are some important instances of QCA circuit design challenges. Currently, most of the research papers focus only on development of individually efficient QCA gates and circuits in terms of only their physical properties such as area and delay. However, throughout this paper, it is demonstrated that these compressed and fast individual QCA gates and circuits cause serious concerns when they are exploited as building blocks in modular design of higher level complex circuits. Some simple but effective design rules are then emphasized to solve this problem by preserving the “modular design efficiency” of the developed underlying QCA gates and circuits. As a case study, two new instances of fault-tole...

Journal ArticleDOI
TL;DR: Simulation results show that the AGPSO classifier provides better performance in terms of convergence speed, entrapment in local minima and classification accuracy compared to the other algorithms.
Abstract: Feed-Forward Neural Networks (FFNNs), as one of the wide-spreading Artificial NNs, has been used to solve many practical problems such as classification of the sonar dataset. Improper selection of the training method, which is an important part of the design process, results in slow convergence rate, entrapment in local minima, and sensitivity to initial conditions. To overcome these issues, the recently proposed method known as “Particle Swarm Optimizer with Autonomous Groups (AGPSO)” has been used in this paper. It is known that the FNNs are very sensitive to the problem’s dimension, so clearly applying it to a dataset with large dimension results in poor performance. However, the combination of FNN and AGPSO solves this problem because of the ability of AGPSO in the optimization of high dimension problems. To evaluate the performance of the proposed classifier, it is applied to other datasets and the results are compared to the standard PSO, modified PSO (IPSO), Gravitational Search Algorithm (GSA) and Gray Wolf Optimizer (GWO). Simulation results show that the AGPSO classifier provides better performance in terms of convergence speed, entrapment in local minima and classification accuracy compared to the other algorithms.

Journal ArticleDOI
TL;DR: Two structures of fractional band- pass filters are presented: one as an analog of classical second-order filter, and one arising from parallel connection of two fractional low-pass filters.
Abstract: Fractional band-pass filters are a promising area in the signal processing. They are especially attractive as a method for processing of biomedical signals, such as EEG, where large signal distortion is undesired. We present two structures of fractional band-pass filters: one as an analog of classical second-order filter, and one arising from parallel connection of two fractional low-pass filters. We discuss a method for filter implementation — Laguerre Impulse Response Approximation (LIRA) — along with sufficient conditions for when the filter can be realized with it. We then discuss methods of filter tuning, in particular we present some analytical results along with optimization algorithm for numerical tuning. Filters are implemented and tested with EEG signals. We discuss the results highlighting the possible limitations and potential for development.

Journal ArticleDOI
TL;DR: This review paper describes different lumped circuitry realizations of the chaotic dynamical systems having equilibrium degeneration into a plane object with topological dimension of the equilibria of these systems.
Abstract: This review paper describes different lumped circuitry realizations of the chaotic dynamical systems having equilibrium degeneration into a plane object with topological dimension of the equilibriu...

Journal ArticleDOI
TL;DR: Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps that cause damages in circuit function.
Abstract: Hardware Trojan Horses (HTHs) are malicious modifications inserted in Integrated Circuit during fabrication steps. The HTHs are very small and can cause damages in circuit function. They cannot be ...

Journal ArticleDOI
TL;DR: The critical inductance relation between CCM and DCM is obtained and the validity of the presented theoretical issues is reconfirmed by using simulation results obtained from PSCAD/EMTDC software.
Abstract: In this paper, a new structure of nonisolated boost DC–DC converters is proposed. The operation of the proposed structure in continuous conduction mode (CCM) and discontinuous conduction mode (DCM) is presented. Then, the critical inductance relation between CCM and DCM is obtained. The voltage gain and current stress of switches are calculated. Finally, the validity of the presented theoretical issues is reconfirmed by using simulation results obtained from PSCAD/EMTDC software.

Journal ArticleDOI
TL;DR: The proposed FD-OTA with rail-to-rail linear input range operating in weak inversion region with fully differential class AB input and output structures has ensured increased gain, GBW, slew rates and output swings with reduced nonlinearity and common mode substrate noise.
Abstract: This paper presents a single-stage ultra-low-power fully differential operational transconductance amplifier (FD-OTA) with rail-to-rail linear input range operating in weak inversion region. The input core of the OTA is comprised of source degenerated, flipped voltage follower (FVF)-based bulk-driven class AB input pair, into which a regenerative feedback loop has been inserted to boost its bulk transconductance (gmb). The proposed FD-OTA has utilized self-cascode current mirror (SC-CM) loads, which increase its open loop gain from nominal intrinsic value of 42dB to 70.4dB. It has provided 9.24kHz gain bandwidth (GBW), consuming 64nW of quiescent power from a 0.51V single power supply at 15pF load. The proposed OTA in unity gain configuration has ensured reduced total harmonic distortion (THD) of −52.4dB at 200Hz frequency and 1Vp-p signal swing. Its fully differential class AB input and output structures have ensured increased gain, GBW, slew rates and output swings with reduced nonlinearity and common mode substrate noise. The Cadence Virtuoso environment using GPDK 180nm standard n-well CMOS process technology has been used to simulate the proposed circuit.

Journal ArticleDOI
TL;DR: The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1- bit FA circuits reported till date.
Abstract: A novel “16 transistor” (16T) 1-bit Full adder (FA) circuit based on CMOS transmission-gate (TG) and pass transistor logics (PTL) is presented. This 1-bit FA circuit with TG and PTL structure is derived based on carry dependent sum implementation approach. The design metrics (DMs) such as power, delay, power-delay-product (PDP), and transistor-count (TC) for this 1-bit FA are compared against eight other standard and state-of-the-art 1-bit FA circuits reported till date. All the comparisons are done at post layout level with respect to the DMs under consideration. The proposed 1-bit FA dissipates an average power of 2.118μW, with a delay of 606 ps, with an area of 33.1μm2, resulting in a PDP of 1.28 fJ. This power and hence the PDP is the lowest of all, ever reported till date. In this comparative study a common test bench with a supply voltage VDD=1.2V, input signal frequency fin=200MHz is used. This 1-bit FA is designed and implemented using Cadences' 90nm “generic-process-design-kit” (GPDK).

Journal ArticleDOI
TL;DR: This study contributes to this area of research by providing a detailed review of the available options and problems to allow other researchers and participants to further develop skin cancer apps, and the new directions of this research were described.
Abstract: Objective: This research aims to survey the efforts of researchers in response to the new and disruptive technology of skin cancer apps, map the research landscape from the literature onto coherent...

Journal ArticleDOI
TL;DR: The CMOS beta multiplier circuit is exploited to synthesize a temperature-independent voltage reference suitable for low voltage and ultra-low power biomedical applications and uses only MOS transistors to generate Proportional To Absolute Temperature (PTAT) and Complimentary To Absolute temperature (CTAT) currents.
Abstract: This paper exploits the CMOS beta multiplier circuit to synthesize a temperature-independent voltage reference suitable for low voltage and ultra-low power biomedical applications. The technique presented here uses only MOS transistors to generate Proportional To Absolute Temperature (PTAT) and Complimentary To Absolute Temperature (CTAT) currents. A self-biasing technique has been used to minimize the temperature and power supply dependency. A prototype in 65nm CMOS has been developed and occupies 0.0039mm2, and at room temperature, it generates a 204mV reference voltage with 1.3mV drift over a wide temperature range (from −40∘C to 125∘C). This has been designed to operate with a power supply voltage down to 0.6V and consumes 1.8uA current from the supply. The simulated temperature coefficient is 40ppm/∘C.

Journal ArticleDOI
TL;DR: A dynamic data guarantee and data confidentiality scheme for public auditing in cloud storage service is proposed and bilinear pairing can achieve the most efficient way to verify data correctness and batch auditing.
Abstract: Recently, storage as a service of cloud computing becomes a new trend to access or share files. Once files are stored in cloud, owner can access files seamlessly by personal computer or mobile device. However, owner may worry about confidentiality and integrity of owner's files stored in cloud because cloud service providers are not always trustworthy. Therefore, there are many kinds of data correctness verification methods proposed to prevent cloud service providers from cheating data owners. Among these models for auditing, bilinear pairing can achieve the most efficient way to verify data correctness and batch auditing. Although auditing methods can ensure whether data is stored properly, it is not considered that the data may be a secret data or a data owner does not want to be known by both auditors and cloud service providers. Another important issue is providing dynamic data of auditing in cloud. Wang et al.13 proposed a scheme that can provide public auditing and dynamic data, but it still cannot guarantee whether cloud has updated data honestly. For this reason, we propose a dynamic data guarantee and data confidentiality scheme for public auditing in cloud storage service.

Journal ArticleDOI
TL;DR: Several artificial neural cells were designed and implemented to form a library of neurons for rapid realization of ANNs on FPGA-based embedded systems that contains a total of 60 different neurons, two-, four- and six-input biased and non-biased, with each having 10 different activation functions.
Abstract: Artificial neural networks (ANNs) are implemented in hardware when software implementations are inadequate in terms of performance. Implementing an ANN as hardware without using design automation tools is a time consuming process. On the other hand, this process can be automated using pre-designed neurons. Thus, in this work, several artificial neural cells were designed and implemented to form a library of neurons for rapid realization of ANNs on FPGA-based embedded systems. The library contains a total of 60 different neurons, two-, four- and six-input biased and non-biased, with each having 10 different activation functions. The neurons are highly pipelined and were designed to be connected to each other like Lego pieces. Chip statistics of the neurons showed that depending on the type of the neuron, about 25 selected neurons can be fit in to the smallest Virtex-6 chip and an ANN formed using the neurons can be clocked up to 576.89MHz. ANN based Rossler system was constructed to show the effectiveness ...

Journal ArticleDOI
TL;DR: An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed, based on decomposition of the full adders logic into the smaller modules, which exhibits excellent signal integrity and driving capability when operated at low voltages.
Abstract: An energy efficient internal logic approach for designing two 1-bit full adder cells is proposed in this work. It is based on decomposition of the full adder logic into the smaller modules. Low power, high speed and smaller area are the main features of the proposed approach. A modified power aware NAND gate, an essential entity, is also presented. The proposed full adder cells achieve 30.13% and improvement in their power delay product (PDP) metrics when compared with the best reported full adder design. Some of the popular adders and proposed adders are designed with cadence virtuoso tool with UMC 90nm technology operating at 1.2V supply voltage and UMC 55nm CMOS technology operating at 1.0V. These designs are tested on a common environment. During the experiment, it is also found that the proposed adder cells exhibit excellent signal integrity and driving capability when operated at low voltages.

Journal ArticleDOI
TL;DR: A comparison study between the DTC with an SVM (D TC-SVM) based on the Proportional Integral regulators (DTC-S VM-PI) and the D TC- SVM based onThe sliding mode controllers (SVM-SMC), and the implementation on the Field Programmable Gate Array (FPGA), due to the parallel processing capability of the FPGAs.
Abstract: The conventional direct torque control (DTC), based on the hysteresis controllers and the switching table, operates with a variable switching frequency, which decreases the conventional DTC performances, like the torque and flux ripples. Thus, the space vector modulation (SVM), used in the DTC, ensures a constant switching frequency and improves the DTC performances. The first aim of this paper is to present a comparison study between the DTC with an SVM (DTC-SVM) based on the Proportional Integral regulators (DTC-SVM-PI) and the DTC-SVM based on the sliding mode controllers (DTC-SVM-SMC). These two approaches are complex control algorithms which require faster micro-controllers; therefore the second objective of this paper is to present the implementation of the DTC-SVM-PI and the DTC-SVM-SMC on the Field Programmable Gate Array (FPGA), due to the parallel processing capability of the FPGAs. The two approaches are designed and simulated using the Xilinx System Generator (XSG) and implemented using an FPGA Virtex 5. The simulation results in the transient behavior and the steady state of the induction motor controlled by these two approaches are compared and discussed. The hardware FPGA implementation results show the effectiveness of the FPGA relative to the digital signal processor in terms of execution time.

Journal ArticleDOI
TL;DR: A simple circuit for the realization of two digital modulation schemes: BPSK and ASK simultaneously, with the advantage of high input impedance at the signal input nodes and use of grounded resistors is presented.
Abstract: The paper presents a simple circuit for the realization of two digital modulation schemes: BPSK and ASK simultaneously, with the advantage of high input impedance at the signal input nodes and use of grounded resistors. The new circuits are based on the use of extra-X current conveyor. Detailed analysis is given and circuit verification is carried out through simulations with a supply voltage of ±1.25V and 0.25μm CMOS parameters to support the proposed circuit. Nonideal study is also given. An extended application of the circuit in realizing precision half-wave and full-wave rectifiers is further proposed by incorporating a simple modification to the proposed topology. The new proposed CMOS compatible electronic circuits enrich the utility of extra-X current conveyor for realizing diverse electronic functions.

Journal ArticleDOI
TL;DR: A cardiac arrhythmia classification scheme that performs classification task directly in the compressed domain, skipping the reconstruction stage is proposed.
Abstract: Due to the capacity of processing signal with low energy consumption, compressive sensing (CS) has been widely used in wearable health monitoring system for arrhythmia classification of electrocardiogram (ECG) signals. However, most existing works focus on compressive sensing reconstruction, in other words, the ECG signals must be reconstructed before use. Hence, these methods have high computational complexity. In this paper, the authors propose a cardiac arrhythmia classification scheme that performs classification task directly in the compressed domain, skipping the reconstruction stage. The proposed scheme first employs the Pan–Tompkins algorithm to preprocess the ECG signals, including denoising and QRS detection, and then compresses the ECG signals by CS to obtain the compressive measurements. The features are extracted directly from these measurements based on principal component analysis (PCA), and are used to classify the ECG signals into different types by the proposed semi-supervised learning a...