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Showing papers in "Journal of Computational Electronics in 2016"


Journal ArticleDOI
TL;DR: This paper presents a novel two-input Exclusive-OR gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs and simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements.
Abstract: Numerous scientific and fundamental hindrances have resulted in a slow down of silicon technology and opened new possibilities for emerging research devices and structures. The need has arisen to expedite new methods to interface these nanostructures for computing applications. Quantum-dot Cellular Automata (QCA) is one of such computing paradigm and means of encoding binary information. QCA computing offers potential advantages of ultra-low power dissipation, improved speed and highly density structures. This paper presents a novel two-input Exclusive-OR (XOR) gate implementation in quantum-dot cellular automata nanotechnology with minimum area and power dissipation as compared to previous designs. The proposed novel QCA based XOR structure uses only 28 QCA cells with an area of $$0.02\,\upmu \hbox {m}^{2}$$0.02μm2 and latency of 0.75 clock cycles. Also the proposed novel XOR gate is implemented in single layer without using any coplanar and multi-layer cross-over wiring facilitating highly robust and dense QCA circuit implementations. To investigate the efficacy of our proposed design in complex array of QCA structures, 4, 8, 16 and 32-bit even parity generator circuits were implemented. The proposed 4-bit even parity design occupies 9 and 50 % less area and has 12.5 and 22.22 % less latency as compared to previous designs. The 32-bit even parity design occupies 22 % less area than the best reported previous design. The proposed novel XOR structure has 28 % less switching energy dissipation, 10 % less average leakage energy dissipation and 19 % less average energy dissipation than best reported design. The simulation results verified that the proposed design offers significant improvements in terms of area, latency, energy dissipation and structural implementation requirements. All designs have been functionally verified in the QCADesigner tool for GaAs/AlGaAs heterostructure based semiconductor implementations. The energy dissipation results have been computed using an accurate QCAPro tool.

83 citations


Journal ArticleDOI
TL;DR: In this paper, dual electrode doping-less TFET (DEDLTFET) was proposed to enhance the ON state current and Analog performances, where electrodes on top and bottom of source and drain are considered to enhance ON state currents and analog performances.
Abstract: In this paper, we have proposed a device and named it dual electrode doping-less TFET (DEDLTFET), in which electrodes on top and bottom of source and drain are considered to enhance the ON state current and Analog performances. The charge plasma technique is used to generate electron's and hole's clouding depending upon their respective work functions at top and bottom of source/drain electrode. Band-to-band-tunneling rate is similar on both sides of source-channel junctions, which increases ON state current. The analog performance parameters of DEDLTFET are investigated and using device simulation the demonstrated characteristics are compared with doping-less (DLTFET) and the conventional doped double gate TFET (DGTFET), such as transconductance $$(\hbox {g}_\mathrm{m})$$(gm), transconductance to drain current ratio $$(\hbox {g}_\mathrm{m}/\hbox {I}_\mathrm{D})$$(gm/ID), output-conductance (g$$_{d})$$d), output resistance $$(\hbox {r}_\mathrm{d})$$(rd), early voltage $$(\hbox {V}_\mathrm{EA})$$(VEA), intrinsic gain $$(\hbox {A}_\mathrm{V})$$(AV), total gate capacitance $$(\hbox {C}_\mathrm{gg})$$(Cgg) and unity gain frequency $$(\hbox {f}_\mathrm{T})$$(fT). From the simulation results, it is observed that DEDLTFET has significantly improved analog performance as compared to DGTFET and DLTFET.

65 citations


Journal ArticleDOI
TL;DR: The simulation results demonstrate that the proposed QCA multiplexer architectures have the best performance in terms of clock delay, circuit complexity, and area in comparison with other QCAmultiplexing architectures.
Abstract: The quantum-dot cellular automata (QCA) technology is a promising alternative technology to CMOS technology to extend the exponential Moore's law progress of microelectronics at nanoscale level, which is expected to be beneficial for digital circuits. This paper presents and evaluates three multiplexer architectures: a new and efficient 2:1 multiplexer architecture, a 4:1 multiplexer architecture, and 8:1 multiplexer architecture in the QCA technology. The 4:1 and 8:1 QCA multiplexer architectures are proposed based on the 2:1 QCA multiplexer. The proposed architectures are implemented with the coplanar crossover approach. These architectures are simulated using the QCADesigner tool version 2.0.1. The 2:1, 4:1, and 8:1 QCA multiplexer architectures utilize 15, 107, and 293 cells, respectively. The simulation results demonstrate that the proposed QCA multiplexer architectures have the best performance in terms of clock delay, circuit complexity, and area in comparison with other QCA multiplexer architectures.

64 citations


Journal ArticleDOI
TL;DR: In this paper, the authors review two of the most promising avenues to increase the power factor, namely modulation doping and electron energy filtering, and present a computational framework for analysis of these mechanisms for two example cases: low-dimensional gated Si nanowires (electrostatically achieved doping), and superlattices (energy filtering over potential barriers).
Abstract: Thermoelectric (TE) materials have undergone revolutionary progress over the last 20 years. The thermoelectric figure of merit ZT, which quantifies the ability of a material to convert heat into electricity has more than doubled compared to traditional values of $$ZT\sim 1$$ZT~1, reaching values even beyond $$ZT\sim 2$$ZT~2 in some instances. These improvements are mostly attributed to drastic reductions of the thermal conductivity in nanostructured materials and nanocomposites. However, as thermal conductivities in these structures approach the amorphous limit, any further benefits to ZT must be achieved through the improvement of the thermoelectric power factor. In this work we review two of the most promising avenues to increase the power factor, namely (i) modulation doping and (ii) electron energy filtering, and present a computational framework for analysis of these mechanisms for two example cases: low-dimensional gated Si nanowires (electrostatically achieved doping), and superlattices (energy filtering over potential barriers). In the first case, we show that a material with high charge density, but free of ionized impurities, can provide up to a five-fold thermoelectric power factors increase compared to the power factor of the doped material, which highlights the benefits of modulation doping, or gating of materials. In the second case, we show that optimized construction of energy barriers within a superlattice material geometry can improve the power factor by up to $$\sim 30\,\%$$~30%. This paper is intended to be a review of our main findings with regards to efforts to improve the thermoelectric power factor through modulation doping and energy filtering.

45 citations


Journal ArticleDOI
TL;DR: In this article, an equilateral triangular patch antenna has been designed using graphene as the patch conductor and the antenna absorption cross section variations due to tunable surface conductivity owing to applied bias voltages is also analyzed.
Abstract: Design of antennas in terahertz regime demands for efficient design methodologies as miniaturization limits the performance in terms of higher geometric uncertainty, improper characterization of the antenna leading to fabrication difficulties. New material such as graphene having a number of desirable electromagnetic and mechanical properties can play a significant role in overcoming the limitations for miniature antenna using a well defined shape of antenna while maintaining the key antenna parameters like return loss, gain, directivity, VSWR, radiation pattern and radiation efficiency. The equilateral triangular patch antenna has been designed here using graphene as the patch conductor. The design procedure presented in this paper incorporates the electrical and non-electrical properties of graphene for initializing the tunable conductivity which is further coupled to electromagnetic simulator for analyzing the radiation properties of the graphene antenna. The mathematical modeling of the antenna is performed using ANSYS Maxwell and high frequency simulation software. The tunable characteristics of the antenna are validated from return loss and radiation plots. Sufficient radiation efficiency is achieved at resonant frequencies in the range 1---3 THz. The antenna absorption cross section variations due to tunable surface conductivity owing to applied bias voltages is also analyzed.

36 citations


Journal ArticleDOI
TL;DR: In this article, a double-gate junctionless FETs (DG-JLFETs) structure incorporating dielectric pockets (DPs) at the source and drain ends is reported.
Abstract: In this paper, we report the TCAD based simulation of a new double-gate junctionless FETs (DG-JLFETs) structure incorporating dielectric pockets (DPs) at the source and drain ends. The proposed structure not only improves the ON to OFF drain current ratio (by $${\sim }$$~900 %), subthreshold swing characteristics (by $${\sim }$$~12 %) and Drain Induced Barrier Lowering (DIBL) (by $${\sim }$$~56 %) over the conventional DG-JLFETs (i.e. without DPs), but also provides additional flexibility of performance optimization of the device by changing the length and thickness of the DPs. Since only little work has been carried out on the performance optimization of the JLFETs, the present work is believed to be very useful for designing the low-power VLSI circuits using DP-DG JLFETs with improved performance.

35 citations


Journal ArticleDOI
TL;DR: This work targets a new robust QCA tile structure hybridizing rotated and non-rotated cell together resulting lesser kink energy and suggests that the proposed QCA logic primitives have achieved high fault tolerance of 97.43 %.
Abstract: The increasing fabrication cost of CMOS-based computing devices and the ever-approaching limits of their fabrication have led to the search for feasible options with high device density and low power waste. Quantum-dot cellular automata (QCA) is an emerging technology with such potential to match the design target beyond the limits of state-of-the-art CMOS. But nanotechnologies, like QCA are extremely susceptible to various forms of flaws and variations during fabrication at nano scale. Thus, the exploration of ingenious fault tolerant structure around QCA is gaining high importance. This work targets a new robust QCA tile structure hybridizing rotated and non-rotated cell together resulting lesser kink energy. Different QCA logic primitives (majority/minority logic, fanout tiles, etc.) are made using such hybrid cell structure. The functional characterization using the kink energy and the polarization level of such QCA structures under different cell defects have been thoroughly investigated. The results suggest that the proposed QCA logic primitives have achieved high fault tolerance of 97.43 %. Also, 100 % fault tolerance can be ascertained if the proposed logic circuit drives the correct output with the application of $$\langle $$?001, 011$$\rangle $$? as a primitive test vector only. A comparative performance of the proposed logic over existing structure makes it more reliable.

35 citations


Journal ArticleDOI
TL;DR: A novel 5-input majority gate for QCA is proposed in this paper which is suitable for designing QCA circuits in a simple and symmetric manner and simulation results and physical proofs confirm the usefulness of the proposed gate design for designing any digital circuit.
Abstract: In a very fast growth of very large scale integration (VLSI) technology, it is the demand and necessity of time to achieve a reliable design with low power consumption. The quantum dot cellular automata (QCA), due to its small size, very high switching speed and ultra-low power consumption, can be an alternative for CMOS VLSI technology at nano-scale level. A novel 5-input majority gate for QCA is proposed in this paper which is suitable for designing QCA circuits in a simple and symmetric manner. Based on it, we have designed a full adder with some physical proofs provided for the functions of Boolean techniques to verify the functionality of the proposed devices properly. For computer simulations analysis, functionality of full adder has been checked using the QCADesigner tool. Both simulation results and physical proofs confirm the usefulness of our proposed gate design for designing any digital circuit.

32 citations


Journal ArticleDOI
TL;DR: In this paper, a double gate tunneling field effect transistor (WFEDG TFET) was proposed, which incorporated the innovative concept of work function engineering by continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction into a DG TFET, thereby presenting a new device structure, a work function engineered double gate TFET.
Abstract: The ongoing trend of device dimension miniaturization is attributed to a large extent by the development of several non-conventional device structures among which tunneling field effect transistors (TFETs) have attracted significant research attention due to its inherent characteristics of carrier conduction by built-in tunneling mechanism which in turn mitigates various short channel effects (SCEs). In this work, we have, incorporated the innovative concept of work function engineering by continuously varying the mole fraction in a binary metal alloy gate electrode along the horizontal direction into a double gate tunneling field effect transistor (DG TFET), thereby presenting a new device structure, a work function engineered double gate tunneling field effect transistor (WFEDG TFET). We have presented an explicit analytical surface potential modeling of the proposed WFEDG TFET by the solving the 2-D Poisson's equation. From the surface potential expression, the electric field has been derived which has been utilized to formulate the expression of drain current by performing rigorous integration on the band-to-band tunneling generation rate over the tunneling region. Based on this analytical modeling, an overall performance comparison of our proposed WFEDG TFET with its normal DG TFET counterpart has been presented in this work to establish the superiority of our proposed structure in terms of surface potential and drain current characteristics. Analytical results have been compared with SILVACO ATLAS device simulator results to validate our present model.

32 citations


Journal ArticleDOI
TL;DR: In this paper, a dual protruded silicon dioxide in the drift region of LDMOS (DP-LDMOS) is proposed which creates new peaks in the electric field profile and an improvement of the breakdown voltage.
Abstract: Breakdown voltage and specific on-resistance are two important parameters in lateral double diffused MOSFET (LDMOS) devices. In order to have a high breakdown voltage, the electric field profile should be uniform. In this paper a dual protruded silicon dioxide in the drift region of LDMOS (DP-LDMOS) is proposed which creates new peaks in the electric field profile and an improvement of the breakdown voltage. Also, a triple P window is considered between these protruded oxides to have the balanced charge in the drift region that helps to have a higher breakdown voltage than a conventional LDMOS transistor. The simulation with two-dimensional ATLAS simulator shows that the proposed DP-LDMOS structure has a low specific on-resistance due to incorporating the protruded oxides in the drift region.

32 citations


Journal ArticleDOI
TL;DR: In this article, the authors investigate perovskite planar heterojunction solar cells using 2D physics-based TCAD simulation and show that in order to achieve high efficiency, the mobility of the hole transport layer should exceed 10-4cm2/V s.
Abstract: In this paper, we investigate perovskite planar heterojunction solar cells using 2D physics-based TCAD simulation. The perovskite cell is modeled as an inorganic material with physics-based parameters. A planar structure consisting of $$\hbox {TiO}_{2}$$TiO2 as the electron transport material (ETM), $$\hbox {CH}_{3}\hbox {NH}_{3}\hbox {PbI}_3{}_{-\mathrm{x}}\hbox {Cl}_\mathrm{x}$$CH3NH3PbI3-xClx as the absorber layer, and Spiro-OmeTAD as the hole transport material (HTM) is simulated. The simulated results match published experimental results indicating the accuracy of the physics-based model. Using this model, the effect of the hole mobility and electron affinity/band gap of the hole transport layer (HTM) is investigated. The results show that in order to achieve high efficiency, the mobility of the HTM layer should exceed $$10^{-4}\hbox {cm}^{2}/\hbox {V s}$$10-4cm2/V s. In addition, reducing the band offset to match the valance band of the perovskite results in achieving the highest efficiency. Moreover, the results are discussed in terms of charge transport in the HTM layer and the band alignment at the HTM/perovskite interface.

Journal ArticleDOI
TL;DR: In this paper, an all-optical universal shift register using silicon waveguide microring resonators (MRRs) to form a nonlinear alloptical switch is proposed and described.
Abstract: An all-optical universal shift register using silicon waveguide microring resonators (MRRs) to form a nonlinear all-optical switch is proposed and described. Such devices can be used as building blocks for optical computing and information processing systems. The proposed device comprises two optical multiplexers and two optical D flip-flops. Each optical D flip-flop consists of a single microring resonator, sharing the same clock pulse. Each multiplexer consists of two microring resonators controlled by optical pump pulses to perform bidirectional shifting and parallel in/parallel out operations on optical signals. Numerical simulation results confirming the described approach are presented. Based on the numerical simulation results, we specify a combination of feasible MRR radius and detuning which enables analysis of system performance parameters for the scheme such as the maximum amplitude difference between marks, between spaces, and between marks and spaces.

Journal ArticleDOI
TL;DR: In this article, the encapsulation of small fullerenes into graphyne nanotubes was studied to investigate the possibility of band gap engineering in these nanotsubes using density functional theory.
Abstract: The encapsulation of small fullerenes into graphyne nanotubes was studied to investigate the possibility of band gap engineering in these nanotubes. The electronic properties of zigzag (4,0) and (5,0) graphyne nanotubes filled with small $$\hbox {C}_{20}$$C20 and $$\hbox {C}_{30}$$C30 fullerenes were studied using density functional theory. It was found that the zigzag (4,0) and (5,0) graphyne nanotubes were semiconductors. These graphyne nanotubes filled with $$\hbox {C}_{20}$$C20 and $$\hbox {C}_{30}$$C30 fullerenes were shown p-type and n-type semiconducting properties, respectively. The energy band gap was dependent on the number of the encapsulated fullerenes. Our results demonstrated the ability of band gap engineering through the encapsulation of small fullerenes into graphyne nanotubes.

Journal ArticleDOI
TL;DR: This work designs a new fault-tolerant QCA majority gate based on a $$3\times 5$$3×5 tile that guarantees good fault tolerance under single cell and double cell missing defects compared with several previous structures.
Abstract: Due to its ultrasmall size and extremely low power consumption, quantum-dot cellular automata (QCA) technology represents a promising alternative to semiconductor transistors at the nanoscale. Nevertheless, the design of QCA circuits is limited by their high defect rate during fabrication, making fault-tolerant QCA structures a popular research topic. The aim of this work is to design a new fault-tolerant QCA majority gate based on a $$3\times 5$$3×5 tile. The majority gate guarantees good fault tolerance under single cell and double cell missing defects compared with several previous structures. The functional results when adopting the polarization and kink energy of the proposed majority gate under such single cell and double cell deposition defects are fully investigated. Besides, a series of new fault-tolerant adders are implemented based on the fault-tolerant majority gates. To evaluate the performance of the proposed adders, a thorough comparison versus previous adders with respect to fault tolerance, cell number, area, and delay is carried out. The results indicate that the proposed design can reach a high level of fault tolerance, and perform rather well in terms of other properties. For simulation analysis, the QCADesigner tool is used to check the functionality of all circuits.

Journal ArticleDOI
TL;DR: In this article, a new kind of multi-band metamaterial absorber based on the concentric ring resonators is engineered to be used in various microwave applications including energy harvesting, which almost perfectly absorbs the electromagnetic wave with polarization angle independency at multiple resonant frequencies in the microwave range.
Abstract: A new kind of multi-band metamaterial absorber based on the concentric ring resonators is engineered to be used in various microwave applications including energy harvesting. Numerical investigations are carried out step by step for observation of the effect of each ring resonator. The results reveal that the structure almost perfectly absorbs the electromagnetic wave with polarization angle independency at multiple resonant frequencies in the microwave range. Additionally, the structure is characterized according to the dimension and geometry variations. For the harvesting application, three different efficiencies are suggested, discussed, and calculated in terms of their contribution to the conditional realization of the connection between the absorption characteristics of the material and its energy harvesting functionality. Also the multi-band absorption characteristics of no-load conditions are presented and compared with the loading conditions through the energy harvesting. As a result, 50 % of the incoming wave energy whose correspondence is 0.25 W is converted to real power through the resistive loads at 5.88 GHz.

Journal ArticleDOI
TL;DR: In this paper, a new analytical model for the gate threshold voltage of a dual-material double-gate (DMDG) tunnel field effect transistor (TFET) was derived by solving the quasi-two-dimensional Poisson's equation in the lightly doped Si film.
Abstract: A new analytical model for the gate threshold voltage ($$V_\mathrm{TG}$$VTG) of a dual-material double-gate (DMDG) tunnel field-effect transistor (TFET) is reported. The model is derived by solving the quasi-two-dimensional Poisson's equation in the lightly doped Si film and employing the physical definition of $$V_\mathrm{TG}$$VTG. A numerical simulation study of the transfer characteristics and $$V_\mathrm{TG}$$VTG of a DMDG TFET has been carried out to verify the proposed analytical model. In the numerical calculations, extraction of $$V_\mathrm{TG}$$VTG is performed based on the transconductance change method as already used for conventional metal---oxide---semiconductor FETs (MOSFETs). The effects of gate length scaling, Si film thickness scaling, and modification of the gate dielectric on $$V_\mathrm{TG}$$VTG are reported. The dependence of $$V_\mathrm{TG}$$VTG on the applied drain bias is investigated using the proposed model. The proposed model can predict the effect of variation of all these parameters with reasonable accuracy.

Journal ArticleDOI
TL;DR: In this article, a novel graphene nanoribbon transistor with electrically induced junction for source and drain regions is proposed, where two parts of same metal are implemented at both sides of the main gate region.
Abstract: In this paper a novel graphene nanoribbon transistor with electrically induced junction for source and drain regions is proposed. An auxiliary junction is used to form electrically induced source and drain regions beside the main regions. Two parts of same metal are implemented at both sides of the main gate region. These metals which act as side gates are connected to each other to form auxiliary junction. A fixed voltage is applied on this junction during voltage variation on other junctions. Side metals have smaller workfunction than the middle one. Tight-binding Hamiltonian and nonequilibrium Green's function formalism are used to perform atomic scale electronic transport simulation. Due to the difference in metals workfunction, additional gates create two steps in potential profile. These steps increase horizontal distance between conduction and valance bands at gate to drain/source junction and consequently lower band to band tunneling probability. Current ratio and subthreshold swing improved at different channel lengths. Furthermore, device reliability is improved where electric field at drain side of the channel is reduced. This means improvement in leakage current, hot electron effect behavior and breakdown voltage. Application to multi-input logic gates shows higher speed and smaller power delay product in comparison with conventional platform.

Journal ArticleDOI
TL;DR: In this paper, the impact of interlayer resistance due to c-axis resistivity and contact resistance on performance in terms of delay, power dissipation and power delay product (PDP) of Multi-layer graphene nanoribbon (MLGNR) interconnect is discussed.
Abstract: This paper addresses the impact of interlayer resistance due to c-axis resistivity and contact resistance on performance in terms of delay, power dissipation and power delay product (PDP) of Multi-layer graphene nanoribbon (MLGNR) interconnect. The impact of model parameter i.e. Fermi energy $$(\hbox {E}_\mathrm{F})$$(EF) on performance of MLGNR is also discussed. A similar analysis is performed for copper interconnect and results are compared with MLGNR at 22 nm technology node. The impact of interlayer resistance on equivalent resistance of MLGNR is critically analyzed. Inductive and capacitive coupling between the adjacent layers are included in this analysis. It is found that the MLGNR with interlayer resistance, compared to copper, gives better performance in terms of delay, power dissipation and PDP with higher value of Fermi energy for semi global to global lengths of interconnect (300---1000 $$\upmu \hbox {m})$$μm) whereas reverse is true for local lengths 100---200 $$(\upmu \hbox {m})$$(μm). In addition, performance gap between MLGNR with and without interlayer resistance decreases with increase in Fermi energy.

Journal ArticleDOI
J. Ajayan1, D. Nirmal1
TL;DR: In this paper, the RF and DC behaviors of a SiN-passivated 20-nm gate length metamorphic high electron mobility transistor (MHEMT) on GaAs substrate with Δ-doped sheets on either side of the composite channel are studied using the Synopsys TCAD tool.
Abstract: In this paper, the RF and DC behaviours of a SiN-passivated 20-nm gate length metamorphic high electron mobility transistor (MHEMT) on GaAs substrate with $${\updelta }$$ź-doped sheets on either side of the composite channel are studied using the Synopsys TCAD tool. The 20-nm enhancement-mode MHEMT with $${\updelta }$$ź-doped sheets on either side of the $$\hbox {In}_{0.75}\hbox {Ga}_{0.25}\hbox {As}$$In0.75Ga0.25As/InAs/ $$\hbox {In}_{0.75}\hbox {Ga}_{0.25}\hbox {As}$$In0.75Ga0.25As multilayer channel shows a transconductance of 3000 mS/mm, cut-off frequency ($${f}_{\mathrm{T}}$$fT) of 760 GHz and a maximum-oscillation frequency ($${f}_{\mathrm{max}}$$fmax) of 1270 GHz. The threshold voltage of the device is found to be 0.07 V. The room-temperature Hall mobilities of the two-dimensional sheet charge density (2DEG) are measured to be over $$12800\,\hbox {cm}^{2}$$12800cm2/Vs with a sheet charge density larger than 4 $$\times $$× $$10^{12}\,\hbox {cm}^{-2}$$1012cm-2. These high-performance enhancement-mode MHEMTs are attractive candidates for future terahertz applications such as high-resolution radars for space research and also for low-noise wide-bandwidth amplifier for future communication systems.

Journal ArticleDOI
TL;DR: In this paper, a simulator for solving self-consistently the Boltzmann transport equations for both electrons and phonons has been developed to investigate the self-heating effects in a 20 nm-long double-gate MOSFET.
Abstract: To study the thermal effect in nano-transistors, a simulator solving self-consistently the Boltzmann transport equations for both electrons and phonons has been developed. It has been used to investigate the self-heating effects in a 20 nm-long double-gate MOSFET (Fig. 1). A Monte Carlo solver for electrons is coupled with a direct solver for the steady-state phonon transport. The latter is based on the relaxation time approximation. This method is particularly efficient to provide a deep insight of the out-of-equilibrium thermal dissipation occurring at the nanometer scale when the device length is smaller than the mean free path of both charge and thermal carriers. It allows us to evaluate accurately the phonon emission and absorption spectra in both real and energy spaces.

Journal ArticleDOI
TL;DR: In this article, an analytical model of the threshold voltage for short-channel symmetrical silicon nano-tube field effect transistors (Si-NT FETs) is presented, where the inversion charge density is calculated in the channel region of the device in the subthreshold regime of device operation, using the Boltzmann relationship.
Abstract: In this paper, an analytical model of the threshold voltage for short-channel symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs) is presented. The three-dimensional (3D) Poisson equation in cylindrical coordinates has been solved with suitable boundary conditions to find the surface potential along the channel length. The inversion charge density $$(Q_{inv} )$$(Qinv) has been calculated in the channel region of the device in the subthreshold regime of device operation, using the Boltzmann relationship. Subsequently, the calculated inversion charge density $$(Q_{inv} )$$(Qinv) has been equated to a threshold charge density $$(Q_{th})$$(Qth) in order to find the threshold voltage $$(V_{th})$$(Vth) expression. The effect of physical device parameters, including the tube thickness, on the threshold voltage and drain induced barrier lowering (DIBL) of the device has been discussed. The model results have been verified with the simulation data obtained by the device simulation software ATLAS.

Journal ArticleDOI
TL;DR: In this paper, a comparative performance analysis in terms of delay, power dissipation, power delay product (PDP), and crosstalk noise between SWCNT bundle interconnects with resistance estimated using conventionally (temperature independent model), and thermally aware model is investigated.
Abstract: A comparative performance analysis in terms of delay, power dissipation, power delay product (PDP), and crosstalk noise between SWCNT bundle interconnects with resistance estimated using conventionally (temperature independent model), and thermally aware model is investigated. The results are also compared with those of currently used copper interconnects at 22 nm technology node. It is observed that, with rise in temperature from 300 to 500 K, SWCNT bundles have a lower delay than that of copper interconnect at different lengths from 100 to $$1000\,\upmu \hbox {m}$$1000μm whereas reverse is true for power dissipation. The SPICE simulation results further reveal that for temperature variations ranging from 300 to 500 K, compared to conventional metal (copper) conductors, crosstalk noise voltage levels (positive peaks) in capacitively coupled SWCNT bundle, at the far end of victim line, are significantly low. Moreover, a relative average improvement in delay, power, and PDP using a thermally aware model in comparison with a temperature independent model is about 22.44, 7.59 and 31.96 %, respectively, with length variations from 100 to $$1000\,\upmu \hbox {m}$$1000μm, whereas for varied tube diameter is about 16.6, 5.6 and 19.72 %, respectively. The average relative improvement in the time duration reduction of victim output, for varied tube diameters, is about 21.7 % by using a thermally-aware model instead of a temperature-independent model of an SWCNT bundle resistance.

Journal ArticleDOI
TL;DR: In this article, a doping-less tunnel field effect transistor (DLTFET) with a 0.45 source structure was proposed to improve the performance of charge-plasma-based DLTFETs.
Abstract: This paper reports studies of a doping-less tunnel field-effect transistor (TFET) with a $$\hbox {Si}_{0.55} \hbox {Ge}_{0.45}$$Si0.55Ge0.45 source structure aimed at improving the performance of charge-plasma-based doping-less TFETs. The proposed device achieves an improved ON-state current ($$I_{{\mathrm{ON}}} \sim {4.88} \times {10}^{-5}\,{\mathrm{A}}/\upmu {\mathrm{m}}$$ION~4.88×10-5A/μm), an $$I_\mathrm{ON}/I_\mathrm{OFF}$$ION/IOFF ratio of $${6.91} \times {10}^{12}$$6.91×1012, an average subthreshold slope ($$\hbox {AV-SS}$$AV-SS) of $$\sim $$~$${64.79}\,{\mathrm{mV/dec}}$$64.79mV/dec, and a point subthreshold slope (SS) of 14.95 mV/dec. This paper compares the analog and radio of frequency (RF) parameters of this device with those of a conventional doping-less TFET (DLTFET), including the transconductance ($$g_{{\mathrm{m}}}$$gm), transconductance-to-drain-current ratio $$(g_\mathrm{m}/I_\mathrm{D})$$(gm/ID), output conductance $$(g_\mathrm{d})$$(gd), intrinsic gain ($$A_{{\mathrm{V}}}$$AV), early voltage ($$V_{{\mathrm{EA}}}$$VEA), total gate capacitance ($$ C_{{\mathrm{gg}}}$$Cgg), and unity-gain frequency ($$f_{{\mathrm{T}}}$$fT). Based on the simulated results, the $$\hbox {Si}_{0.55}\hbox {Ge}_{0.45}$$Si0.55Ge0.45-source DLTFET is found to offer superior analog as well as RF performance.

Journal ArticleDOI
TL;DR: In this paper, two structures of wide band gap high electron mobility transistor (HEMT) are presented, one structure is made up of a stack of AlGaN layer over GaN layer and the other structure introduces an AlN spacer layer between the Al GaN and GaN layers to improve these characteristics.
Abstract: This paper presents two structures of wide band gap high electron mobility transistor (HEMT). One structure is made-up of a stack of AlGaN layer over GaN layer. This structure is characterized by two-dimensional (2-D) electron gas layer formed at the interface of the AlGaN and GaN layers. The 2-D electron gas plays an important role in determining the carrier-mobility $$(\upmu )$$(μ) and hence drain-to-source current $$(I_\mathrm{DS})$$(IDS) of HEMT. The other structure introduces an AlN spacer layer between the AlGaN and GaN layers to improve these characteristics. This paper compares the output characteristics curves $$(I_\mathrm{DS}-V_\mathrm{DS})$$(IDS-VDS) and transconductance characteristics curves $$(I_\mathrm{DS}-V_\mathrm{GS})$$(IDS-VGS) obtained from simulations performed using Silvaco $$\hbox {ATLAS}^\mathrm{TM}$$ATLASTM. The modified structure with spacer layer shows improvements in carrier-mobility and hence drain-to-source current. This paper estimates and compares the subthreshold slope (SS) of the two devices. AlGaN/AlN/GaN HEMT offers an SS of 80 mV/decade whereas AlGaN/GaN HEMT offers an SS of 95 mV/decade. Thus, an improvement in SS of about 18.75 % is achieved in AlGaN/AlN/GaN HEMT compared to AlGaN/GaN HEMT. HEMT with spacer layer also offers 10$$\times $$× improvement in $$I_{DS}$$IDS as compared to HEMT without spacer layer. The proposed HEMTs achieve $$\approx $$?3.19$$\times $$× improvement in breakdown voltage, $$>$$>1.3$$\times $$× improvement in SS compared to HEMTs previously proposed in the literature.

Journal ArticleDOI
TL;DR: In this article, the authors investigate theoretically the possibility of exploiting the electrically tunable band gap property of silicene to achieve field effect transistor with improved characteristics and find that the device output characteristic displays a very good saturation due to improved pinch-off of the channel.
Abstract: We investigate theoretically the possibility of exploiting the electrically tunable band gap property of silicene to achieve field effect transistor with improved characteristics. We find that the silicene field effect transistor where a band gap is introduced through a perpendicular electric field shows a subthreshold swing smaller than 60 mV/decade and a switching effect with high on/off current ratio exceeding $$10^{5}$$105. We find also that the device output characteristic displays a very good saturation due to improved pinch-off of the channel, stemming from the electrically induced band gap.

Journal ArticleDOI
TL;DR: In this article, a self-consistent quantum drift-diffusion model for multiple quantum well (MQW) impact avalanche transit time (IMPATT) diodes is presented, where the bound states in MQWs have been taken into account by selfconsistent solutions of the coupled classical driftdiffusion (CLDD) equations and time independent Schrodinger equations associated with both the conduction and valence bands.
Abstract: In this paper, the authors have presented a self-consistent quantum drift-diffusion model for multiple quantum well (MQW) impact avalanche transit time (IMPATT) diodes. The bound states in MQWs have been taken into account by self-consistent solutions of the coupled classical drift-diffusion (CLDD) equations and time-independent Schrodinger equations associated with both the conduction and valence bands. The static and high-frequency properties of MQW DDR IMPATTs based on Si$$\sim $$~3C-SiC material system designed to operate near 94-GHz atmospheric window have been studied by means of the above-mentioned self-consistent solutions of coupled CLDD equations and Schrodinger equations followed by a well-established double-iterative field maximum computational technique. A symmetric and two complementary asymmetric doping profiles for the proposed structures have been taken into account for the present study. The RF power outputs of Si$$\sim $$~3C-SiC MQW DDR IMPATTs near 94 GHz obtained from the simulation are compared with the experimentally obtained power outputs of flat DDR IMPATT diodes based on Si, GaAs, and InP at the same frequency band. It is observed that Si$$\sim $$~3C-SiC MQW DDR IMPATTs are capable of delivering significantly higher RF power compared with IMPATTs based on the above-mentioned materials especially when the doping concentrations of 3C-SiC layers are kept higher than those of the Si layers.

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TL;DR: In this article, the ground-state geometries of selected anthoxanthins belonging to the Flavone and Flavonol families were optimized by Density-Functional Theory (DFT).
Abstract: Systematic theoretical investigations of selected anthoxanthins belonging to the Flavone and Flavonol families are carried out with the aim of identifying the dye with the optimum properties for use as sensitizers in dye sensitized solar cells (DSSCs). The ground-state geometries of these dyes in the gas phase are fully optimized by Density-Functional Theory (DFT). Time-Dependent Density Functional Theory (TDDFT) with Polarizable Continuum Model (PCM) for solvent effects is invoked to predict the vertical electron excitation energy, maximal absorption wavelength, oscillator strengths, light harvesting efficiency (LHE), free energy change of electron injection $$\left( {\Delta } G^{inject}\right) $$ΔGinject and dye regeneration $$\left( {\Delta } G_{dye}^{regen}\right) $$ΔGdyeregen. The charge transfer from the excited state and charge regeneration in the ground state of the dyes is also identified. All these calculations were performed in the gas phase and with dimethyl sulfoxide (DMSO) as solvent. Finally, the electron transfer characteristics between the dye's lowest unoccupied molecular orbital (LUMO) and the conduction band of $$\hbox {TiO}_{2}$$TiO2 are investigated. The study reveals that the electron transfer character of these dyes can be made suitable for applications in DSSCs with structural modifications.

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TL;DR: In this article, the coherent and incoherent transport simulation capabilities of the multipurpose nanodevice simulation tool NEMO5 are presented and applied on transport in tunneling field effect transistors.
Abstract: In this work, the coherent and incoherent transport simulation capabilities of the multipurpose nanodevice simulation tool NEMO5 are presented and applied on transport in tunneling field-effect transistors. The comparison with experimental resistivity data confirms the validity of NEMO5's phonon-scattering models. Common pitfalls of numerical implementations and the applicability of common approximations of scattering self-energies are discussed. The impact of phonon-assisted tunneling on the performance of TFETs is exemplified with a concrete Si nanowire device. The communication-efficient implementation of self-energies in NEMO5 is demonstrated with a scaling comparison of self-energies solved with blocking and nonblocking MPI-communication.

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TL;DR: A new voltage-mode (VM) full-wave rectifier circuit employing two plus-type differential voltage–current conveyors, two grounded resistors, and two diodes is proposed, suitable for direct cascading with other VM circuits without requiring additional buffers.
Abstract: In this paper, a new voltage-mode (VM) full-wave rectifier circuit employing two plus-type differential voltage---current conveyors, two grounded resistors, and two diodes is proposed. The proposed full-wave rectifier enjoys high input impedance and low output impedance; accordingly, it is suitable for direct cascading with other VM circuits without requiring additional buffers. It employs only two grounded resistors which are advantageous for integrated circuit implementations. However, it needs a single resistor-matching condition. It is simulated using SPICE program to verify the theoretical analysis.

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TL;DR: In this article, an analytical model for the sub-threshold swing of nanoscale undoped trigate silicon-on-insulator metal-oxide-semiconductor field effect transistors (MOSFETs) is proposed, based on the channel potential distribution and physical conduction path concept.
Abstract: A new analytical model for the subthreshold swing of nanoscale undoped trigate silicon-on-insulator metal---oxide---semiconductor field-effect transistors (MOSFETs) is proposed, based on the channel potential distribution and physical conduction path concept. An analytical model for the potential distribution is obtained by solving the three-dimensional (3-D) Poisson's equation, assuming a parabolic potential distribution between the lateral gates. In addition, mobile charges are considered in the model. The proposed analytical model is investigated and compared with results obtained from 3-D simulations using the ATLAS device simulator and experimental data. It is demonstrated that the analytical model predicts the subthreshold swing with good accuracy for different lengthes, thicknesses, and widths of channel.