Showing papers in "Journal of Electronic Packaging in 1996"

An Ultra-High Power Two-Phase Jet-Impingement Avionic Clamshell Module

Abstract: Boiling jet impingement heat transfer from a simulated electronic chip to Fluorinert FC-72 within a clamshell avionic module was investigated for dependence upon inlet fluid temperature, nozzle diameter, nozzle to chip spacing, jet velocity, and chip length. The clamshell module was designed and fabricated to accommodate both single and multiple chip boards and to demonstrate the feasibility of an ultra-high power (on the order of several kilowatts) module. Critical heat flux ( CHF ) was found to be directly dependent upon subcooling and jet velocity, but relatively unaffected by the nozzle to chip spacing variations examined. The effect of varying the chip size was evaluated and found to produce higher CHF values as chip size was decreased. A correlation accounting for both geometric and subcooling effects was adapted to predict the CHF database with a mean absolute error of 9.6 percent. The module is shown to be capable of dissipating a heat load of 12,000 W at a module flow rate of 8.01 X 10 -4 m3/s (12.7 gpm), thus eclipsing the current technology available in avionic cooling.

Prediction of Solder Joint Geometries in Array-Type Interconnects

Abstract: An approximate mathematical model is developed for predicting the shapes of solder joints in an array-type interconnect (e.g., a ball-grid array or flip-chip interconnect). The model is based on the assumption that the geometry of each joint may be represented by a surface of revolution whose generating meridian is a circular arc. This leads to simple, closed-form expressions relating stand-off height, solder volume, contact pad radii, molten joint reaction force (exerted on the component), meridian curvature, and solder surface tension. The qualitative joint shapes predicted by the model include concave (hourglass-shaped), convex (barrel-shaped, with a truncated sphere as a special case), and truncated-cone geometries. Theoretical results include formulas for determining the maximum and minimum solder volumes that can be supported by a particular pair of contact pads. The model is used to create dimensionless plots which summarize the general solution in the case of a uniform array (i.e., one comprising geometrically identical joints) for which the contact pads on the component and substrate are of the same size. These results relate the values of joint height and width (after reflow) to the solder joint volume and the molten-joint force for arbitrary values of the pad radius and solder surface tension. The graphs may be applied to both upright and inverted reflow, and can be used to control stand-off for higher reliability or to reduce bridging and necking problems causing low yields. A major advantage of the model is that it is numerically efficient (involving only simple, closed-form expressions), yet generates results that are in excellent agreement with experimental data and more complex models. Thus, the model is ideally suited to performing parametric studies, the results of which may be cast in a convenient form for use by practicing engineers. Although in the present paper the array is assumed to be doubly-symmetric, i.e., possess two orthogonal planes of symmetry, the model may be extended to analyze arrays of arbitrary layout. The motivation for predicting joint geometries in array-type interconnects is two-fold: (1) to achieve optimal joint geometries from the standpoint of improved yield and better reliability under thermal cycling and (2) to take full advantage of the flexibility of new methods of dispensing solder, such as solder-jet and solder-injection technologies, which enable the volume of each individual joint to be controlled in a precise manner. Use of dispensing methods of these types permits the solder volumes in the array to be distributed in a non-uniform manner. Results such as those presented here (in combination with appropriate fatigue studies) can be used to determine the optimal arrangement of solder volumes.

Verification of Numerical Models Used in Microelectronics Packaging Design by Interferometric Displacement Measurement Methods

Abstract: Verified/predictive modeling has become an integral part of electronic packaging product development in order to reduce costs and cycle time. In this paper, interferometric displacement measurement methods are utilized to verify the validity of numerical models for microelectronics packaging design. Three optical methods with submicron sensitivities are employed: moire interferometry, microscopic moire interferometry and Twyman/Green interferometry. The first two provide contour maps of in-plane displacement fields, and the third maps out-of-plane displacement fields. Their high sensitivity and high spatial resolution make them ideally suited for verification of numerical models. By combining numerical modeling and experimental verification until the results merge, numerical models become more accurate and dependable. Then, the models can be applied extensively to optimize the package designs with confidence that the models provide effective information on material and geometry sensitivity.

Vibration Induced Fatigue Life Estimation of Corner Leads of Peripheral Leaded Components

Abstract: The rapid advancement of integrated circuits and associated electronic technologies have placed increasing demands on electronic packaging and its material structures in terms of the reliability requirements. In addition to the thermally induced stresses, electronic packages often experience dynamic external loads during shipping, handling, and/or operation. This is especially important for automotive, military, and commercial avionics operating environments. These dynamic loads give rise to large dynamic stresses in the leads causing fatigue failures. For peripheral leaded packages the corner leads are the most highly stressed leads. This paper addresses the determination of the out-of-plane displacement of the corner leads of peripheral leaded components when the local peripheral leaded component/board assembly is subjected to bending moments in two directions. The solution is achieved by using a combination of Finite Element Analysis (FEA), Design of Experiments (DOE), and analytical techniques. The out-of-plane displacement can then be applied as a boundary condition on a local lead model to determine the stresses which in turn can be used to estimate the fatigue life.

Effect of Interface Roughness on Fatigue Crack Growth in Sn-Pb Solder Joints

Abstract: The effect of interface roughness on fatigue crack growth was studied by examining the contribution of crack-surface sliding to the fatigue crack growth resistance of the interface in 63Sn-37Pb solder joints. Model interfaces with different values of roughness were produced in Sn-Pb/Cu joints by systematically varying the morphology of the intermetallic phase at the interface. Fracture mechanics analysis was conducted to calculate the crack-sliding resistance as a function of interface roughness, contact zone length, the shear strength of the solder, and elastic properties of bi-materials. The results were compared to the variation of fatigue crack growth threshold with interface morphology.

An Interfacial Delamination Analysis for Multichip Module Thin Film Interconnects

Abstract: Analysis of interfacial delamination for multichip module thin-film interconnects (MCM/TFI) is the primary objective of this paper. An interface crack model is integrated with finite-element analysis to allow for accurate numerical evaluation of the magnitude and phase angle of the complex stress intensity factor. Under the assumption of quasi-static delamination growth, the fate of an interfacial delamination after inception of propagation is determined. It is established that whether an interfacial delamination will continue to grow or become arrested depends on the functional behavior of the energy release rate and loading phase angle over the history of delamination growth. This functional behavior is numerically obtained for a typical MCM/TFI structure with delamination along die and via base, subjected to thermal loading condition. The effect of delamination interactions on the structural reliability is also investigated. It is observed that the delamination along via wall and polymer thin film can provide a benevolent mechanism to relieve thermal constraints, leading to via stress relaxation.

A Model Study of Thermal Stress-Induced Voiding in Electronic Packages

Abstract: Thin film metallizations are one of the most important interconnects in large-scale integrated circuits They are covered by substrates and passivation films Large hydrostatic (mean) tension develops due to the constraint and thermal mismatch, and voiding is identified as the failure mechanism This phenomenon of rapid nucleation and growth of voids is called cavitation instability and it can lead to the failure of ductile components in electronic packages such as metallizations A micromechanics model is developed to provide the critical mean stress level that will trigger the cavitation instability It is found that this critical mean stress level the cavitation stress, not only depends on the material properties but also is very sensitive to defects in the material For example, the cavitation stress decreases drastically as the void volume fraction increases The stress-based design criterion for ductile components in electronic packages should then be: (1) Von Mises effective stress < yield stress; and (2) mean stress < cavitation stress, which is particularly important to the constrained ductile components in electronic packages such as vias and conductive adhesives An analytical expression of cavitation stress for elastic-perfectly plastic solids is obtained, and numerical results for elastic-power law hardening solids are presented

Single-Phase and Boiling Cooling of Small Pin Fin Arrays by Multiple Nozzle Jet Impingement

Abstract: Experimental measurements of multiple nozzle submerged jet array impingement single-phase and boiling heat transfer were made using FC-72 and 1 cm square copper pin fin arrays, having equal width and spacing of 0.1 and 0.2 mm, with aspect ratios from 1 to 5. Arrays of 25 and 100 nozzles were used, with diameters of 0.25 to 1.0 mm providing nozzle area from 5 to 20 mm2 (5 to 20% of the heat source base area). Flow rates of 2.5 to 10 cm3 /s (0.15 to 0.6 l/min) were studied, with nozzle velocities from 0.125 to 2 m/s. Single nozzles and smooth surfaces were also evaluated for comparison. Single-phase heat transfer coefficients (based on planform area) from 2.4 to 49.3 kW/m2 K were measured, while critical heat flux varied from 45 to 395 W/cm2 . Correlations of the single-phase heat transfer coefficient and critical heat flux as functions of pin fin dimensions, number of nozzles, nozzle area and liquid flow rate are provided.

Comparison of the Cooling Performance of Staggered and In-Line Arrays of Electronic Packages

Abstract: The cooling performance of in-line and staggered regular arrays of simulated electronic packages is compared for both sparse and dense packaging configurations. At equal flow rates, staggered arrays exhibit higher element heat transfer coefficients and friction factors than in-line arrays. Furthermore, an increase in the packaging density of the elements results in a moderate reduction in the friction factor with negligible change in the heat transfer coefficient. However, when performance is expressed in terms of heat transfer rate per unit packaging system volume, dense arrays are found to out perform sparse arrays at equal flow rate, applied pressure gradient or pumping power. Furthermore, no significant difference in performance is observed between staggered and in-line configurations when they are compared on the basis of either equal coolant flow pressure drop or pumping power.

An Experimental Technique for Studying Mixed-Mode Fatigue Crack Growth in Solder Joints

Abstract: Failures of solder joints often result from development of cracks under complex mixed-mode loading conditions In this study, a flexural peel technique was developed to investigate the growth of cracks at the interface between solder and Cu substrate The technique was based on a tri-layer solder/Cu joints, with the solder layer sand-wiched between two Cu layers of desired thicknesses Finite element analysis was used to calculate the mixed-mode condition at the crack tip as a function of the thicknesses of Cu outerlayers and the solder interlayer The application of this technique to studying interface crack growth under fatigue loading is demonstrated for eutectic solder joints

Experimental Investigation of the Formation of Surface Mount Solder Joints

Abstract: As part of a major project to develop a computer-based model to support the product and process design activity for reflow soldered assemblies, it has been found necessary to carry out fundamental investigations of the processes occurring as solder pastes approach and pass the reflow temperature. This paper presents the results and our interpretation of the observed physical phenomena arising from recent high-speed video microscopy studies of the reflow of bulk deposits of solder paste and also of the formation of solder joints during infrared reflow soldering. These studies have provided insights into the physical phenomenology of reflowing solder paste, the interpretation of wetting curves and the mechanisms behind the formation of manufacturing driven defects.