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Showing papers in "Journal of Electronic Packaging in 1997"


Journal ArticleDOI
TL;DR: In some engineering systems processing of experimental data as mentioned in this paper, random loads and responses in some engineering system processing of test data are discussed. But they do not cover the full spectrum of random variables.
Abstract: Random events discrete random variables continuous random variables systems of random variables functions of random variables entropy and information random processes - correlation theory random processes - spectral theory extreme value distributions reliability Markovian processes random fatigue geometric tolerance random loads and responses in some engineering systems processing of experimental data.

142 citations




Journal ArticleDOI
TL;DR: In this paper, the authors present a glossary of the latest trends and challenges in the field of failure detection and defect analysis. But they do not discuss the issues of quality assurance and accelerated testing.
Abstract: Plastic Packaging Materials Manufacturing Processes Assembly Onto Printed Wiring Boards Packing and Handling Failure Mechanisms, Sites, and Modes Quality Assurance Qualification and Accelerated Testing Defect Analysis Techniques Trends and Challenges Glossary Index.

64 citations



Journal ArticleDOI
TL;DR: In this article, a finite element analysis of thermally loaded solder joints is coupled with a newly developed approach for fatigue life prediction by using a volume-weighted averaging technique instead of an approach based on the maximum stress and strain locations in the solder joint.
Abstract: Fatigue lives of thermally loaded solder joints are predicted using the finite element method. An appropriate constitutive relation to model the time-dependent inelastic deformation of the near-eutectic solder is implemented into a commercial finite element code, and the stress-strain responses of different electronic assemblies under the applied temperature cycles are calculated. The finite element analysis results are coupled with a newly developed approach for fatigue life predictions by using a volume-weighted averaging technique instead of an approach based on the maximum stress and strain locations in the solder joint. Volume-weighted average stress and strain results of three electronic assemblies are related to the corresponding experimental fatigue data through least-squares curve-fitting analyses for determination of the empirical coefficients of two fatigue life prediction criteria. The coefficients thus determined predict the mean cycles-to-failure value of the solder joints. Among the two prediction criteria, the strain range criterion uses the inelastic shear strain range and the total strain energy criterion uses the total inelastic strain energy calculated over a stabilized loading cycle. The obtained coefficients of the two fatigue criteria are applied to the finite element analysis results of two additional cases obtained from the literature. Good predictions are achieved using the total strain energy criterion, however, the strain range criterion underestimated the fatigue life. It is concluded that the strain information alone is not sufficient to model the fatigue behavior but a combination of stress and strain information is required, as in the case of total inelastic strain energy. The superiority of the volume-weighted averaging technique over the maximum stress and strain location approach is discussed.

48 citations




Journal ArticleDOI
TL;DR: In this article, the combined effects of pressure and subcooling on nucleate pool boiling and critical heat flux (CHF) for degassed fluorocarbon FC-72 boiling on a plastic pin-grid-array (PPGA) chip package were investigated.
Abstract: This study presents a detailed experimental investigation of the combined effects of pressure and subcooling on nucleate pool boiling and critical heat flux (CHF) for degassed fluorocarbon FC-72 boiling on a plastic pin-grid-array (PPGA) chip package. In these experiments pressure was varied between 101.3 and 303.9 kPa and the subcooling ranged from 0 to 65°C. As expected, lower wall superheats resulted from increases in pressure, while subcooling had a minimal effect on fully developed pool boiling. However, the superheat reductions and CHF enhancements were found to be smaller than those predicted by existing models. The CHF for saturated liquid conditions increased by nearly 17 percent for an increase in pressure from 101.3 to 202.7 kPa. In experiments with both FC-72 and FC-87 further increases in pressure did not produce any significant increase in CHF. At a pressure of 101.3 kPa a subcooling of 30°C increased CHF on horizontal upward-facing chips by approximately 50 percent, as compared to 70 percent on vertically oriented packages. The enhancement in CHF due to subcooling decreased rapidly with increasing pressure, and the data showed that the influence of pressure and subcooling on CHF is not additive. A correlation to predict pool boiling CHF under the combined effects of pressure and subcooling is proposed.

41 citations


Journal ArticleDOI
TL;DR: In this article, the authors present a comparison of three-dimensional stacked dielectric dielectrics and chip-on-board (CoBoard) interconnects with three dimensions.
Abstract: Three--Dimensional Stacked Dies. Cofired Ceramic Substrates. Organic Laminated Substrates and Chip--on--Board. High--Density Interconnects and Deposited Dielectrics. Wire and Wirebonds. Tape Automated Bonds. Flip--Chip Bonds. Device and Substrate Attachment. Cases. Leads. Lead Seals. Lid Seals. Material and Product Evaluation Methods. Rework Methods. Bibliography. Index.

40 citations




Journal ArticleDOI
TL;DR: The basic theory and procedures for finding parameters in the model based on laboratory test data and their values for typical solder materials are presented and the DSC shows excellent potential for unified characterization of the stress-strain-strength and failure behavior of engineering materials in electronic packaging problems.
Abstract: The disturbed state concept (DSC) presented here provides a unified and versatile methodology for constitutive modeling of thermomechanical response of materials and interfaces/joints in electronic chip-substrate systems. It allows for inclusion of such important features as elastic, plastic and creep strains, microcracking and degradation, strengthening, and fatigue failure. It provides the flexibility to adopt different hierarchical versions in the range of simple (e.g., elastic) to sophisticated (thermoviscoplastic with microcracking and damage), depending on the user’s specific need. This paper presents the basic theory and procedures for finding parameters in the model based on laboratory test data and their values for typical solder materials. Validation of the models with respect to laboratory test behavior and different criteria for the identification of cyclic fatigue and failure, including a new criterion based on the DSC and design applications, are presented in the compendium paper (Part II, Desai et al., 1997). Based on these results, the DSC shows excellent potential for unified characterization of the stress-strain-strength and failure behavior of engineering materials in electronic packaging problems.

Journal ArticleDOI
TL;DR: In this article, a detailed nonlinear finite element analysis (FEA) was applied to study the thermal cyclic response of solder joints in two particular BGA packages, full-matrix and perimeter.
Abstract: The application of Ball Grid Array (BGA) technology in electronic packaging on high I/O plastic and ceramic packages has grown significantly during the past few years. Although PBGA (plastic BGA) has several advantages over fine-pitch Quad Flat Pack (QFP) in terms of smaller package area, higher I/Os, lower switching noise, large pitch, higher assembly yield, and improved robustness in manufacturing process, potential package reliability problems can still occur, e.g., excessive solder joint deformation induced by substrate warpage, moisture ingression (popcorn effect), large variation in solder ball size, voiding as a result of flux entrapment and improper pad/solder mask design (Marrs and Olachea, 1994; Solberg, 1994; Freyman and Petrucci, 1995; Lau, 1995; Donlin, 1996; Lasky et al., 1996; Munroe et al., 1996). Regardless of its improved thermal fatigue performance over the past few years through an extensive amount of research, the BGA solder joint may still pose a reliability issue under harsh environment, e.g., automotive underhood, larger package size, or higher temperature and temperature gradient due to increase in power dissipation of the package. Numerous studies in BGA solder joint deformation and reliability under thermal and mechanical loadings can be found in the literature, e.g., Borgesen et al. (1993), Choi et al. (1993), Guo et al. (1993), Ju et al. (1994), Lau et al. (1994) Lau (1995), and Heinrich et al. (1995). Also, reliability prediction models have been developed by, e.g., Darveaux et al. (1995) and Darveaux (1996). The present study focuses on the application of a detailed nonlinear finite element analysis (FEA) to studying the thermal cyclic response of solder joints in two particular BGA packages, full-matrix and perimeter. Both time-independent plasticity and time-dependent effect, i.e., creep and relaxation, are considered in the constitutive equations of solder joint to evaluate the discrepancy in the results of life prediction. The critical solder joint is identified, and the locations that are most susceptible to fatigue failure in the critical joint are discussed. Some limitations in computation and reliability prediction are also discussed.


Journal ArticleDOI
TL;DR: In this article, an algorithm that uses simulated annealing to perform electronic component layout while incorporating constraints related to thermal performance is introduced, and a hierarchical heat transfer analysis is developed which is used in conjunction with the simulated AN algorithm to produce final layout configurations that are densely packed and operate within specified temperature ranges.
Abstract: This work introduces an algorithm that uses simulated annealing to perform electronic component layout while incorporating constraints related to thermal performance. A hierarchical heat transfer analysis is developed which is used in conjunction with the simulated annealing algorithm to produce final layout configurations that are densely packed and operate within specified temperature ranges. Examples of three-dimensional component placement test cases are presented including an application to embedded wearable computers.




Journal ArticleDOI
TL;DR: In this paper, the effect of the load-mix on fatigue crack growth is shown to result from shear-enhanced frictional sliding of fatigue crack surfaces, with the effect being more pronounced in the near-threshold regime.
Abstract: Fatigue crack growth at the interface between Sn-Pb solder and Cu was examined under various mixed-mode conditions. The load-mix, in terms of the ratio of Mode-II to Mode-I stress intensities, was systematically changed by varying the thickness ratio of Cu layers in the flexural-peel specimens made from Sn-Pb/Cu joints. Fatigue crack growth experiments were conducted using a sinusoidal waveform at a frequency of 5 Hz and a load-ratio of zero. Fatigue crack growth rates were measured as a function of the total strain energy release rates for a given load-mix. Fatigue crack growth resistance was found to increase with the load-mix, with the effect of the load-mix being more pronounced in the near-threshold regime. The effect of the load-mix on fatigue crack growth is shown to result from shear-enhanced frictional sliding of fatigue crack surfaces.

Journal ArticleDOI
TL;DR: In this article, the thermomechanicaI behavior of a new multilayered substrate with embedded passive components is the focus of the study, where the effect of some key parameters -base layer material, interlayer dielectric material base layer thickness, and temperature range on substrate warpage and interfacial shear and peel stress distribution is presented.
Abstract: The thermomechanicaI behavior of a new multilayered substrate with embedded passive components is the focus of this study. Such structures are typically susceptible to localized interfacial stresses near the free edge, which might initiate delamination and subsequent failure of the electronic component. The effect of some key parameters -base layer material, interlayer dielectric material base layer thickness, and temperature range--on substrate warpage and interfacial shear and peel stress distribution is presented. Material and design recommendations for improved thermomechanical response are suggested based on this initial parametric study.


Journal ArticleDOI
TL;DR: In this article, the performance of micro heat exchangers fabricated on silicon wafers and consisting ofpin arrays and straight channels is evaluated theoretically using three-dimensional numerical simulations, and it is demonstrated that by proper selection of the heat of heat exchanger's geometry, the thermal resistance can be minimized.
Abstract: The performance of micro heat exchangers fabricated on silicon wafers and consisting ofpin arrays and straight channels is evaluated theoretically using three-dimensional numerical simulations. The coolant is liquid nitrogen and the objective is to maintain the wafer’s temperature below 90K so as to facilitate the use of high temperature superconductor interconnects in multichip modules. Both developing and periodic flows are considered. Comparisons of the performance of various geometric configurations are presented It is demonstrated that by proper selection of the heat of the heat exchanger’s geometry, the thermal resistance can be minimized.

Journal ArticleDOI
TL;DR: In this paper, the transient conjugated heat transfer in forced convection for simultaneously developing laminar flow inside a microchannel heat sink is studied by solving the steady momentum equation and the transient energy equation.
Abstract: The transient conjugated heat transfer in forced convection for simultaneously developing laminar flow inside a microchannel heat sink is studied by solving the steady momentum equation and the transient energy equation. A parametric study is performed to understand the effects of channel depth and width, Reynolds number, spacing between channels, and solid to fluid thermal conductivity ratio. Silicon as well as indium phosphide are used as wafer’s material. Step and pulsed variations of the heat load are analyzed. Results show that the time required for the heat transfer to reach steady state condition is longer for the system with larger channel depth or spacing and smaller channel width or Reynolds number. Characteristic results for the fluid mean temperature at the exit, solid maximum temperature, local Nusselt number, and local heat flux are presented graphically as functions of position and time.

Journal ArticleDOI
TL;DR: Resilient silicone-matrix composites containing 7–13 volume percent nickel filaments (0.4 μm diameter) exhibited 74–93 dB electromagnetic interference (EMI) shielding effectiveness at 1–2 GHz and 1 × 10–1 – 2 × 10−2 Ω cm DC volume electrical resistivity.
Abstract: Resilient silicone-matrix composites containing 7–13 volume percent nickel filaments (0.4 μm diameter) exhibited 74–93 dB electromagnetic interference (EMI) shielding effectiveness at 1–2 GHz and 1 × 10−1 – 2 × 10−2 Ω cm DC volume electrical resistivity. The high shielding effectiveness is due to the small diameter of the nickel filaments. The composites are useful for EMI shielding gaskets and cable jackets.



Journal ArticleDOI
TL;DR: In this paper, an analytical expression for determining the maximum solder joint shearing displacement occurring in an a real-array interconnect under global CTE mismatch loading is derived, which may be viewed as a load correction factor.
Abstract: An analytical expression is derived for determining the maximum solder joint shearing displacement occurring in an a real-array interconnect under global CTE mismatch loading. The result may be viewed as a “load correction factor” to be applied to the commonly used estimate which is based on the free thermal expansion of component and substrate. The new expression for the correction factor includes the following parameters: (a) dimensions and material properties of component and substrate; (b) array size and population; (c) material properties of solder; and (d) geometric parameters of the individual joints. The theoretical result is based on modeling the assembly as two circular elastic disks connected by a shear-type “elastic foundation” whose distributed shear stiffness is related to the joint/array characteristics. The analytical expression and the graphical aids presented herein may provide convenient alternatives to performing time-consuming and expensive finite element “macro-analyses” on the assembly for the purpose of specifying boundary conditions for a subsequent “micro-analysis” on a single joint.