Showing papers in "Journal of Electronic Packaging in 2000"

Sodium Silicate Based Thermal Interface Material for High Thermal Contact Conductance

Abstract: Sodium silicate based thermal interface pastes give higher thermal contact conductance across conductor surfaces than polymer based pastes and oils, due to their higher fluidity and the consequent greater conformability. Addition of hexagonal boron nitride particles up to 16.0 vol. percent further increases the conductance of sodium silicate, due to the higher thermal conductivity of BN. However, addition beyond 16.0 vol. percent BN causes the conductance to decrease, due to the decrease in fluidity. At 16.0 vol. percent BN, the conductance is up to 63 percent higher than those given by silicone based pastes and is almost as high as that given by solder. Water is almost as effective as sodium silicate without filler, but the thermal contact conductance decreases with time due to the evaporation of water. Mineral oil and silicone without filler are much less effective than water or sodium silicate without filler. @S1043-7398~00!00402-3#

Accelerated Thermal Cycling and Failure Mechanisms for BGA and CSP Assemblies

Abstract: This paper reviews the accelerated thermal cycling test methods that are currently used by industry to characterize the interconnect reliability of commercial-off-the-shelf (COTS) ball grid array (BGA) and chip scale package (CSP) assemblies. Acceleration induced failure mechanisms varied from conventional surface mount (SM) failures for CSPs. Examples of unrealistic life projections for other CSPs are also presented. The cumulative cycles to failure for ceramic BGA assemblies performed under different conditions, including plots of their two Weibull parameters, are presented. The results are for cycles in the range of -30 C to 100 C, -55 C to 100 C, and -55 C to 125 C. Failure mechanisms as well as cycles to failure for thermal shock and thermal cycling conditions in the range of -55 C to 125 C were compared. Projection to other temperature cycling ranges using a modified Coffin-Manson relationship is also presented.

Thermal Characterization of Electronic Packages Using a Three-Dimensional Fourier Series Solution

Abstract: The need to accurately predict component junction temperatures on fully operational printed circuit boards can lead to complex and time consuming simulations if component details are to be adequately resolved. An analytical approach for characterizing electronic packages is presented, based on the steady-state solution of the Laplace equation for general rectangular geometries, where boundary conditions are uniformly specified over specific regions of the package. The basis of the solution is a general threedimensional Fourier series solution which satisfies the conduction equation within each layer of the package. The application of boundary conditions at the fluid-solid, packageboard and layer-layer interfaces provides a means for obtaining a unique analytical solution for complex IC packages. Comparisons are made with published experimental data for both a plastic quad flat package and a multichip module to demonstrate that an analytical approach can offer an accurate and efficient solution procedure for the thermal characterization of electronic packages. @S1043-7398~00!01403-1#

Micro-Mechanical Deformation Analysis of Surface Laminar Circuit in Organic Flip-Chip Package: An Experimental Study

Abstract: Thermo-mechanical deformations of microstructures in a surface laminar circuit (SLC) substrate are quantified by microscopic moire interferometry. Two specimens are analyzed; a bare SLC substrate and a flip chip package assembly. The specimens are subjected to a uniform thermal loading of DT5270°C and the microscopic displacement fields are documented at the identical region of interest. The nano-scale displacement sensitivity and the microscopic spatial resolution obtained from the experiments provide a faithful account of the complex deformation of the surface laminar layer and the embedded microstructures. The displacement fields are analyzed to produce the deformed configuration of the surface laminar layer and the strain distributions in the microstructures. The high modulus of underfill produces a strong coupling between the chip and the surface laminar layer, which produces a DNP-dependent shear deformation of the layer. The effect of the underfill on the deformation of the microstructures is investigated and its implications on the package reliability are discussed. @S1043-7398~00!01304-9#

Reliability Analysis of Flip Chip Designs Via Computer Simulation

Abstract: A flip chip component is a silicon chip mounted to a substrate with the active area facing the substrate. This paper presents the results of an investigation into the relationship between a number of important material properties and geometric parameters on the thermal-mechanical fatigue reliability of a standard flip chip design and a flip chip design with the use of microvias. Computer modeling has been used to analyze the mechanical conditions of flip chips under cyclic thermal loading where the Coffin-Manson empirical relationship has been used to predict the life time of the solder interconnects. The material properties and geometry parameters that have been investigated are the Young's modulus, the coefficient of thermal expansion (CTE) of the underfill, the out-of-plane CTE (CTEz) of the substrate, the thickness of the substrate, and the standoff height. When these parameters vary, the predicted life-times are calculated and some of the features of the results are explained. By comparing the predicted lifetimes of the two designs and the strain conditions under thermal loading, the local CTE mismatch has been found to be one of most important factors in defining the reliability of flip chips with microvias.

Warpage Measurement on Dielectric Rough Surfaces of Microelectronics Devices by Far Infrared Fizeau Interferometry

Abstract: Far infrared Fizeau interferometry is developed and it is proposed as a tool for warpage measurement of microelectronics devices. The method provides a whole-field map of surface topography with a basic measurement sensitivity of 5.31 mm per fringe contour. The method is implemented by a compact apparatus using a computer controlled environmental chamber for real-time measurement. The method retains the simplicity of classical interferometry while providing wide applicability to dielectric rough surfaces. Roughness tolerance is achieved by utilizing a far infrared light (l510.6 mm). The detailed optical and mechanical configuration is described and selected applications are presented to demonstrate the applicability. The unique advantages of the method are discussed. @S1043-7398~00!01303-7#

Finite Element Analysis of Stress Singularities in Attached Flip Chip Packages

Abstract: Cracking and delamination at the interfaces of different materials in plastic IC packages is a well-known failure mechanism. The investigation of local stress behavior, including characterization of stress singularities, is an important problem in predicting and preventing crack initiation and propagation. In this study, a three-dimensional finite element procedure is used to compute the strength of stress singularities at various threedimensional corners in a typical Flip-Chip assembled Chip-on-Board (FCOB) package. It is found that the stress singularities at the three-dimensional corners are always more severe than those at the corresponding two-dimensional edges, which suggests that they are more likely to be the potential delamination sites. Furthermore, it is demonstrated that the stress singularity at the upper silicon die/epoxy fillet edge can be completely eliminated by an appropriate choice in geometry. A weak stress singularity at the FR4 board/epoxy edge is shown to exist, with a stronger singularity located at the internal die/epoxy corner. The influence of the epoxy contact angle and the FR4 glass fiber orientation on stress state is also investigated. A general result is that the strength of the stress singularity increases with increased epoxy contact angle. In addition, it is shown that the stress singularity effect can be minimized by choosing an appropriate orientation between the glass fiber in the FR4 board and the silicon die. Based on these results, several guidelines for minimizing edge stresses in IC packages are presented. !S1043-7398"00#00904-X$

Multiobjective Optimal Placement of Convectively and Conductively Cooled Electronic Components on Printed Wiring Boards

Abstract: This paper presents a solution methodology for the optimal placement of convective conductively air-cooled electronic components on planar printed wiring boards con ering thermal and electrical/cost design objectives. The methodology combines the a heat transfer solver for the prediction of the temperature distribution among the e tronic components and a genetic algorithm for the adaptive search of optimal or optimal solutions and a multiobjective optimization strategy (Pareto optimization multiattribute utility analysis). After proper validation of the elements of the solut methodology (heat transfer solver/genetic algorithm) in isolation, the methodology u consideration is tested using a placement problem (case study) that considers as o zation criteria the minimization of an estimate of the failure rate of the system of com nents due to thermal overheating (via an Arrhenius relation) and the minimization o total wiring length given some interconnectivity requirements. Results correspondi the case study are presented and discussed for both Pareto optimization and m tribute utility analysis.@S1043-7398 ~00!00801-X#