Showing papers in "Journal of Electronic Packaging in 2010"
85 citations
TL;DR: In this article, a liquid metal cooling device for heat dissipation of high performance CPUs was demonstrated, where GaInSn alloy with the melting point around 10°C was adopted as the coolant and a tower structure was implemented so that the lowest coolant amount was used.
Abstract: Broad societal needs have focused attention on technologies that can effectively dissipate huge amount of heat from high power density electronic devices. Liquid metal cooling, which has been proposed in recent years, is fast emerging as a novel and promising solution to meet the requirements of high heat flux optoelectronic devices. In this paper, a design and implementation of a practical liquid metal cooling device for heat dissipation of high performance CPUs was demonstrated. GaInSn alloy with the melting point around 10°C was adopted as the coolant and a tower structure was implemented so that the lowest coolant amount was used. In order to better understand the design procedure and cooling capability, several crucial design principles and related fundamental theories were demonstrated and discussed. In the experimental study, two typical prototypes have been fabricated to evaluate the cooling performance of this liquid metal cooling device. The compared results with typical water cooling and commercially available heat pipes show that the present device could achieve excellent cooling capability. The thermal resistance could be as low as 0.13°C/W, which is competitive with most of the latest advanced CPU cooling devices in the market. Although the cost (about 70 dollars) is still relatively high, it could be significantly reduced to less than 30 dollars with the optimization of flow channel. Considering its advantages of low thermal resistance, capability to cope with extremely high heat flux, stability, durability, and energy saving characteristic when compared with heat pipe and water cooling, this liquid metal cooling device is quite practical for future application.
58 citations
TL;DR: In this article, two layers of channels were created by machining grooves on both sides of a copper plate in order to increase the channel number per unit volume, and the channels had rectangular crosssections with hydraulic diameters ranging from 0.762 mm to 1.389 mm.
Abstract: The heat transfer performance of flat-plate oscillating heat pipes (FP-OHPs) was investigated experimentally and theoretically. Two layers of channels were created by machining grooves on both sides of a copper plate in order to increase the channel number per unit volume. The channels had rectangular cross-sections with hydraulic diameters ranging from 0.762 mm to 1.389 mm. Acetone, water, diamond/acetone, gold/water, and diamond/water nanofluids were tested as working fluids. It was found that the FP-OHP’s thermal resistance depended on the power input and operating temperature. The FP-OHP charged with 0.0003 vol % gold/water nanofluids achieved a thermal resistance of 0.078 K/W while removing 560 W with a heat flux of 86.8 W/cm2. The thermal resistance was further decreased when the nanofluid was used as the working fluid. A mathematical model predicting the heat transfer performance was developed to predict the thermal performance of the FP-OHP. Results presented here will assist in the optimization of the FP-OHP and provide a better understanding of heat transfer mechanisms occurring in OHPs.
41 citations
TL;DR: In this article, the effect of three different constitutive laws of the lead-free solder, namely Anand viscoplasticity, power law break-down creep, and time-hardening creep, on the board-level thermomechanical fatigue lifetimes of five different wafer-level chip scale packages (WCSPs) was studied by both experiment and finite element method modeling.
Abstract: Board-level thermomechanical fatigue lifetimes of five different wafer-level chip scale packages (WCSPs) with lead-free solder joints were studied by both experiment and finite element method modeling. The effect of three different constitutive laws of the lead-free solder, namely Anand viscoplasticity, power law break-down creep, and time-hardening creep are also investigated for each of the five packages. The fatigue correlation parameters based on the increment of volume-averaged inelastic strain energy density are deduced for each of the corresponding three constitutive laws. It is demonstrated that the relative error of the predicted lifetime for WCSP with lead-free solder joints can be within 10% compared with experiment. It is found that the fatigue correlation parameters depend strongly on the specific constitutive law. Another important finding is that the fatigue correlation parameters depend on the specific package family. It is also demonstrated that when fatigue correlation parameters calibrated for other package families are applied to WCSPs, the error in predicted lifetimes is consistently large.
34 citations
TL;DR: In this article, a new interconnection material-nanosilver paste is used for the LED chip packaging to pursue a better optical performance, since high thermal conductivity of this material can help improve the efficiency of heat dissipation.
Abstract: As a solid electroluminescent source, white light emitting diode (LED) has entered a practical stage and become an alternative to replace incandescent and fluorescent light sources. However, due to the increasing integration and miniaturization of LED chips, heat flux inside the chip is also increasing, which puts the packaging into the position to meet higher requirements of heat dissipation. In this study, a new interconnection material-nanosilver paste is used for the LED chip packaging to pursue a better optical performance, since high thermal conductivity of this material can help improve the efficiency of heat dissipation for the LED chip. The bonding ability of this new die-attach material is evaluated by their bonding strength. Moreover, high-power LED modules connected with nanosilver paste, Sn 3 Ag 0.5 Cu solder, and silver epoxy are aged under hygrothermal aging and temperature cycling tests. The performances of these LED modules are tested at different aging time. The results show that LED modules sintered with nanosilver paste have the best performance and stability.
30 citations
TL;DR: In this article, the authors discuss the nontrivial issues associated with calculating the steady state heat spreading effects generated by a heat source on top of a multilayer assembly such as a printed circuit board.
Abstract: The nontrivial issues associated with calculating the steady state heat spreading effects generated by a heat source on top of a multilayer assembly such as a printed circuit board are discussed. It is argued that problems arise with the interpretation of heat spreading effects due to a misconception about the meaning of often-quoted flux limits and especially the physical meaning of thermal resistance. The usefulness of a number of approaches that are generally in use to analyze heat spreading effects is discussed and it is shown that the popular series-resistance approach has severe limitations. A number of test cases are covered in detail and the results testify to this assertion.
28 citations
TL;DR: In this paper, a pulsating heat pipe (PHP) using a self-rewetting fluid was discussed, where 1-butanol and 1-pentanol were added to water at a concentration of less than 1/5 % to make self-reweffing fluid.
Abstract: This paper discusses a pulsating heat pipe (PHP) using a self-rewetting fluid. Unlike other coommon liqids, self-reweffing flinds have the properfy that the surface tension other common liquids, self-rewetting fluids have the property that the surface tension increases with temperature. The increasing surface tension at a higher temperature can cause the liquid to be drawn toward a heated surface if a dry spot appears and thus to improve boiling heat transfer. In experiments, 1-butanol and 1-pentanol were added to water at a concentration of less than I wt % to make self-rewetting fluid. A pulsating heat pipe made from an extruded multiport tube was partially filled with the self-rewetting fluid water mixture and tested for its heat transport capability at different input power levels. The experiments showed that the maximum heat transport capability was enhanced by a factor of 4 when the maximum heater temperature was limited to 110°C. Thus, the use of a self-rewetting fluid in a PHP was shown to be highly effective in improving the heat transport capability of pulsating heat pipes.
27 citations
TL;DR: A numerical simulation method for electromigration void incubation, and afterwards, void propagation, based on commercial software ANSYS Multiphysics and FORTRAN code, is presented in this paper.
Abstract: As the electronics industry continues to push for high performance and miniaturization, the demand for higher current densities, which may cause electromigration failures in an IC, interconnects. Electromigration is a phenomenon that metallic atoms constructing the line are transported by electron wind. The damage induced by electromigration appears as the formation of voids and hillocks. A numerical simulation method for electromigration void incubation, and afterwards, void propagation, based on commercial software ANSYS Multiphysics and FORTRAN code, is presented in this paper. The electronic migration formulation considering the effects of the electron wind force, stress gradients, temperature gradients, and the atomic concentration gradient has been developed for the electromigration failure mechanisms. Due to introducing the atomic concentration gradient driving force in atomic flux formulations, the conventional atomic flux divergence method is no longer valid in electromigration (EM) simulation. Therefore, the corresponding EM atomic concentration redistribution algorithm is proposed using FORTRAN code. Finally, the comparison of voids generation through the numerical example of a standard wafer electromigration accelerated test (SWEAT) structure with the measurement result is discussed.
25 citations
TL;DR: In this paper, the effect of computer room and computer room air conditioning unit modeling on the perforated tile flow distribution in a representative raised-floor data center was quantified, and it was concluded that modeling the computer room, the CRAC units, and/or the plenum pipes could make an average change of up to 17% in the tile flow rates with a maximum of upto 135% for the facility with 56% open tiles while the average and maximum changes for 25% open tile are 6% and 60%, respectively.
Abstract: This paper is centered on quantifying the effect of computer room and computer room air conditioning (CRAC) unit modeling on the perforated tile flow distribution in a representative raised-floor data center. Also, this study quantifies the effect of plenum pipes and perforated tile porosity on the operating points of the CRAC blowers, total CRAC air flow rate, and its distribution. It is concluded that modeling the computer room, the CRAC units, and/or the plenum pipes could make an average change of up to 17% in the tile flow rates with a maximum of up to 135% for the facility with 56% open tiles while the average and maximum changes for the facility with 25% open tiles are 6% and 60%, respectively.
24 citations
TL;DR: In this article, a coupled electrical-thermal analysis was performed to obtain the nonuniform temperature distribution of electric current and then, a thermomechanical analysis was carried out based on the temperature distribution from the electrical thermal analysis.
Abstract: This paper presents a simulation method to evaluate the thermal fatigue life of a power module. A coupled electrical-thermal analysis was performed to obtain the nonuniform temperature distribution of electric current. Then, a thermomechanical analysis was carried out based on the temperature distribution from the electrical-thermal analysis. Since crack propagation can change the route of heat transfer, a crack path simulation technique was used to investigate the fracture behavior of the power module. The crack initiates in the solder joint below the Al bonding wire of the insulated gate bipolar transistor module and propagates by increasing the diameter. The effect of the bonding type on power cycling fatigue life is also discussed. The fracture process was found to depend on the type of bonding. Lead frame bonding was found to be more effective than wire bonding.
18 citations
TL;DR: A design approach is presented to bring adaptability and concurrency for coordinated minimization of cooling and IT power consumption in data centers using a proper orthogonal decomposition based reduced order thermal modeling approach and power profiling of the IT equipment.
Abstract: Concurrency and exchanging design knowledge among thermal and IT management are required to achieve an energy efficient operational data center. In this paper, a design approach is presented to bring adaptability and concurrency for coordinated minimization of cooling and IT power consumption in data centers. The presented approach is centered on a proper orthogonal decomposition based reduced order thermal modeling approach, and power profiling of the IT equipment to identify the optimal parameters of the air cooling systems along with optimal dynamic workload distribution among the servers. The method is applied to a data center cell with different rack and server architectures. The results show that the design approach results in 12-70% saving in the total energy consumption of the data center cell for various scenarios, compared with a baseline design.
TL;DR: In this paper, the authors investigated the effects of underfill material properties, fillet height, and silicon die thickness on the interface delamination between epoxy molding compound and silicon dies during a lead-free solder reflow process based on the modified virtual crack closure method.
Abstract: The reliability of the flip chip package is strongly influenced by underfill, which has a much higher coefficient of thermal expansion (CTE) compared with other packaging materials and leads to large thermomechanical stresses developed during the assembly processes. Thermal expansion mismatch between different materials causes interface delamination between epoxy molding compound and silicon die as well as interface delamination between underfill and silicon die. The main objective of this study is to investigate the effects of underfill material properties, fillet height, and silicon die thickness on the interface delamination between epoxy molding compound and silicon die during a lead-free solder reflow process based on the modified virtual crack closure method. Based on finite element analysis and experiment study, it can be concluded that the energy release rates at reflow temperature are the suitable criteria for the estimation of interface delamination. Furthermore, it is found that underfill material properties (elastic modulus, CTE, and chemical cure shrinkage), fillet height, and silicon die thickness can be optimized to reduce the risk of interface delamination between epoxy molding compound and silicon die in the flip chip ball grid array package.
TL;DR: In this article, a multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance in a 90 nm Pentium IV Northwood architecture operating at 3 GHz clock speed.
Abstract: Integration of different functional components such as level two (L2) cache memory, high-speed I/O interfaces, and memory controller has enhanced microprocessor performance. In this architecture, certain functional units on the microprocessor dissipate a significant fraction of the total power while other functional units dissipate little or no power. This highly nonuniform power distribution results in a large temperature gradient with Localized hot spots that may have detrimental effects on computer performance, product reliability, and yield. Moving the functional units may reduce the junction temperature but can affect performance by a factor as much as 30%. In this paper, a multi-objective optimization is performed to minimize the junction temperature without significantly altering the computer performance. The analysis was performed for 90 nm Pentium IV Northwood architecture operating at 3 GHz clock speed. Each functional unit on the die has a specific role, so functional units with similar roles were grouped together. Thus, the actual Pentium IV die was divided into four groups (front end, execution cores, bus and L2, and out-of-order engine). Repositioning constraints were determined using circuit delay models of major functional units in a micro-architectural simulator. Thus, depending on the scenario, relocating functional units can result in virtually no performance loss (less than 2% is assumed to be minimal and is reported as 0%) to as much as 30% performance loss. From the results, the minimum and the maximum temperatures were 56.6°C and 62.2°C. This ΔT corresponds to thermal design power of 60.2 W For microprocessors with higher thermal design power (115 W) and operating at higher clock speed, higher ΔT can be realized. Based on this paper's analysis, the optimized scenario resulted in a junction temperature of 56.6 ° C at the cost of a 14% performance loss.
TL;DR: In this paper, the thermal and optical properties of white light-emitting diodes (LEDs) with different phosphor concentrations ranging from 4 to 13 wt % were investigated.
Abstract: The thermal and optical characteristics of phosphor converted white light-emitting diodes (LEDs) with different phosphor concentrations ranging from 4 wt % to 13 wt % are investigated. The light output of LEDs with higher phosphor concentration is found to have larger degradation in constant current compared with pulse current than that with lower phosphor concentration. In addition, the junction temperatures of phosphor converted white LEDs raise with increasing phosphor concentration, so that the decreased phosphor conversion efficiency is observed both in pulse and constant current modes. The physical mechanisms for these observations are discussed. This study elucidates the phosphor dependent optical and thermal behavior of phosphor converted white LEDs.
TL;DR: In this paper, a laser ultrasound-interferometric system was applied to inspect solder joint quality during thermal cycling tests, and it was found out that the LGA packages can withstand 1000 temperature cycles without showing crack initiation or other failure mechanisms in the solder joints.
Abstract: Microelectronics packaging technology has evolved from through-hole, and bulk configuration to surface-mount, and small-profile ones. Today’s electronics industry is also transiting from SnPb to Pb-free to meet environmental requirements. Land grid array (LGA) package has been becoming popular in portable electronics in terms of low profile on the printed wiring boards and direct Pb-free assembly process compatibility. With the package profile shrinking and operating power increasing, solder joint quality and reliability has become a major concern in microelectronics manufacturing. The solder joint failure at the package level or board level will cause electronic devices not to function during service. In this paper, board-level solder joint reliability of the LGA packages under thermal loading is studied through thermal cycling tests. A novel laser ultrasound-interferometric system developed by the authors is applied to inspect solder joint quality during the thermal cycling tests. While the laser ultrasound inspection technique has been successfully applied to flip chips and chip scale packages, this study is the first application of this technique to overmolded packages. In this study, it is found out that the LGA packages can withstand 1000 temperature cycles without showing crack initiation or other failure mechanisms in the solder joints. The laser ultrasound inspection results match the visual observation and X-ray inspection results. This study demonstrates the feasibility of this system to solder joint quality inspection of overmolded packages. In particular, the devices constituting the objective of this study are radio frequency modules, which are encapsulated through overmolding and are mounted on a typical four-layer FR4 board through LGA terminations.
TL;DR: In this paper, the fabrication and measurements of a water-filled 5 mm wide by 10 mm long silicon microheat pipe (MHP) array consisting of 22-100 μm square channels are described.
Abstract: This study details the fabrication and measurements of a water-filled 5 mm wide by 10 mm long silicon microheat pipe (MHP) array consisting of 22-100 μm square channels. This study is unique in that many experimental results reported in open literature are for single channel microheat pipes. The number of channels in the array and the fluid charge used here were optimized under a separate study. A number of experiments were carried out on the specimen MHPs to determine their effective thermal conductivity and comparisons were made with previous results found in literature. The testing methodology was designed to remove systematic biases and the array thermal performance measurements are reported in terms of a silicon equivalence by identically measuring an uncharged empty silicon array as a baseline measurement. Two separate water-filled specimens were made, independently tested, and are reported to have thermal conductivities of 261 W/m K and 324 W/m K, representing a silicon equivalence of 1.8 and 2.2, respectively. All testing was performed in a horizontal orientation.
TL;DR: In this article, the effect of changing the blade chord length on the performance of a small-scale fan was analyzed in terms of the relevant dimensionless parameters: Reynolds number, chord length to diameter of fan ratio, flow coefficient, pressure coefficient, and power coefficient.
Abstract: This paper analyzes the scale effects that occur in miniature centrifugal flow fans and investigates the possibility of optimizing blade geometry so that performance can be enhanced. Such fans are typically employed in small scale heat sinks such as those used for processor cooling applications or in portable electronics. The specific design parameter varied is the blade chord length, and the resulting fan performance is gauged by examining the flow rate, pressure rise, and power consumption characteristics. The former two are measured using a BS 848 fan characterization rig and the latter, by directly measuring the power consumed. These characteristics are studied for three sets of scaled fans with diameters of 15 mm, 24 mm, and 30 mm, and each set considers six individual blade chord lengths. A novel theory is put forward to explain the anticipated effect of changing this parameter, and the results are analyzed in terms of the relevant dimensionless parameters: Reynolds number, chord length to diameter of fan ratio, flow coefficient, pressure coefficient, and power coefficient. When these characteristic parameters are plotted against the Reynolds number, similar trends are observed as the chord length is varied in all sets of scaled fans. The results show that the flow coefficient for all the miniature fans degrade at low Re values, but the onset of this degradation was observed at higher Re values for longer blade chord designs. Conversely, it was found that the pressure coefficient is elevated at low Re, and the onset Re for this phenomenon correlates well with the drop off in flow coefficient. Finally the trend in power coefficient data is similar to that for the flow coefficient. The derived theory is used to correlate this data for which all data points fall within 6% of the correlation. Overall, the finding reported herein provide a good understanding of how changing the blade chord length affects the performance of miniature centrifugal fans; hence, providing fan designers with guidelines to aid in developing optimum blade designs, which minimize adverse scaling phenomena.
TL;DR: In this article, a solid-state bonding process for flip-chip joints between silicon (Si) chips and copper (Cu) substrates was proposed. And the bonding process was performed at 250°C, compatible with typical reflow temperature for lead-free solders.
Abstract: Silver flip-chip joints between silicon (Si) chips and copper (Cu) substrates were fabricated using a solid-state bonding process without any solder and without flux. The bonding process was performed at 250°C, compatible with typical reflow temperature for lead-free solders. During the bonding process, there was no molten phase involved. The Ag joints fabricated consisted of only pure Ag without any intermetallic compound (IMC). Thus, reliability issues associated with IMCs and IMC growth do not exist anymore. Silver has the highest electrical conductivity and highest thermal conductivity among all metals. It is also quite ductile and able to deform to release stresses caused by thermal expansion mismatch. Flip-chip joints of high aspect ratio can be accomplished because the joints stay in a solid state during the bonding process. It looks like that silver is the ultimate joining material for flip-chip as well as through-Si-via interconnect technologies. In this study, the solid-state bonding process was first developed using a pure Ag foil to bond a Si chip to a Cu substrate in one step. The bonding strength on two interfaces, SilAg and Ag/Cu, passes the MIL-STD-883G Method 2019.7. To demonstrate Ag flip-chip interconnects, Si chips were electroplated with Ag bumps, followed by the solid-state bonding process on Cu substrates. The flip-chip bumps are well bonded to the Cu substrate. It would take some time for this new technology to be probably accepted and utilized in production. On the other hand, the preliminary results in this study show that Ag flip-chip joints can indeed be fabricated at 250°C.
TL;DR: In this article, anisotropic conductive films (ACFs) are incorporated with copper (Cu) particles as electrically conductive fillers for environmentally friendly, low cost, high electrical, and high thermal interconnect applications in microelectronics packaging.
Abstract: This paper describes the development and characterization of anisotropically conductive films (ACFs) incorporated with copper (Cu) particles as electrically conductive fillers for environmentally friendly, low cost, high electrical, and high thermal interconnect applications in microelectronics packaging. The Cu particle surface modification by a coupling agent and its effects on the electrical conductivity and thermal stability of Cu-filled ACF joints were investigated for the potential alternatives of conventional Au-coated polymer and Au-coated Ni-filled ACFs. The surface characteristics of a thin film of the coupling agent on copper surfaces such as element analysis, their hydrophobicity, and thermal stability were evaluated. The treated Cu ball-filled ACF showed the lowest contact resistance 1.0×10 -5 Ω, higher current carrying capability, and higher thermal stability of ACF joints compared with the conventional Au-coated polymer ball and Au-coated Ni ball-filled anisotropically conductive adhesives.
TL;DR: In this paper, a comparison between phenolic and amine epoxy systems was made in order to evaluate the reliability performance of a flip chip plastic ball grid array (FC-PBGA).
Abstract: Phenolic and amine epoxy systems are widely used as hardeners in underfill materials for flip chip packaging. A comparison was made between these two systems in order to evaluate the reliability performance of a flip chip plastic ball grid array (FC-PBGA). The coefficient of thermal expansion, glass transition temperature (Tg), Young’s modulus (E), and fracture toughness were revealed by using a thermal mechanical analyzer, a dynamic mechanical analyzer, and a single-edge notch three-point bending test, while moisture absorption study was performed using an 85°C/85% relative humidity chamber. The adhesion strength with different conditions of temperature and humidity was performed using a die shear test. The series of standard reliability tests such as accelerated temperature cycle test, pressure cooker test, thermal humidity storage test, and high temperature storage test were executed upon the FC-PBGA, which was filled by phenolic and amine epoxy systems of underfill materials. It was found that the adhesion strength of phenolic-based underfills is better than that of amine-based underfills in almost all test conditions. Phenolic-based underfills also demonstrated better reliability compared with amine-based underfills.
TL;DR: In this article, the effects of substrate material, substrate surface roughness, and operating temperature on the wetting behavior of eutectic solders on metallic substrates were investigated.
Abstract: The effects of substrate material, substrate surface roughness, and operating temperature on the wetting behavior of Sn–37Pb, Sn–3.5Ag, and Sn–9Zn eutectic solders on metallic substrates were investigated. Solder spreading kinetics was successfully represented by the exponential power law (EPL): ϕ=exp(−Kτn). The EPL parameter K has the significance of accelerating the kinetics of relaxation while the parameter n represents the resistance to spreading process (spread resistance parameter). EPL parameters exhibited a decreasing trend with an increase in surface roughness. Estimated activation energies for solder spreading were found to be in between those reported for inert and highly reactive spreading systems.
TL;DR: In this article, a successive initiation finite element modeling approach is presented in which an empirical continuum damage model, energy partitioning damage evolution model, developed by the author is used to update state of damage and constitutive properties of the material under thermomechanical cyclic loading and accumulate damage in the elements.
Abstract: A successive initiation finite element modeling approach is presented in which an empirical continuum damage model, energy partitioning damage evolution model, developed by the author is used to update state of damage and constitutive properties of the material under thermomechanical cyclic loading and accumulate damage in the elements. Plastic and viscoplastic damages are evaluated based on the plastic and viscoplastic work densities obtained through finite element. Constitutive properties are updated elementwise at each step of the process based on the state of damage in each element. The elements that have reached the damage threshold are removed from the structure to initiate and propagate fatigue crack. This successive initiation approach is used to model crack initiation and propagation in Pb-free solder material under thermomechanical loading. A case study is presented, damage propagation path and pattern are compared with typical experimental results, and the accuracy of the model was verified.
TL;DR: In this paper, a sequential hygro-thermal-mechanical finite-element model has been developed to mimic the load steps associated with package assembly as well as moisture soaking under 85°C/85RH over 500 h.
Abstract: The thermal efficacy of thermal interface material (TIM) is highly dependent on its ability to adhere to the surfaces of interest. Any delamination of the TIM from the die or the lid will increase the local thermal resistance and, thus, will reduce the overall effectiveness of the TIM. Although significant amount of work has been done on understanding the thermal and moisture effects of various polymer materials used in microelectronic package assemblies, very limited work has been done to study the effect of temperature and moisture on TIM delamination. In this paper, a sequential hygro-thermal-mechanical finite-element model has been developed to mimic the loadsteps associated with package assembly as well as moisture soaking under 85°C/85RH over 500 h. The predictions from the models have been validated with a wide range of experimental data including laser Moire data for thermomechanical loading and digital image correlation data for hygro-thermo-mechanical loading. Weight gain and coordinate-measurement machine have been used to characterize moisture diffusivity and moisture expansion coefficient of various polymer materials in the package assembly. The developed models show the evolution of normal strain in TIM during various loadsteps and provide important insight into the potential for TIM delamination under package assembly process and moisture soaking. Thus, the models can be used for developing various designs and process steps for reducing the chances for TIM delamination.
TL;DR: In this article, a high-resolution measurement of flow field in a glass plate with glass cover with two holes was done by a micro-DHPTV system, and the two holes mentioned here were also inside the photo-curable resin.
Abstract: A high time-resolution measurement of flow field in a glass plate with glass cover with two holes was done by a micro-DHPTV system. The two holes mentioned here were also inside the photo-curable resin. Particle measurement was carried out during a 2 s time period that covered the time it took for the curing of resin. This curing time was theoretically calculated from the irradiation flux of the Ultraviolet (UV) source employed in the experiment. Moreover, temperature dependence of photo-curable resin was evaluated by measuring the resin at changing temperatures. Consequently, the tracking of seeding particles could instantaneously be recorded. The 3-D displacements, obtained from the particles being tracked, took place primarily along the direction of the depth. These values were found to be in good agreement with the theoretically calculated displacement values obtained from UV irradiation flux. Moreover, the displacement during photo-curing appeared to be proportional to the increase in temperature.
TL;DR: In this article, four kinds of TGs in which diamond served as essential filler were prepared and hot disk technique was applied to measure their thermal conductivity k(TG), after two unoverlapped particle sizes were selected, the volumetric filler content, terminal group, and viscosity of a polydimethylsiloxane matrix were modified in sequence.
Abstract: As a thermal interface material, thermal grease (TG) has been extensively applied to facilitate heat dissipation in electronic devices. Despite the superior thermal conductivity of diamond, researches on diamond-containing TGs remain rare. In this study, four kinds of TGs in which diamond served as essential filler were prepared and hot disk technique was applied to measure their thermal conductivity k(TG). After two unoverlapped particle sizes were selected, the volumetric filler content, terminal group, and viscosity of a polydimethylsiloxane (PDMS) matrix were modified in sequence. Based on the preferred recipe of a single-filler TG, two double-filler TG series were prepared by retaining the large diamonds and replacing the small ones by Al2O3 or ZnO, respectively. Depending on the content, it was found that diamond was not always the best choice for small filler. The highest k(TG), which was 23 times greater than the original k(PDMS), appeared in a ZnO-containing double-filler grease (=3.52 W/mK). The prediction for the maximum attainable thermal conductivity was preliminarily supported.
IBM1
TL;DR: The thermal profile of a high performance computing cluster located in an data center and a comparison of that cluster modeled via CFD is described and trends showed trends that compared somewhat favorably but some rack thermal profiles deviated quite significantly from measurements.
Abstract: With the ever increasing heat dissipated by information technology (IT) equipment housed in data centers, it is becoming more important to project the changes that can occur in the data center as the newer higher powered hardware is installed. The computational fluid dynamics (CFD) software that is available has improved over the years. CFD software specific to data center thermal analysis has also been developed. This has improved the time lines of providing some quick analysis of the effects of new hardware into the data center. But it is critically important that this software provide a good report to the user of the effects of adding this new hardware. It is the purpose of this paper to examine a large cluster installation and compare the CFD analysis with environmental measurements obtained from the same site. This paper shows measurements and CFD data for high powered racks as high as 27 kW clustered such that heat fluxes in some regions of the data center exceeded 700 W per square foot. This paper describes the thermal profile of a high performance computing cluster located in an data center and a comparison of that cluster modeled via CFD. The high performance advanced simulation and computing (ASC) cluster had a peak performance of 77.8 TFlop/s, and employed more than 12,000 processors, 50 Tbytes of memory, and 2 Pbytes of globally accessible disk space. The cluster was first tested in the manufacturer's development laboratory in Poughkeepsie, New York, and then shipped to Lawrence Livermore National Laboratory in Livermore, California, where it was installed to support the national security mission of the U.S. Detailed measurements were taken in both data centers and were previously reported. The Poughkeepsie results will be reported here along with a comparison to CFD modeling results. In some areas of the Poughkeepsie data center, there were regions that did exceed the equipment inlet air temperature specifications by a significant amount. These areas will be highlighted and reasons given on why these areas failed to meet the criteria. The modeling results by region showed trends that compared somewhat favorably but some rack thermal profiles deviated quite significantly from measurements.
TL;DR: In this paper, the effect of biaxial stress on the variation in electron-mobility was quantitatively evaluated by the electron mobility model but are quantitatively different from the experimental results.
Abstract: Stress-induced changes in the electrical characteristics of a semiconductor device become a major concern in the production of semiconductor packages because the electrical characteristics are adversely affected by packaging (residual) stresses. The objective of our project is to evaluate the effects of stress on semiconductor devices. In this study, the shift of the DC characteristics of nMOSFETs during the resin-molding process was investigated experimentally. After a silicon chip including the n-type metal oxide semiconductor field effect transistors (nMOSFETs) was encapsulated in a quad flat package, the drain current variations and the transconductance shifts were measured. The drain current decreased during the resin-molding process while no significant shift in threshold voltage was observed. The experimental results were estimated adequately from the residual stress predicted by numerical and experimental analyses and from the stress-sensitivity of the nMOSFETs measured by the four-point bending method. Also, we tested the validity of an electron-mobility model that included the effect of stress. The electron-mobility model takes into account the variation in the relative occupancy of the electrons in each conduction-band energy valley. It was found that the effect of biaxial stress on the variation in electron-mobility can be qualitatively evaluated by the electron-mobility model but are quantitatively different from the experimental results. Several needed improvements to the electron-mobility model are proposed in this article.