Showing papers in "Journal of Electronic Packaging in 2012"

An Overview of the IBM Power 775 Supercomputer Water Cooling System

Abstract: In 2008 IBM reintroduced water cooling technology into its high performance computing platform, the Power 575 Supercomputing node/system. Water cooled cold plates were used to cool the processor modules which represented about half of the total system (rack) heat load. An air-to-liquid heat exchanger was also mounted in the rear door of the rack to remove a significant fraction of the other half of the rack heat load: the heat load to air. The next generation of this platform, the Power 775 Supercomputing node/system, is a monumental leap forward in computing performance and energy efficiency. The computer node and system were designed from the start with water cooling in mind. The result, a system with greater than 96% of its heat load conducted directly to water, is a system that, together with a rear door heat exchanger, removes 100% of its heat load to water with no requirement for room air conditioning. In addition to the processor, the memory, power conversion, and I/O electronics conduct their heat to water. Included within the framework of the system is a disk storage unit (disc enclosure) containing an interboard air-to-water heat exchanger. This paper will give an overview of the water cooling system featuring the water conditioning unit and rack manifolds. Advances in technology over this system’s predecessor will be highlighted. An overview of the cooling assemblies within the server drawer (i.e., central electronics complex,) the disc enclosure, and the centralized (bulk) power conversion system will also be given. Furthermore, techniques to enhance performance and energy efficiency will also be described.

Absorption Heat Pump/Refrigeration System Utilizing Ionic Liquid and Hydrofluorocarbon Refrigerants

Abstract: The ionic liquid butylmethylimidazolium hexafluorophosphate (bmim)(PF6) and five different hydrofluorocarbon refrigerants were investigated as the working fluid pairs for a waste-heat driven absorption heat pump system for possible applications in electronics thermal management. A significant amount of the energy consumed in large electronic systems is used for cooling, resulting in low grade waste heat, which can be used to drive an absorption refrigeration system if a suitable working fluids can be identified. The Redlich–Kwong-type equation of state was used to model the thermodynamic conditions and the binary mixture properties at the corresponding states. The effects of desorber and absorber temperatures, waste-heat quality, and system design on the heat pump performance were investigated. Supporting experiments using R134a/(bmim)(PF6) as the working fluid pair were performed. Desorber and absorber outlet temperatures were varied by adjusting the desorber supply power and the coolant temperature at the evaporator inlet, respectively. For an evaporator temperature of 41 C, which is relevant to electronics cooling applications, the maximum cooling-to-total-energy input was 0.35 with the evaporator cooling capability of 36 W and the desorber outlet temperature in the range of 50 to 110 C. [DOI: 10.1115/1.4007111]

Analysis of Flow and Thermal Performance of a Water-Cooled Transversal Wavy Microchannel Heat Sink for Chip Cooling

Abstract: With the increasing output power of the integrated circuit chips, the heat flux involved is being accordingly increased. In such situation, the air has almost reached its limit of cooling capacity, and thus the liquid cooling technology incorporating microchannel heat sinks is desired to cool the electronic chips in order to remove more heat loads. However, these microchannel heat sinks are often designed to be straight with rectangular cross section. In this study, on the basis of a straight microchannel having rectangular cross section, a kind of transversal wavy microchannel is designed and then the laminar flow and heat transfer are investigated numerically. It is shown that for removing the identical load, the transversal wavy microchannel has great potential to reduce pressure drop compared to the straight microchannel, especially for higher wave amplitude at the same Reynolds number, indicating the overall thermal performance of the transversal wavy microchannel is superior to the traditional straight rectangular microchannel. It is suggested such wavy microchannel can be used to cool chips effectively with much smaller pressure drop penalty. [DOI: 10.1115/1.4023035] (Less)

Characterization of Metallically Bonded Carbon Nanotube-Based Thermal Interface Materials Using a High Accuracy 1D Steady-State Technique

Abstract: The next generation of Thermal Interface Materials (TIMs) are currently being developed to meet the increasing demands of high-powered semiconductor devices. In particular, a variety of nanostructured materials, such as carbon nanotubes (CNTs), are interesting due to their ability to provide low resistance heat transport from device to spreader and compliance between materials with dissimilar coefficients of thermal expansion (CTEs). As a result, nano-Thermal Interface Materials (nTIMs) have been conceived and studied in recent years, but few application-ready configurations have been produced and tested. Over the past year, we have undertaken major efforts to develop functional nTIMs based on short, vertically-aligned CNTs grown on both sides of a thin interposer foil and interfaced with substrate materials via metallic bonding. A high-precision 1-D steady-state test facility has been utilized to measure the performance of nTIM samples, and more importantly, to correlate performance to the

Array of Thermoelectric Coolers for On-Chip Thermal Management

Abstract: Site-specific on-demand cooling of hot spots in microprocessors can reduce peak temperature and achieve a more uniform thermal profile on chip, thereby improve chip performance and increase the processor’s life time An array of thermoelectric coolers (TECs) integrated inside an electronic package has the potential to provide such efficient cooling of hot spots on chip This paper analyzes the potential of using multiple TECs for hot spot cooling to obtain favorable thermal profile on chip in an energy efficient way Our computational analysis of an electronic package with multiple TECs shows a strong conductive coupling among active TECs during steady-state operation Transient operation of TECs is capable of driving cold-side temperatures below steady-state values Our analysis on TEC arrays using current pulses shows that the effect of TEC coupling on transient cooling is weak Various pulse profiles have been studied to illustrate the effect of shape of current pulse on the operation of TECs considering crucial parameters such as total energy consumed in TECs peak temperature on the chip, temperature overshoot at the hot spot and settling time during pulsed cooling of hot spots The square root pulse profile is found to be the most effective with maximum cooling and at half the energy expenditure in comparison to a constant current pulse We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots The analysis shows that the transient cooling using high amplitude current pulses is beneficial for short term infrequent hot spots, but high amplitude current pulse cannot be used for very frequent or long lasting hot spots

A Multiphysics Finite Element Model of a 35A Automotive Connector Including Multiscale Rough Surface Contact

Abstract: Electrical contacts influence the reliability and performance of relays, electrical connectors, high power connectors, and similar systems, and are therefore a key region which needs to be considered. In the current study, a new inclusive multiphysics (involving mechanical, electrical, and thermal fields) finite element model (FEM) of a 35A automotive connector has been developed. The contact resistance is predicted using a multiscale rough surface contact method and is embedded in the multiphysics FEM. The coupled connector model is solved to obtain stresses, displacements, contact pressures, electrical and thermal contact resistances, voltage, current density, and temperature distributions. It appears that the current flows mostly through very small regions that are usually near the contacting surfaces in the connector, thereby suggesting that the available conducting material can be more efficiently used by developing optimized connector designs. Through analytical calculations and experimental measurements of temperature rise (ΔT or change in temperature) for the cable and the connector, it is believed that a large portion of the temperature rise in actual 35A connectors is due to the Joule heating in the supply cables. The model is a powerful tool that can be used for the basic connector characterization, prototype evaluation, and design through various material properties, and surface finishes.

Optimization of Enclosed Aisle Data Centers Using Bypass Recirculation

Abstract: used for exploring optimization possibilities in air-cooled data centers. The model is used to evaluate parametrically the total energy consumption of the data center cooling infrastructure for data centers that utilize aisle containment. The analysis highlights the importance of reducing the total power required for moving the air within the computer room air conditioners (CRACs), the plenum, and the servers, rather than focusing primarily or exclusively on reducing the refrigeration system’s power consumption. In addition, the benefits of introducing a bypass recirculation branch in enclosed aisle configurations are shown. The analysis shows a potential for as much as a 60% savings in cooling infrastructure energy consumption by utilizing an optimized enclosed aisle configuration with bypass recirculation, instead of a traditional enclosed aisle in which all the data center exhaust is forced to flow through the CRACs. Furthermore, computational fluid dynamics is used to evaluate practical arrangements for implementing bypass recirculation in raised floor data centers. A configuration where bypass tiles, with controllable low-lift fans, are placed close to the discharge of CRACs results in increased mixing and is shown to be a suitable method for providing nearly thermally uniform conditions to the inlet of the servers in an enclosed cold aisle. Other configurations of bypass implementation are also discussed and explored. [DOI: 10.1115/1.4005907]

Thermal Stresses of Through Silicon Vias and Si Chips in Three Dimensional System in Package

Abstract: Rbased on finite element method (FEM) was used to simulate the effects of voids formed inside Cu TSVs on the thermal conduction and mechanical stresses in the TSV structure. The thermal performance that was required in 3D SiP was estimated to ensure the reliability. Simulations for thermal stresses in the TSV structure in 3D SiP were carried out under thermal condition due to power ON/ OFF of device. In case that void was not present inside the TSV, the stresses in TSV were close to the hydrostatic pressure and the magnitude of the equivalent stress was lower than the yield stress of copper. Maximum principal stress of the Si chip in the TSV structure for the case without voids was lower than that of the bending strength of silicon. However, the level of the stresses in the Si chips should not be negligible for damages to Si chips. In case that void was present inside the TSV, stress concentration was occurred around the void in the TSV. The magnitude of the equivalent stress in the TSV was lower than the yield stress of copper. The magnitude of the maximum principal stress of the Si chip was lower than that of the bending strength of silicon. However, its level should not be negligible for damages to TSVs and Si chips. The stress on inner surfaces of Si chip was slightly reduced due to the presence of a void in the TSV. [DOI: 10.1115/1.4006515]

Norris–Landzberg Acceleration Factors and Goldmann Constants for SAC305 Lead-Free Electronics

Abstract: Goldmann constants and Norris–Landzberg acceleration factors for SAC305 lead-free solders have been developed based on principal component regression models (PCR) for reliability prediction and part selection of area-array packaging architectures under thermo-mechanical loads. Models have been developed in conjunction with stepwise regression methods for identification of the main effects. Package architectures studied include ball-grid array (BGA) packages mounted on copper-core and no-core printed circuit assemblies in harsh environments. The models have been developed based on thermomechanical reliability data acquired on copper-core and no-core assemblies in four different thermal cycling conditions. Packages with Sn3Ag0.5Cu solder alloy interconnects have been examined. The models have been developed based on perturbation of accelerated test thermomechanical failure data. Data have been gathered on nine different thermal cycle conditions with SAC305 alloys. The thermal cycle conditions differ in temperature range, dwell times, maximum temperature, and minimum temperature to enable development of constants needed for the life prediction and assessment of acceleration factors. Goldmann constants and the Norris–Landzberg acceleration factors have been benchmarked against previously published values. In addition, model predictions have been validated against validation datasets which have not been used for model development. Convergence of statistical models with experimental data has been demonstrated using a single factor design of experimental study for individual factors including temperature cycle magnitude, relative coefficient of thermal expansion, and diagonal length of the chip. The predicted and measured acceleration factors have also been computed and correlated. Good correlations have been achieved for parameters examined. Previously, the feasibility of using multiple linear regression models for reliability prediction has been demonstrated for flex-substrate BGA packages (Lall , 2004, “Thermal Reliability Considerations for Deployment of Area Array Packages in Harsh Environments,” Proceedings of the ITherm 2004, 9th Intersociety Conference on Thermal and Thermo-mechanical Phenomena, Las Vegas, Nevada, Jun. 1–4, pp. 259–267, Lall , 2005, “Thermal Reliability Considerations for Deployment of Area Array Packages in Harsh Environments,” IEEE Trans. Compon. Packag. Technol., 28 (3), pp. 457–466., flip-chip packages (Lall , 2005, “Decision-Support Models for Thermo-Mechanical Reliability of Leadfree Flip-Chip Electronics in Extreme Environments,” Proceedings of the 55th IEEE Electronic Components and Technology Conference, Orlando, FL, Jun. 1–3, pp. 127–136) and ceramic BGA packages (Lall , 2007, “Thermo-Mechanical Reliability Based Part Selection Models for Addressing Part Obsolescence in CBGA, CCGA, FLEXBGA, and Flip-Chip Packages,” ASME InterPACK Conference, Vancouver, British Columbia, Canada, Jul. 8–12, Paper No. IPACK2007-33832, pp. 1–18). The presented methodology is valuable in the development of fatigue damage constants for the application specific accelerated test datasets and provides a method to develop institutional learning based on prior accelerated test data.

Influence of Gap Height in Flip Chip Underfill Process With Non-Newtonian Flow Between Two Parallel Plates

Abstract: In this paper, the finite volume method (FVM) is used for the simulation of flip chip underfill process by considering non-Newtonian flow between two parallel plates that emulate the silicon die and the substrate. 3D model of two parallel plates of size 12.75 mm � 9.5 mm with gap heights of 5 lm, 15 lm, 25 lm, 35 lm, 45 lm, and 85 lm are developed and simulated by computational fluid dynamic (CFD) code, FLUENT 6.3.26. The flow is modeled by using power law model and volume of fluid (VOF) technique is applied for flow front tracking. The effect of change in height of the gap between the plates on the underfill process is mainly studied in the present work. It is observed that the gap height has significant influence on the melt filling time and pressure drop, as the gap height decreases filling time and pressure drop increase. The simulation results are compared with previous experimental results and found in good conformity. [DOI: 10.1115/1.4005914]

Die Bonding of High Power 808 nm Laser Diodes With Nanosilver Paste

Abstract: Conduction-cooled high power laser diodes have a variety of significant commercial, industrial, and military applications. For these devices to perform effectively, an appropriate die-attached material meeting specific requirements must be selected. In this study, nanosilver paste, a novel die-attached material, was used in packaging the 60 W 808 nm high power laser diodes. The properties of the laserdiodes operating in the continuous wave (CW) mode, including the characteristics of power-current-voltage (LIV), spectrum, near field, far field, near field linearity, spatial spectrum, and thermal impedance, were determined. In addition, destructive tests, including the die shear test, scanning acoustic microscopy, and the thermal rollover test, were conducted to evaluate the reliability of the die bonding ofthe 60 W 808 nm high power semiconductor laser with nanosilver paste. Thermal analyses of the laserdiodes operating at CW mode with different die-attached materials, indium solder, gold-tin solder andnanosilver paste, were conducted by finite element analysis (FEA). According to the result of the FEA, thenanosilver paste resulted in the lowest temperature in the laser diodes. The test results showed that thenanosilver paste was a very promising die-attached material in packaging high power semiconductorlaser.

From Chip to Cooling Tower Data Center Modeling: Chip Leakage Power and Its Impact on Cooling Infrastructure Energy Efficiency

Abstract: The power consumption of the chip package is known to vary with operating temperature, independently of the workload processing power. This variation is commonly known as chip leakage power, typically accounting for ~10% of total chip power consumption. The influence of operating temperature on leakage power consumption is a major concern for the information technology (IT) industry for design optimization where IT system power densities are steadily increasing and leakage power expected to account for up to ~50% of chip power in the near future associated with the reducing package size. Much attention has been placed on developing models of the chip leakage power as a function of package temperature, ranging from simple linear models to complex super-linear models. This knowledge is crucial for IT system designers to improve chip level energy efficiency and minimize heat dissipation. However, this work has been focused on the component level with little thought given to the impact of chip leakage power on entire data center efficiency. Studies on data center power consumption quote IT system heat dissipation as a constant value without accounting for the variance of chip power with operating temperature due to leakage power. Previous modeling techniques have also omitted this temperature dependent relationship. In this paper, we discuss the need for chip leakage power to be included in the analysis of holistic data center performance. A chip leakage power model is defined and its implementation into an existing multiscale data center energy model is discussed. Parametric studies are conducted over a range of system and environment operating conditions to evaluate the impact of varying degrees of chip leakage power. Possible strategies for mitigating the impact of leakage power are also illustrated in this study. This work illustrates that when including chip leakage power in the data center model, a compromise exists between increasing operating temperatures to improve cooling infrastructure efficiency and the increase in heat load at higher operating temperatures due to leakage power.

Characterization of Compressive Die Stresses in CBGA Microprocessor Packaging Due to Component Assembly and Heat Sink Clamping

Abstract: Microprocessor packaging in modern workstations and servers often consists of one or more large flip chip die that are mounted to a high performance ceramic chip carrier. The final assembly configuration features a complex stack up of flip chip area array solder interconnects, underfill, ceramic substrate, lid, heat sink, thermal interface materials (TIMs), second level ceramic ball grid array (CBGA) solder joints, organic printed circuit board, etc., so that a very complicated set of loads is transmitted to the microprocessor chip. Several trends in the evolution of this packaging architecture have exacerbated die stress levels including the transition to larger die, high coefficient of thermal expansion (CTE) ceramic substrates, lead free solder joints, higher levels of power generation, and larger heat sinks with increased clamping forces. Die stress effects are of concern due to several reasons including degradation of silicon device performance (mobility/speed), damage that can occur to the copper/low-k top level interconnect layers, and potential mechanical failure of the silicon in extreme cases. In this work, test chips containing piezoresistive stress sensors have been used to measure the buildup of mechanical stresses in a microprocessor die after various steps of the flip chip CBGA assembly process. The utilized (111) silicon test chips were able to measure the complete three-dimensional stress state at each sensor site being monitored by the data acquisition hardware. Special test fixtures were developed to eliminate any additional stresses due to clamping effects. The developed normal stresses are compressive (triaxial compression) across the die surface, with significant in-plane and out-of-plane (interfacial) shear stresses also present at the die corners. The compressive stresses increase with each assembly step (flip chip solder joint reflow, underfill dispense and cure, and lid attachment). The experimental observations from this study show clearly that large area array flip chips are subjected to relatively large compressive in-plane normal stresses after solder reflow. We also observed that the majority of the die compressive stress is accumulated during the underfilling assembly step. Typical increases in the stress magnitude were on the order of 300% (relative to the stresses due to solder joint reflow only). As a general “rule of thumb,” approximately two-thirds (∼66%) of the final die stress magnitudes were observed to be developed during the underfill dispense and cure, with the second largest contribution coming from the die attachment, and the smallest contribution coming from lid attachment. The experimental test chip stress measurements were correlated with finite element simulations of the packaging process. A sequential modeling approach has been utilized to predict the build-up of compressive stress. The utilized method incorporates precise thermal histories of the packaging process, element creation, and nonlinear temperature and time dependent material properties. With suitable detail in the models, excellent correlation has been obtained with the sensor data throughout all packaging processes. Finally, CBGAs with the stress sensing chips were soldered to organic printed circuit board (PCB) test boards. A simulated heat sink loading applied, and the stresses were measured as a function of the clamping force. Compressive stress changes of up to − 60 MPa were observed for a 1000 N applied clamping force. The experimental test chip stress measurements were correlated with finite element simulations of the clamping process. With suitable detail in the models, excellent correlation has been obtained for the stress changes occurring during simulated heat sink clamping.

From Chip to Cooling Tower Data Center Modeling: Influence of Air-Stream Containment on Operating Efficiency

Abstract: In the drive to enhance data center energy efficiency, much attention has been placed on the prospect of airflow containment in hot-aisle cold-aisle raised floor arrangements. Such containment prevents airflow recirculation, eliminating the mixing effects of the hot and cold air streams that can cause an undesirable temperature rise at the inlet of the equipment racks. The intuitive assessment of the industry has been that the elimination of such mixing effects increases the energy efficiency of the data center cooling system by enabling delivery of air at higher inlet temperatures, thus reducing the amount of infrastructure cooling required. This paper employs an end-to-end modeling approach to analyze the effect of air stream containment in the computer room and its impact on the holistic system efficiency. Dimensionless heat index parameters are employed to characterize the effects of containment, recirculation, and mixing within the computer room environment. The extent of recirculation is shown to primarily influence the operation of the rack and computer room air conditioning (CRAC) level cooling systems, with the chiller systems also impacted. The overall effect on the complete cooling system performance and data center efficiency requires balancing of these effects. Through this model analysis, it is shown that containment may negatively impact overall energy efficiency in some circumstances, and that recirculation may actually be beneficial to overall energy efficiency under certain system dependent operating thresholds.

Minimization of the Local Residual Stress in 3D Flip Chip Structures by Optimizing the Mechanical Properties of Electroplated Materials and the Alignment Structure of TSVs and Fine Bumps

Abstract: Since the thickness of stacked silicon chips in 3D integration has been thinned to less than 100 μm, the local thermal deformation of the chips has increased drastically because of the decrease of the flexural rigidity of the thinned chips. The clear periodic thermal deformation and thus, the local distribution of thermal residual stress appears in the stacked chips due to the periodic alignment of metallic bumps, and they sometimes deteriorate mechanical and electrical reliability of electronic products. In this paper, the dominant structural factors of the local residual stress in a silicon chip are investigated quantitatively based on the results of a three-dimensional finite element analysis and the measurement of the local residual stress in a chip using stress sensor chips. The piezoresistive strain gauges were embedded in the sensor chips. The length of each gauge was 2 μm, and an unit cell consisted of four gauges with different crystallographic directions. This alignment of the strain gauges enables us to measure the tensor component of three-dimensional stress fields separately. Test flip chip substrates were made of silicon chip on which the area-arrayed tin/copper bumps were electroplated. The width of a bump was fixed at 200 μm, and the bump pitch was varied from 400 μm to 1000 μm. The thickness of the copper bump was about 40 μm and that of tin layer was about 10 μm. This tin layer was used for the formation of rigid joint by alloying it with copper interconnection formed on a stress sensing chip. The measured amplitude of the residual stress increased from about 30 MPa to 250 MPa depending on the combination of materials such as bump, underfill, and interconnections. It was confirmed that both the material constant of underfill and the alignment structure of fine bumps are the dominant factors of the local deformation and stress of a silicon chip mounted on area-arrayed metallic bumps. It was also confirmed that not only the control of mechanical properties of electroplated copper thin films, but also the hound’s-tooth alignment of a through silicon via and a bump are indispensable for minimizing the packaging-induced stress in the three-dimensionally mounted chips. This test chip is very effective for evaluating the packaging-process-induced stress in 3D stacked chips quantitatively.

Effect of Design Parameters on Drop Test Performance of Wafer Level Chip Scale Packages

Abstract: Today’s consumer market demands electronics that are smaller, faster, and cheaper. To cater to these demands, novel materials, new designs, and new packaging technologies are introduced frequently. Wafer level chip scale package (WLCSP) is one of the emerging package technologies that have the key advantages of reduced cost and smaller footprint. The portable consumer electronics are frequently dropped; hence, the emphasis of reliability is shifting toward the study of effects of mechanical shock loading increasingly. Mechanical loading typically induces brittle fractures (also known as intermetallic failures) between the solder bumps and the bond pads at the silicon die side. This type of failure mechanism is typically characterized by the board level drop test. WLCSP is a variant of the flip-chip interconnection technique. In WLCSPs, the active side of the die is inverted and connected to the printed circuit board (PCB) by solder balls. The size of these solder balls is typically large enough (300 μm pre-reflow for 0.5-mm pitch and 250 μm pre-reflow for 0.4-mm pitch) to avoid the use of underfill that is required for the flip-chip interconnects. Several variations are incorporated in the package design parameters to meet the performance, reliability, and footprint requirements of the package assembly. The design parameters investigated in this effort are solder ball compositions with different silver (Ag) contents, backside lamination with different thicknesses, WLCSP type—direct and redistribution layer (RDL), bond pad thickness, and sputtered versus electroplated under bump metallurgy (UBM) deposition methods for 8 × 8, 9 × 9, and 10 × 10 array sizes. The test vehicles built using these design parameters were drop tested using Joint Electron Devices Engineering Council (JEDEC) recommended test boards and conditions as per JESD22-B11. Cross-sectional analysis was used to identify, confirm, and segregate the intermetallic and bulk solder failures. The objective of this research was to quantify the effects and interactions of WLCSP design parameters through drop test. The drop test data were collected and treated as a right censored data. Further, it was analyzed by fitting empirical distributions using the grouped and ungrouped data approach. Data analysis showed that design parameters had a significant effect on the drop performance and played a vital role in influencing the package reliability.

Accelerated Temperature and Voltage Stress Tests of Embedded Planar Capacitors With Epoxy–BaTiO3 Composite Dielectric

Abstract: Accelerated temperature and voltage stress tests were conducted on embedded planar capacitors with epoxy–BaTiO3 composite dielectric. The failure modes were found to be a sudden increase in the leakage current across the capacitor dielectric and a gradual decrease in the capacitance. The failure mechanisms associated with these failure modes were investigated by performing data analysis and failure analysis. The time-to-failure as a result of a sudden increase in the leakage current was modeled using the Prokopowicz equation. The values of constants of the Prokopowicz equation, n and Ea , were determined for the epoxy–BaTiO3 composite. The degradation in capacitance was modeled by performing regression analysis. The time-to-failure and degradation models can be used for the qualification tests of embedded planar capacitors, for the development of new composite dielectric materials, and to improve the manufacturing processes of these capacitors.

Numerical Simulations of Electromigration and Stressmigration Driven Void Evolution in Solder Interconnects

Abstract: Understanding the effect of high current density on void formation and growth and relating the size of the void to the resulting electrical/mechanical failure is a critical need at the present time to ensure reliable functioning of flip-chip packages. In general, toward this end, the modeling and simulation of geometrical evolution of current induced voids have been relatively few. Simulations considering the coupled effects of mass transport through mechanisms of surface and bulk diffusion under the influence of electrical, thermal, and stress fields in solder joints leading to eventual electromigration failure do not appear to be common. In this study, we develop a phase field model for the evolution of voids under electrical, thermal, and stress fields in a flip-chip solder interconnect. We derive the equations of motion for the void accounting for energetic contributions from the active factors of surface energy, stress, and electric potential, considering both surface diffusion and transfer of the material through the bulk of the material. We describe the implementation of this model using a finite element code written in the PYTHON language, coupled with a commercial finite element solver from which we obtain the electrical, thermal, and stress fields driving the void motion. We demonstrate the implemented methodology through simulations of void evolution in flip-chip solder joints under the effects of mechanical/electrical fields and surface/bulk diffusion. [DOI: 10.1115/1.4006707]

Reliability Assessment of Preloaded Solder Joint Under Thermal Cycling

Abstract: The ever increasing power density in modern semiconductor devices requires heat dissi-pation solution such as heat sink to remove heat away from the device. A compressiveloading is usually applied to reduce the interfacial thermal resistance between packageand heat sink. In this paper, both experimental approaches and numerical modeling wereemployed to study the effect of compressive loading on the interconnect reliability underthermal cycling conditions. A special loading fixture which simulated the heat sink wasdesigned to apply compressive loading to the package. The JEDEC standard thermalcycle tests were performed and the resistance of daisy chained circuits was in situ meas-ured. The time to crack initiation and time to permanent failure were identified separatelybased on in situ resistance measurement results. Failure analysis has been performed toidentify the failure modes of solder joint with and without the presence of compressiveloading. A finite element based thermal-fatigue life prediction model for SAC305 solderjoint under compressive loading was also developed to understand the thermal-fatiguecrack behaviors of solder joint and successfully validated with the experimental results.[DOI: 10.1115/1.4007674]

Experimental Investigation by Speckle Interferometry of Solder Joint Failure Under Thermomechanical Load Aggravated by Boundary Conditions at Board Level

Abstract: Reliability of electronic assemblies at board level and solder joint integrity depend upon the stress applied to the assembly The stress is often of thermomechanical or of vibrational nature In both cases, the behavior of the assembly is strongly influenced by the mechanical boundary conditions created by the printed circuit board (PCB) to casing fasteners In many previously published papers, the conditions imposed to the fasteners are mostly aiming at an increase of the fundamental frequency and a decrease of static or dynamic displacement values characterizing the deformation These conditions aim at reducing the fatigue in different parts of these assemblies In the photomechanics laboratory of INSA Rouen, the origins of solder joint failure have been investigated by means of full-field measurements of the flexure deformation induced by vibrations or by forced thermal convection The measurements were done both at a global level for the whole printed circuit board assembly (PCBA) and at a local level at the solder joints where failure was reported The experimental technique used was phase-stepped laser speckle interferometry This technique has a submicrometer sensitivity with respect to out-of-plane deformations induced by bending and its use is completely nonintrusive Some of the results were comforted by comparison with a numerical finite elements model The experimental results are presented either as time-average holographic fringe patterns, as in the case of vibrations, or as wrapped phase patterns, as in the case of deformation under thermomechanical stress Both types of fringe patterns may be processed so as to obtain the explicit out-of-plane static deformation (or vibration amplitude) maps Experimental results show that the direct cause of solder joint failure may be a high local PCB curvature produced by a supplementary fastening screw intended to reduce displacements and increase fundamental frequency The curvature is directly responsible for tensile stress appearing in the leads of a large quad flat pack (QFP) component and for shear in the corresponding solder joints The general principle of increasing the fundamental frequency and decreasing the static or dynamic displacement values has to be checked against the consequences on the PCB curvature near large electronic devices having high stiffness