Journal of Semiconductor Technology and Science 

About: Journal of Semiconductor Technology and Science is an academic journal published by Institute of Electronics Engineers of Korea. The journal publishes majorly in the area(s): CMOS & Amplifier. It has an ISSN identifier of 1598-1657. Over the lifetime, 1129 publications have been published receiving 5849 citations. The journal is also known as: JSTS.

New Memristor-Based Crossbar Array Architecture with 50-% Area Reduction and 48-% Power Saving for Matrix-Vector Multiplication of Analog Neuromorphic Computing

Abstract: In this paper, we propose a new memristorbased crossbar array architecture, where a single memristor array and constant-term circuit are used to represent both plus-polarity and minus-polarity matrices This is different from the previous crossbar array architecture which has two memristor arrays to represent plus-polarity and minus-polarity connection matrices, respectively The proposed crossbar architecture is tested and verified to have the same performance with the previous crossbar architecture for applications of character recognition For areal density, however, the proposed crossbar architecture is twice better than the previous architecture, because only single memristor array is used instead of two crossbar arrays Moreover, the power consumption of the proposed architecture can be smaller by 48% than the previous one because the number of memristors in the proposed crossbar architecture is reduced to half compared to the previous crossbar architecture From the high areal density and high energy efficiency, we can know that this newly proposed crossbar array architecture is very suitable to various applications of analog neuromorphic computing that demand high areal density and low energy consumption

Assessment of Ambipolar Behavior of a Tunnel FET and Influence of Structural Modifications

Abstract: In the present work, comprehensive investigation of the ambipolar characteristics of two silicon (Si) tunnel field-effect transistor (TFET) architectures (i.e. p-i-n and p-n-p-n) has been carried out. The impact of architectural modifications such as heterogeneous gate (HG) dielectric, gate drain underlap (GDU) and asymmetric source/drain doping on the ambipolar behavior is quantified in terms of physical parameters proposed for ambipolarity characterization. Moreover, the impact on the miller capacitance is also taken into consideration since ambipolarity is directly related to reliable logic circuit operation and miller capacitance is related to circuit performance.

Two Phase Clocked Adiabatic Static CMOS Logic and its Logic Family

Abstract: This paper proposes a two-phase clocked adiabatic static CMOS logic (2PASCL) circuit that utilizes the principles of adiabatic switching and energy recovery. The low-power 2PASCL circuit uses two complementary split-level sinusoidal power supply clocks whose height is equal to V dd . It can be directly derived from static CMOS circuits. By removing the diode from the charging path, higher output amplitude is achieved and the power consumption of the diode is eliminated. 2PASCL has switching activity that is lower than dynamic logic. We also design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology. From the simulation results, we find that 2PASCL 4-inverter chain logic can save up to 79% of dissipated energy as compared to that with a static CMOS logic at transition frequencies of 1 to 100 ㎒. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

On-Chip Spiral Inductors for RF Applications: An Overview

Abstract: Passive components are indispensable in the design and development of microchips for high-frequency applications. Inductors in particular are used frequently in radio frequency (RF) Ie's such as low-noise amplifiers and oscillators. This paper gives a broad overview on the on-chip spiral inductors. The design concept and modeling approach of the typical square-shaped spiral inductor are first addressed. This is followed by the discussions of advanced structures for the enhancement of inductor performance. Research works reported in the literature are summarized to aid the understanding of the recent development of such devices.

2-D Large Inverse Transform (16×16, 32×32) for HEVC (High Efficiency Video Coding)

Abstract: This paper proposes a 16×16 and 32×32 inverse transform architecture for HEVC (High Efficiency Video Coding). HEVC large transform of 16×16 and 32×32 suffers from huge computational complexity. To resolve this problem, we proposed a new large inverse transform architecture based on hardware reuse. The processing element is optimized by exploiting fully recursive and regular butterfly structure. To achieve low area, the processing element is implemented by shifters and adders without multiplier. Implementation of the proposed 2-D inverse transform architecture in 0.18 ㎛ technology shows about 300 ㎒ frequency and 287 Kgates area, which can process 4K (3840×2160)@ 30 fps image.