Showing papers in "Journal of Semiconductor Technology and Science in 2011"
TL;DR: In this paper, the effect of ambipolar behavior on the device performance was evaluated as a function of device structure, gate oxide thickness, supply voltage, drain doping concentration and body doping concentration.
Abstract: The ambipolar behavior of tunneling field- effect transistors (TFETs) has been investigated quantitatively by introducing a novel parameter: ambipolarity factor (ν). It has been found that the malfunction of TFET can result from the ambipolar state which is not on- or off- state. Therefore, the effect of ambipolar behavior on the device performance should be parameterized quantitatively, and this has been successfully evaluated as a function of device structure, gate oxide thickness, supply voltage, drain doping concentration and body doping concentration by using ν.
59 citations
TL;DR: In this article, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated, and it is shown that high performance (HP) logic technology can be achieved by the proposed device.
Abstract: In this work, a tunneling field-effect transistor (TFET) based on heterojunctions of compound and Group IV semiconductors is introduced and simulated. TFETs based on either silicon or compound semiconductors have been intensively researched due to their merits of robustness against short channel effects (SCEs) and excellent subthreshold swing (SS) characteristics. However, silicon TFETs have the drawback of low on-current and compound ones are difficult to integrate with silicon CMOS circuits. In order to combine the high tunneling efficiency of narrow bandgap material TFETs and the high mobility of III-V TFETs, a Type-I heterojunction tunneling field- effect transistor (I-HTFET) adopting Ge-AlxGa1-xAs- Ge system has been optimized by simulation in terms of aluminum (Al) composition. To maximize device performance, we considered a nanowire structure, and it was shown that high performance (HP) logic technology can be achieved by the proposed device. The optimum Al composition turned out to be around 20% (x=0.2). Index Terms—Tunneling field-effect transistor (TFET), Type-I heterojunction, narrow bandgap material, high mobility, simulation, nanowire, high performance (HP) logic technology
28 citations
TL;DR: The FLASH controller to manage shrink effect leads to speed and current issues will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization.
Abstract: It is progressing as new advents and remarkable developments of mobile device every year. On the upper line reason, NAND FLASH large density memory demands which can be stored into portable devices have been dramatically increasing. Therefore, the cell size of the NAND Flash memory has been scaled down by merely 50% and has been doubling density each per year. [1] However, side effects have arisen the cell distribution and reliability characteristics related to coupling interference, channel disturbance, floating gate electron retention, write-erase cycling owing to shrinking around 20㎚ technology. Also, FLASH controller to manage shrink effect leads to speed and current issues. In this paper, It will be introduced to solve cycling, retention and fail bit problems of sub-deep micron shrink such as Virtual negative read used in moving read, randomization. The characteristics of retention, cycling and program performance have 3 K per 1 year and 12.7 MB/s respectively. And device size is 179.32 ㎟ (16.79 ㎜ × 10.68 ㎜) in 3 metal 26 ㎚ CMOS.
21 citations
TL;DR: The T-shape stepped impedance resonators are adopted for the design of microstrip bandpass filters for wide harmonics suppression and the applicable return losses for both frequency bands and a wide stopband better than 17 dB up to 20 GHz have been obtained.
Abstract: In this paper, the T-shape stepped impedance resonators are adopted for the design of microstrip bandpass filters for wide harmonics suppression. The proposed filters are operated at the center frequency of 2.44 GHz and 5.20 GHz, respectively. These bandpass filters have been also applied for a high performance diplexer. The insertion losses at the center frequencies of 2.44 and 5.20 GHz are 1.23 and 1.18, respectively. The applicable return losses for both frequency bands and a wide stopband better than 17 dB up to 20 GHz have been obtained.
20 citations
TL;DR: Experimental results show that the proposed reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems reduces on-chip area, execution time and power consumption when compared with the conventional CGRA-based architectures.
Abstract: Coarse-grained reconfigurable architecture (CGRA) based embedded systems aims to achieve high system performance with sufficient flexibility to map a variety of applications. However, the CGRA has been considered as prohibitive one due to its significant area/power overhead and performance bottleneck. In this work, I propose reconfigurable multi-array architecture to reduce power/area and enhance performance in configurable embedded systems. The CGRA-based embedded systems that consist of hierarchical configurable computing arrays with varying size and communication speed were examined for multimedia and other applications. Experimental results show that the proposed approach reduces on-chip area by 22%, execution time by up to 72% and reduces power consumption by up to 55% when compared with the conventional CGRA-based architectures.
16 citations
TL;DR: This paper describes 250-Mb/s fiber optic transmitter and receiver ICs for plastic optical fiber applications using a 0.18-μm CMOS technology that converts non-return-to-zero digital data into 650-nm visible-red light signal and recovers the digital data from the incident light signal through up to 50-m plastic optical Fiber.
Abstract: This paper describes 250-Mb/s fiber optic transmitter and receiver ICs for plastic optical fiber applications using a 0.18-μm CMOS technology. Simple signal and light detection schemes are introduced for power reduction in sleep mode. The transmitter converts non-return-to-zero digital data into 650-nm visible-red light signal and the receiver recovers the digital data from the incident light signal through up to 50-m plastic optical fiber. The transmitter and receiver ICs occupy only 0.62 mm 2 of area including electrostatic discharge protection diodes and bonding pads. The transmitter IC consumes 23 mA with 20 mA of LED driving currents, and the receiver IC consumes 16 mA with 4 mA of output driving currents at 250 Mb/s of data rate from a 3.3-V supply in active mode. In sleep mode, the transmitter and receiver ICs consume only 25 μA and 40 μA, respectively.
15 citations
TL;DR: A 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell is designed.
Abstract: In this paper, we design a 1-kb OTP (Onetime programmable) memory IP in consideration of BCD process based EM (Electro-migration) and resistance variations of eFuse. We propose a method of precharging BL to VSS before activation of RWL (Read word-line) and an optimized design of read NMOS transistor to reduce read current through a non-programmed cell. Also, we propose a sensing margin test circuit with a variable pull-up load out of consideration for resistance variations of programmed eFuse. Peak current through the nonprogrammed eFuse is reduced from 728 ㎂ to 61 ㎂ when a simulation is done in the read mode. Furthermore, BL (Bit-line) sensing is possible even if sensed resistance of eFuse has fallen by about 9 ㏀ in a wafer read test through a variable pull-up load resistance of BL S/A (Sense amplifier).
14 citations
TL;DR: An effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage that uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation.
Abstract: Higher integrated density in 3D ICs also brings the difficulties of routing, which can cause the routing failure or re-design from beginning. Hence, precise congestion estimation at the early physical design stage such as floorplan is beneficial to reduce the total design time cost. In this paper, an effective estimation method of routing congestion is proposed for 3D ICs at floorplan stage. This method uses synthesized virtual signal nets, power/ground network and clock network to achieve the estimation. During the synthesis, the TSV location is also under consideration. The experiments indicate that our proposed method had small difference with the estimation result got at the post-placement stage. Furthermore, the comparison of congestion maps obtained with our method and global router demonstrates that our estimation method is able to predict the congestion hot spots accurately.
13 citations
TL;DR: In this paper, two competing mechanisms determining drain current of tunneling field-effect transistors (TFETs) have been investigated such as band-to-band tunneling and drift.
Abstract: In this paper, two competing mechanisms determining drain current of tunneling field-effect transistors (TFETs) have been investigated such as band-to-band tunneling and drift. Based on the results, the characteristics of TFETs have been discussed in the tunneling-dominant and drift- dominant region.
12 citations
TL;DR: In this paper, a comparative study of two capacitance methods to measure the effective channel length in deep-submicron MOSFETs has been made in detail, and it was shown that the capacitance method removing the parasitic capacitance in the accumulation region extracts a more accurate estimation of channel length than the method removing that at zero gate voltage.
Abstract: A comparative study of two capacitance methods to measure the effective channel length in deep-submicron MOSFETs has been made in detail. Since the reduction of the overlap capacitance in the accumulation region is smaller than the addition of the inner fringe capacitance at zero gate voltage, the capacitance method removing the parasitic capacitance in the accumulation region extracts a more accurate effective channel length than the method removing that at zero gate voltage.
11 citations
TL;DR: In this paper, a two-dimensional analytical model for deriving the threshold voltage of a short channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested.
Abstract: A two-dimensional analytical model for deriving the threshold voltage of a short channel fully depleted (FD) cylindrical/surrounding gate MOSFET (CGT/SGT) is suggested. By taking into account the lateral variation of the surface potential, introducing the natural length expression, and using the Bessel functions of the first and the second kinds of order zero, we can derive potentials in the gate oxide layer and the silicon core fully two-dimensionally. Making use of these potentials, the minimum surface potential can be obtained to derive the threshold voltage as a closed-form expression in terms of various device parameters and applied voltages. Obtained results can be used to explain the drain-induced threshold voltage roll-off of a CGT/SGT in a unified manner.
TL;DR: In this paper, a flip-flop based approach for optical failure analysis was proposed, consisting of a sense amplifier and a photon-emitting device, which can be used even with deep- submicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared region of the spectrum.
Abstract: In this paper, we have proposed a new approach for optical failure analysis which employs a CMOS photon-emitting circuitry, consisting of a flip- flop based on a sense amplifier and a photon-emitting device. This method can be used even with deep- submicron processes where conventional optical failure analyses are difficult to use due to the low sensitivity in the near infrared (NIR) region of the spectrum. The effectiveness of our approach has been proved by the failure analysis of a prototype designed and fabricated in 0.18 μm CMOS process.
TL;DR: In this paper, a simple variable gain amplifier (VGA) structure that shows an inherently dB-linear gain control property was proposed. But the performance of the two-stage VGA was limited to a gain error in the range of ± 0.4 dB.
Abstract: This paper introduces a simple variable gain amplifier (VGA) structure that shows an inherently dB-linear gain control property. Requiring no additional components for dB-linear control, the structure is compact and power efficient. The designed two-stage VGA shows a gain control range of 60dB with the gain error in the range of ±0.4 dB. The power consumption including the output buffer is 20.4 mW from 1.2 V supply voltage with bandwidth of 630 MHz. The prototype was fabricated in a 0.13 m CMOS process and the VGA core occupies 0.06 mm 2
TL;DR: In this paper, a 2D analytical model for the potential distribution and threshold voltage of short-channel ion-implanted GaAs MESFETs operating in the sub-threshold regime has been presented.
Abstract: A two-dimensional (2D) analytical model for the potential distribution and threshold voltage of short-channel ion-implanted GaAs MESFETs operating in the sub-threshold regime has been presented. A double-integrable Gaussian-like function has been assumed as the doping distribution profile in the vertical direction of the channel. The Schottky gate has been assumed to be semi-transparent through which optical radiation is coupled into the device. The 2D potential distribution in the channel of the shortchannel device has been obtained by solving the 2D Poisson’s equation by using suitable boundary conditions. The effects of excess carrier generation due to the incident optical radiation in channel region have been included in the Poisson’s equation to study the optical effects on the device. The potential function has been utilized to model the threshold voltage of the device under dark and illuminated conditions. The proposed model has been verified by comparing the theoretically predicted results with simulated data obtained by using the commercially available ATLAS™ 2D device simulator.
TL;DR: This paper describes a reset-free delaylocked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector, that neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal.
Abstract: This paper describes a reset-free delaylocked loop (DLL) for a memory controller application, with the aid of a hysteresis coarse lock detector. The coarse lock loop in the proposed DLL adjusts the delay between input and output clock within the pull-in range of the main loop phase detector. In addition, it monitors the main loop’s lock status by dividing the input clock and counting its multiphase edges. Moreover, by using hysteresis, it controls the coarse lock range, thus reduces jitter. The proposed DLL neither suffers from harmonic lock and stuck problems nor needs an external reset or start-up signal. In a 0.13-㎛ CMOS process, postlayout simulation demonstrates that, even with a switching supply noise, the peak-to-peak jitter is less than 30 ps over the operating range of 500-1200 ㎒. It occupies 0.04 ㎟ and dissipates 16.6 ㎽ at 1.2 ㎓.
TL;DR: A low noise and low power RF front-end for 5.8 ㎓ DSRC (Dedicated Short Range Communication) receiver is presented and a single-to-differential LNA with capacitive cross coupled pair is proposed.
Abstract: A low noise and low power RF front-end for 5.8 ㎓ DSRC (Dedicated Short Range Communication) receiver is presented. The RF front-end is composed of a single-to-differential two-stage LNA and a Gilbert down-conversion mixer. In order to remove an external balun and 5.8 ㎓ LC load tuning circuit, a single-to-differential LNA with capacitive cross coupled pair is proposed. The RF front-end is fabricated in a 0.13 ㎛ CMOS process and draws 7.3 ㎃ from a 1.2 V supply voltage. It shows a voltage gain of 40 ㏈ and a noise figure (NF) lower than 4.5 dB over the entire DSRC band.
TL;DR: The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 V p-p at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology.
Abstract: This paper proposes a 6b 1.2 GS/s 47.8 ㎽ 0.17 ㎟ 65 ㎚ CMOS ADC for high-rate wireless personal area network systems. The proposed ADC employs a source follower-free flash architecture with a wide input range of 1.0 V p-p at a 1.2 V supply voltage to minimize power consumption and high comparator offset effects in a nanometer CMOS technology. The track-and-hold circuits without source followers, the differential difference amplifiers with active loads in pre-amps, and the output averaging layout scheme properly handle a wide-range input signal with low distortion. The interpolation scheme halves the required number of pre-amps while three-stage cascaded latches implement a skew-free GS/s operation. The two-step bubble correction logic removes a maximum of three consecutive bubble code errors. The prototype ADC in a 65 ㎚ CMOS demonstrates a measured DNL and INL within 0.77 LSB and 0.98 LSB, respectively. The ADC shows a maximum SNDR of 33.2 ㏈ and a maximum SFDR of 44.7 ㏈ at 1.2 GS/s. The ADC with an active die area of 0.17 ㎟ consumes 47.8 ㎽ at 1.2 V and 1.2 GS/s.
TL;DR: This paper presents a high-speed QR decomposition architecture for the multi-input-multi- output (MIMO) receiver based on Givens rotation that achieves 34.83% speed-up over the Compact CORDIC based Architecture for the 4 × 4 matrix decomposition.
Abstract: This paper presents a high-speed QR decomposition architecture for the multi-input-multi- output (MIMO) receiver based on Givens rotation. Under fast-varying channel, since the inverse matrix calculation has to be performed frequently in MIMO receiver, a high performance and low latency QR decomposition module is highly required. The proposed QR decomposition architecture is composed of Sign-Select Lookahead (SSL) coordinate rotation digital computer (CORDIC). In the SSL-CORDIC, the sign bits, which are computed ahead to select which direction to rotate, are used to select one of the last iteration results, therefore, the data dependencies on the previous iterations are efficiently removed. Our proposed QR decomposition module is implemented using TSMC 0.25 µm CMOS process. Experimental results show that the proposed QR architecture achieves 34.83% speed-up over the Compact CORDIC based architecture for the 4 × 4 matrix decomposition.
TL;DR: A new Verilog-A current-voltage model for multi-level-cell PCRAMs which can describe the PCRAM operation not only in full SET and RESET states but also in the partial resistance states and 3 PCRAM operating regions are unified into one equation in this model.
Abstract: In this paper, we propose a new Verilog-A current-voltage model for multi-level-cell PCRAMs. This model can describe the PCRAM operation not only in full SET and RESET states but also in the partial resistance states. And, 3 PCRAM operating regions of SET-RESET, Negative Differential Resistance, and strong-ON are unified into one equation in this model thereby any discontinuity that may introduce a convergence problem cannot be found in the new PCRAM model. The percentage error between the measured data and this model is as small as 7.4% on average compared to 60.1% of the previous piecewise model. The parameter extraction which is embedded in the Verilog-A code can be done automatically.
TL;DR: A smart bus arbiter is introduced to adjust the priority adaptively the QoS (Quality of Service) control of the decoding process to reduce the requirement of the bandwidth for the memory bus.
Abstract: H.264 decoders usually have pipeline architecture by a macroblock or a 4 × 4 sub-block. The period of the pipeline is usually fixed to guarantee the operation in the worst case which results in many idle cycles and higher data bandwidth. Adaptive pipeline architecture for H.264 decoders has been proposed for efficient decoding and lower the requirement of the bandwidth for the memory bus. However, it requires a controller for the adaptive priority control to utilize the advantage. We propose a smart bus arbiter that replaces the controller. It is introduced to adjust the priority adaptively the QoS (Quality of Service) control of the decoding process. The smart arbiter can be integrated the arbiter of bus systems and it works when certain conditions are met so that it does not affect the original functions of the arbiter. An H.264 decoder using the proposed architecture is designed and implemented to verify the operation using an FPGA.
TL;DR: In this paper, a drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: gm 1, gm 2, gm 3, and figure-of-merit (FOM) metrics; V IP2, V IP3, IIP3 and I-dB compression point, has been obtained.
Abstract: In this present paper, a comprehensive drain current model incorporating the effects of channel length modulation has been presented for multi-layered gate material engineered trapezoidal recessed channel (MLGME-TRC) MOSFET and the expression for linearity performance metrics, i.e. higher order transconductance coefficients: gm 1 , gm 2 , gm 3 , and figure-of-merit (FOM) metrics; V IP2 , V IP3 , IIP3 and I-dB compression point, has been obtained. It is shown that, the incorporation of multi-layered architecture on gate material engineered trapezoidal recessed channel (GME-TRC) MOSFET leads to improved linearity performance in comparison to its conventional counterparts trapezoidal recessed channel (TRC) and rectangular recessed channel (RRC) MOSFETs, proving its efficiency for low-noise applications and future ULSI production. The impact of various structural parameters such as variation of work function, substrate doping and source/drain junction depth (X j ) or negative junction depth (NJD) have been examined for GME- TRC MOSFET and compared its effectiveness with MLGME-TRC MOSFET. The results obtained from proposed model are verified with simulated and experimental results. A good agreement between the results is obtained, thus validating the model.
TL;DR: A framework for custom instruction generation considering both area constraints and resource sharing is presented and how to speed up the process through pruning and library-based design space exploration is presented.
Abstract: Extensible processors provide an efficient mechanism to boost the performance of the whole system without losing much flexibility. However, due to the intense demand of low cost and power consumption, customizing an embedded system has been more difficult than ever. In this paper, we present a framework for custom instruction generation considering both area constraints and resource sharing. We also present how we can speed up the process through pruning and library-based design space exploration.
TL;DR: In this paper, a physics-based SPICE model of amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) is presented and demonstrated using Verilog-A. As key physical parameter, subgap density-of-states (DOS) is extracted and used for calculating the electric potential, carrier density, and mobility along the depth direction of active thin-filters.
Abstract: In this work, we report the physics-based SPICE model of amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) and demonstrate the SPICE simulation of amorphous InGaZnO (a- IGZO) TFT inverter by using Verilog-A. As key physical parameter, subgap density-of-states (DOS) is extracted and used for calculating the electric potential, carrier density, and mobility along the depth direction of active thin-film. It is confirmed that the proposed DOS-based SPICE model can successfully reproduce the voltage transfer characteristic of a-IGZO inverter as well as the measured I-V characteristics of a-IGZO TFTs within the average error of 6% at VDD=20 V.
TL;DR: A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application and is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC.
Abstract: A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application. The proposed 10-bit dual sampling capacitive DAC topology reduces switching energy by 62% compared with 10-bit conventional SAR ADC. Also, it is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC. The proposed SAR ADC is fabricated in 0.18 ㎛ 1P6M CMOS technology and occupies 1.17 ㎟ including pads. It dissipates only 1.1 ㎼ with 1 V supply voltage while operating at 100 kS/s.
TL;DR: In this article, a 144 GHz divide-by-2 injection locked frequency divider (ILFD) with inductive feedback developed in a commercial 90-nm Si RFCMOS technology was demonstrated.
Abstract: This paper presents a 144 GHz divide-by-2 injection locked frequency divider (ILFD) with inductive feedback developed in a commercial 90-nm Si RFCMOS technology. It was demonstrated that division-by-2 operation is achieved with input power down to -12 dBm, with measured locking range of 0.96 GHz (144.18 - 145.14 GHz) at input power of -3 dBm. To the authors' best knowledge, this is the highest operation frequency for ILFD based on a 90- nm CMOS technology. From supply voltage of 1.8 V, the circuit draws 5.7 mA including both core and buffer. The fabricated chip occupies 0.54 mm × 0.69 mm including the DC and RF pads.
TL;DR: A new programmable compensation circuit (PCC) for a System-on-Chip (SoC) that automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation.
Abstract: This paper presents a new programmable compensation circuit (PCC) for a System-on-Chip (SoC). The PCC is integrated with O.18-J.1m BiCMOS SiGe technology. It consists of RF Design-for-Testability (DFT) circuit, Resistor Array Bank (RAB) and digital signal processor (DSP). To verify performance of the PCC we built a 5-GHz low noise amplifier (LNA) with an on-chip RAB using the same technology. Proposed circuit helps it to provide DC output voltages, hence, making the RF system chain automatic. It automatically adjusts performance of an LNA with the processor in the SoC when it goes out of the normal range of operation. The PCC also compensates abnormal operation due to the unusual PVT (Process, Voltage and Thermal) variations in RF circuits.
TL;DR: In this paper, a compact model of gatevoltage-dependent quantum effects in short-channel surrounding-gate (SG) MOSFETs is presented. But the model is based on a two-dimensional (2-D) analytical solution of Poisson's equation using cylindrical coordinates.
Abstract: In this paper, we present a compact model of gate-voltage-dependent quantum effects in shortchannel surrounding-gate (SG) metal-oxide-semiconductor field-effect transistors (MOSFETs). We based the model on a two-dimensional (2-D) analytical solution of Poisson’"s equation using cylindrical coordinates. We used the model to investigate the electrostatic potential and current sensitivities of various gate lengths (Lg) and radii (R). Schrodinger’"s equation was solved analytically for a one-dimensional (1-D) quantum well to include quantum effects in the model. The model takes into account quantum effects in the inversion region of the SG MOSFET using a triangular well. We show that the new model is in excellent agreement with the device simulation results in all regions of operation.
TL;DR: In this article, a novel type of optical plasma process monitoring system, called plasma eyes chromatic system (PECSTM), is introduced for the purpose of fault detection in semiconductor manufacturing industry.
Abstract: To enter next process control, numerous approaches, including run-to-run (R2R) process control and fault detection and classification (FDC) have been suggested in semiconductor manufacturing industry as a facilitation of advanced process control. This paper introduces a novel type of optical plasma process monitoring system, called plasma eyes chromatic system (PECSTM) and presents its potential for the purpose of fault detection. Qualitatively comparison of optically acquired signal levels vs. process parameter modifications are successfully demonstrated, and we expect that PECSTM signal can be a useful indication of onset of process change in real-time for advanced process control (APC).
TL;DR: In this article, a 60 GHz LTCC SiP with low-power CMOS OOK modulator and demodulator is presented, and the measured data rate is up to 2 Gb/s.
Abstract: In this paper, a 60 GHz LTCC SiP with low-power CMOS OOK modulator and demodulator is presented. The 60 GHz modulator is designed in a 90-nm CMOS process. The modulator uses a current reuse technique and only consumes 14.4-mW of DC power in the on-state. The measured data rate is up to 2 Gb/s. The 60 GHz OOK demodulator is designed in a 130nm CMOS process. The demodulator consists of a gain boosting detector and a baseband amplifier, and it recovers up to 5 Gb/s while consuming low DC power of 14.7 mW. The fabricated 60 GHz modulator and demodulator are fully integrated in an LTCC SiP with 1 by 2 patch antenna. With the LTCC SiP, 648 Mb/s wireless video transmission was successfully demonstrated at wireless distance of 20-cm.
TL;DR: It is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.
Abstract: Interconnect lines with inter-layer vias are experimentally characterized by using high-frequency S-parameter measurements. Test patterns are designed and fabricated using a package process. Then they are measured using Vector Network Analyzer (VNA) up to 25 GHz. Modeling a via as a circuit, its model parameters are determined. It is shown that the circuit model has excellent agreement with the measured S-parameters. The signal integrity of the lines with inter-layer vias is evaluated by using the developed circuit model. Thereby, it is shown that via may have a substantially deteriorative effect on the signal integrity of high-speed integrated circuits.