Showing papers in "Journal of Semiconductors in 2012"

Photoelectric properties of Cu 2 ZnSnS 4 thin films deposited by thermal evaporation

Abstract: Sn/Cu/ZnS precursor were deposited by evaporation on soda lime glass at room temperature, and then polycrystalline thin films of Cu2ZnSnS4 (CZTS) were produced by sulfurizing the precursors in a sulfur atmosphere at a temperature of 550 °C for 3 h Fabricated CZTS thin films were characterized by X-ray diffraction, energy dispersive X-ray spectroscopy, ultraviolet-visible-near infrared spectrophotometry, the Hall effect system, and 3D optical microscopy. The experimental results show that, when the ratios of [Cu]/([Zn] + [Sn]) and [Zn]/[Sn] in the CZTS are 0.83 and 1.15, the CZTS thin films possess an absorption coefficient of larger than 4.0 × 104 cm−1 in the energy range 1.5–3.5 eV, and a direct band gap of about 1.47 eV. The carrier concentration, resistivity and mobility of the CZTS film are 6.98 × 1016 cm−3, 6.96 Ωcm, and 12.9 cm2/(Vs), respectively and the conduction type is p-type. Therefore, the CZTS thin films are suitable for absorption layers of solar cells.

Effect of substrate temperature on the stability of transparent conducting cobalt doped ZnO thin films

Abstract: Transparent conducting Co doped ZnO thin films have been fabricated by Ultrasonic spray. The thin films were deposited at three different substrate temperatures of 300, 350 and 400 °C. The obtained films had a hexagonal wurtzite structure with a strong (002) preferred orientation. The maximum crystallite size value of the film deposited at 350 °C is 55.46 run. Spectrophotometer (UV-vis) of a Co doped ZnO film deposited at 350 °C shows an average transmittance of about 90%. The band gap energy increased from 3.351 to 3.362 eV when the substrate temperature increased from 300 to 350 °C. The electrical conductivity of the films deposited at 300, 350 and 400 °C were 7.424, 7.547 and 6.743 (Ω·cm)−1 respectively. The maximum activation energy value of the films at 350 °C was 1.28 eV, indicating that the films exhibit a n-type semiconducting nature.

Characteristics of AlGaN/GaN/AlGaN double heterojunction HEMTs with an improved breakdown voltage

Abstract: We studied the performance of AlGaN/GaN double heterojunction high electron mobility transistors (DH-HEMTs) with an AlGaN buffer layer, which leads to a higher potential barrier at the backside of the two-dimensional electron gas channel and better carrier confinement. This, remarkably, reduces the drain leakage current and improves the device breakdown voltage. The breakdown voltage of AlGaN/GaN double heterojunction HEMTs (~100 V) was significantly improved compared to that of conventional AlGaN/GaN HEMTs (~50 V) for the device with gate dimensions of 0.5 × 100 μm and a gate—drain distance of 1 μm. The DH-HEMTs also demonstrated a maximum output power of 7.78 W/mm, a maximum power-added efficiency of 62.3% and a linear gain of 23 dB at the drain supply voltage of 35 V at 4 GHz.

A nanostructured copper telluride thin film grown at room temperature by an electrodeposition method

Abstract: Copper telluride onion flower like microstructures, constructed by quantum dots with various diameters, were obtained by a potentiostatic electrodeposition method at room temperature. The structural, optical, surface morphology, compositional analysis and Raman spectra properties of the deposited films have been studied using X-ray diffraction, optical absorption with scanning electron microscopy, EDAX, and Raman spectroscopy. The electrolyte concentration and deposition time can be used to control the diameter of the electrodeposited quantum dots to within a range of 50-55 nm. The films are found to be stoichiometric in composition. The optical constants such as the optical band gap energy and the optical absorption spectra show significant variation in their values with a change in deposition time. Upon deposition time the band gap energy increased from a value of 2.74 to 2.89 eV.

Continuous analytic I—V model for GS DG MOSFETs including hot-carrier degradation effects

Abstract: We have studied the influence of hot-carrier degradation effects on the drain current of a gate-stack double-gate (GS DG) MOSFET device. Our analysis is carried out by using an accurate continuous current?voltage (I?V) model, derived based on both Poisson's and continuity equations without the need of charge-sheet approximation. The developed model offers the possibility to describe the entire range of different regions (subthreshold, linear and saturation) through a unique continuous expression. Therefore, the proposed approach can bring considerable enhancement at the level of multi-gate compact modeling including hot-carrier degradation effects.

Humidity sensing properties of Cu2O-PEPC nanocomposite films

Abstract: A blend of copper oxide nanopowder (Cu2O), 3 wt.%, and poly-N-epoxypropylcarbazole (PEPC), 2 wt.%, in benzol was drop-casted on glass substrates with pre-deposited surface-type silver electrodes for the fabrication of Cu2O-PEPC nanocomposite thin films. The thicknesses of the Cu2O-PEPC films were in the range of 10–13 μm. The effect of humidity on the electrical properties of the nanocomposite films was investigated by measuring the capacitance and dissipation of the samples at two different frequencies of the applied voltage: 120 Hz and 1 kHz. The AC resistance of the samples was determined from the dissipation values, and the DC resistance was measured directly. The effect of ageing on the humidity sensing properties of the nanocomposite was observed. After ageing, it was observed that at 120 Hz and 1 kHz, under a humidity of up to 86% RH, the capacitance of the cell increased by 85 and 8 times, and the resistance decreased by 345 and 157 times, accordingly, with respect to 30% RH conditions. It was found that with an increase in frequency, the capacitance and resistance of the samples decreased. It is assumed that the humidity response of the cell is associated with the diffusion of water vapors and doping of the semiconductor nanocomposite by water molecules.

Synthesis and efficient field emission characteristics of patterned ZnO nanowires

Abstract: Patterned ZnO nanowires were successfully synthesized on ITO electrodes deposited on the glass sub- strate by using a simple thermal evaporation approach. The morphology, crystallinity and optical properties of ZnO nanowires were characterized by scanning electron microscopy, X-ray diffraction, energy dispersive X-ray and pho- toluminescence spectroscopy. Their field emission characteristics were also investigated. SEM images showed that the ZnO nanowires, with a diameter of 100-200 nm and length up to 5m, were highly uniform and well distributed on the linear ITO electrodes. The field emission measurement indicated that patterned ZnO nanowire arrays have a turn-on field of 1.6 V/ m at current density of 1 A/cm 2 and a threshold field of 4.92 V/m at current density of 1 mA/cm 2 at an emitter-anode gap of 700 m. The current density rapidly reached 2.26 mA/cm 2 at an applied field of 5.38 V/ m. The fluctuation of emission current was lower than 5% for 4.5 h. The low turn-on field, high current density and good stability of patterned ZnO nanowire arrays indicate that it is a promising candidate for field emission application.

Material removal rate of 6H-SiC crystal substrate CMP using an alumina (Al2O3) abrasive

Abstract: The influences of the polishing slurry composition, such as the pH value, the abrasive size and its concentration, the dispersant and the oxidants, the rotational velocity of the polishing platen and the carrier and the polishing pressure, on the material removal rate of SiC crystal substrate (0001) Si and a (0001) C surface have been studied based on the alumina abrasive in chemical mechanical polishing (CMP). The results proposed by our research here will provide a reference for developing the slurry, optimizing the process parameters, and investigating the material removal mechanism in the CMP of SiC crystal substrate.

Dielectric response and electric properties of organic semiconducting phthalocyanine thin films

Abstract: The dielectric function of some phthalocyanine compounds (ZnPc, H2Pc, CuPc, and FePc) were inves- tigated by analyzing the measured capacitance and loss tangent data. The real part of the dielectric constant, "1, varies strongly with frequency and temperature. The frequency dependence was expressed as: "1 D A! n , where the index, n, assumes negative values (n < 0). In addition, the imaginary part of the dielectric constant, "2, is also frequency and temperature dependent. Data analysis confirmed that "2 D B! m with values of m less than zero. At low frequencies and all temperatures, a strong dependence is observed, while at higher frequencies, a moderate dependence is obvious especially for the Au-electrode sample. Qualitatively, the type of electrode material had little effect on the behavior of the dielectric constant but did affect its value. Analysis of the AC conductivity dependence on frequency at different temperatures indicated that the correlated barrier hopping (CBH) model is the most suitable mechanism for the AC conduction behavior. Maximum barrier height, W , has been estimated for ZnPc with different electrode materials (Au and Al), and had values between 0.10 and 0.9 eV. For both electrode types, the maximum barrier height has strong frequency dependence at high frequency and low temperatures. The relaxation time, , for ZnPc and FePc films increases with decreasing frequency. The activation energy was derived from the slopes of versus 1/T curves. At low temperatures, an activation energy value of about 0.01 eV and 0.04 eV was estimated for ZnPc and FePc, respectively. The low values of activation energy suggest that the hopping of charge carriers between localized states is the dominant mechanism.

Structural and optical properties of Zn-doped β-Ga 2 O 3 films

Abstract: Intrinsic β-Ga2O3 and Zn-doped β-Ga2O3 films were prepared using RF magnetron sputtering. The effects of the Zn doping and thermal annealing on the structural and optical properties are investigated. In comparison with the intrinsic β-Ga2O3 films, the microstructure, optical transmittance, optical absorption, optical energy gap, and photoluminescence of Zn-doped β-Ga2O3 films change significantly. The post-annealed β-Ga2O3 films are polycrystalline. After Zn doping, the crystallization deteriorates, the optical band gap shrinks, the transmittance decreases and the UV, blue, and green emission bands are enhanced.

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

Abstract: We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al0:83In0:17N and narrowband GaN layers, along with high-k Al2O3 as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (Vt/, Ion/Ioff ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, Ion, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the Ioff and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.

The conductive path in HfO 2 : first principles study

Abstract: The conductive path formed by the interstitial Ag or substitutional Ag in HfO2 was investigated by using the Vienna ab initio simulation package based on the DFT theory. The calculated results indicated that the ordering of interstitial Ag ions at special positions can form a conductive path, and it cannot form at other positions. The orientation dependence of this conductive path was then investigated. Various types of super cells are also built to study the rupture of the path, which corresponds to some possible "off" states.

Acetic acid gas sensors based on Ni2+ doped ZnO nanorods prepared by using the solvothermal method

Abstract: Ni2+-doped ZnO nanorods with different doping concentrations are prepared via the solvothermal method. The doped ZnO nanorods are characterized by X-ray diffraction (XRD) and scanning electron microscopy (SEM), respectively. The amount of Ni2+ ions that enter the lattice of ZnO increases with increasing the Ni2+/Zn2+ molar ratio when the molar ratio of Ni2+/Zn2+ in the starting solution is lower than 3% and does not change obviously if the mole ratio of Ni2+/Zn2+ in the starting solution is in the range of 3–10 mol%. The effect of Ni2+ doping on the gas-sensing properties is investigated. The results reveal that the amount of Ni2+ has a great influence on the response (Ra/Rg) and the gas-sensing selectivity. The sensor based on 1 mol % Ni2+ doped ZnO nanorods (120 °C, 10 h) exhibits a high response to acetic acid vapor, in particular, the responses to 0.001 ppm and 0.01 ppm acetic acid vapor reach 1.6 and 2, respectively. The response time and the recovery time for 0.001 ppm acetic acid are only 4 s and 27 s, respectively.

Effect of ZnO films on CdTe solar cells

Abstract: The ZnO high resistivity transparent (HRT) layers were prepared by DC magnetron sputtering on the 1 mm borosilicate glass with 150 nm ITO coating. The structural, optical and electrical properties of the as-deposited films were investigated by XRD, UV/Vis spectroscopy and four-probe technology. The interface characters of the ITO/ZnO and ZnO/CdS systems were studied by ultraviolet photoelectron spectroscopy (UPS) and X-ray photoelectron spectroscopy (XPS) depth profiling tests. The results show that ZnO has good optical and electrical properties. The insertion of the ZnO films decreases the energy barrier between ITO and CdS films. The energy conversion efficiency and quantum efficiency were found to be 12.77% (8.9%) and > 90% (79%) with or (without) ZnO films of CdTe solar cells. Furthermore, the effect of thickness, mobility and carrier density of ZnO films on CdTe solar cells was analyzed by AMPD-1D.

Nano-WO 3 film modified macro-porous silicon (MPS) gas sensor

Abstract: We prepared macro-porous silicon (MPS) by electrochemical corrosion in a double-tank cell on the surface of single-crystalline P-type silicon. Then, nano-WO3 films were deposited on MPS layers by DC facing target reactive magnetron sputtering. The morphologies of the MPS and WO3/MPS samples were investigated by using a field emission scanning electron microscope. The crystallization of WO3 and the valence of the W in the WO3/MPS sample were characterized by X-ray diffraction and X-ray photoelectron spectroscopy, respectively. The gas sensing properties of MPS and WO3/MPS gas sensors were thoroughly measured at room temperature. It can be concluded that: the WO3/MPS gas sensor shows the gas sensing properties of a P-type semiconductor gas sensor. The WO3/MPS gas sensor exhibits good recovery characteristics and repeatability to 1 ppm NO2. The addition of WO3 can enhance the sensitivity of MPS to NO2. The long-term stability of a WO3/MPS gas sensor is better than that of an MPS gas sensor. The sensitivity of the WO3/MPS gas sensor to NO2 is higher than that to NH3 and C2H5OH. The selectivity of the MPS to NO2 is modified by deposited nano-WO3 film.

An AES chip with DPA resistance using hardware-based random order execution

Abstract: This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm2. A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance.

Fabrication and characterization of a low frequency electromagnetic energy harvester

Abstract: This paper presents the fabrication and characterization of an AA size electromagnetic energy transducer based on vibration. A magnetic spring technique is used to scavenge energy from low frequency external vibration. The output of the harvester is maximized by optimizing the mass of moving and fixed magnets, coil width, coil position and load resistance through a comprehensive experimental analysis. The prototype can generate an open circuit voltage of 3.961 V and 1.18 mW average power at a load resistance of 97 Ω with 9 Hz resonance frequency and 0.5 mm displacement.

An offset cancellation technique in a switched-capacitor comparator for SAR ADCs

Abstract: An offset cancellation technique for a SAR (successive approximation register) ADC switched-capacitor comparator is described. The comparator is designed with a pre-amplifying and regenerative latching structure and realized in 0.18 μm CMOS. With the first stage preamplifier offset cancellation and low offset regenerative latching approach, the equivalent offset of the comparator is reduced to < 0.55 mV. By using the pre-amplifying and regenerative latching comparison mode the comparator exhibits low power dissipation. Under a 1.8 V power supply, with a 200 kS/s ADC sampling rate and 3 MHz clock frequency, a 13-bit comparison resolution is reached and less than 0.09 mW power dissipation is consumed. The superiority of this comparator is discussed and proved by the post-simulation and application to a 10 bit 200 kS/s touch screen SAR A/D converter.

Progress in Group III nitride semiconductor electronic devices

Abstract: Recently there has been a rapid domestic development in group III nitride semiconductor electronic materials and devices. This paper reviews the important progress in GaN-based wide bandgap microelectronic materials and devices in the Key Program of the National Natural Science Foundation of China, which focuses on the research of the fundamental physical mechanisms of group III nitride semiconductor electronic materials and devices with the aim to enhance the crystal quality and electric performance of GaN-based electronic materials, develop new GaN heterostructures, and eventually achieve high performance GaN microwave power devices. Some remarkable progresses achieved in the program will be introduced, including those in GaN high electron mobility transistors (HEMTs) and metal—oxide—semiconductor high electron mobility transistors (MOSHEMTs) with novel high-k gate insulators, and material growth, defect analysis and material properties of InAlN/GaN heterostructures and HEMT fabrication, and quantum transport and spintronic properties of GaN-based heterostructures, and high-electric-field electron transport properties of GaN material and GaN Gunn devices used in terahertz sources.

An advanced alkaline slurry for barrier chemical mechanical planarization on patterned wafers

Abstract: We have developed an alkaline barrier slurry (named FA/O slurry) for barrier removal and evaluated its chemical mechanical planarization (CMP) performance through comparison with a commercially developed barrier slurry. The FA/O slurry consists of colloidal silica, which is a complexing and an oxidizing agent, and does not have any inhibitors. It was found that the surface roughness of copper blanket wafers polished by the FA/O slurry was lower than the commercial barrier slurry, demonstrating that it leads to a better surface quality. In addition, the dishing and electrical tests also showed that the patterned wafers have a lower dishing value and sheet resistance as compared to the commercial barrier slurry. By comparison, the FA/O slurry demonstrates good planarization performance and can be used for barrier CMP.

A PNPN tunnel field-effect transistor with high-k gate and low-k fringe dielectrics

Abstract: A PNPN tunnel field effect transistor (TFET) with a high-k gate dielectric and a low-k fringe dielectric is introduced. The effects of the gate and fringe electric fields on the TFET's performance were investigated through two-dimensional simulations. The results showed that a high gate dielectric constant is preferable for enhancing the gate control over the channel, while a low fringe dielectric constant is useful to increase the band-to-band tunneling probability. The TFET device with the proposed structure has good switching characteristics, enhanced on-state current, and high process tolerance. It is suitable for low-power applications and could become a potential substitute in next-generation complementary metal-oxide-semiconductor technology.

Analysis of the p+/p window layer of thin film solar cells by simulation

Abstract: The application of a p+/p configuration in the window layer of hydrogenated amorphous silicon thin film solar cells is simulated and analyzed utilizing an AMPS-1D program. The differences between p+?p?i?n configuration solar cells and p?i?n configuration solar cells are pointed out. The effects of dopant concentration, thickness of p+-layer, contact barrier height and defect density on solar cells are analyzed. Our results indicate that solar cells with a p+?p?i?n configuration have a better performance. The open circuit voltage and short circuit current were improved by increasing the dopant concentration of the p+ layer and lowering the front contact barrier height. The defect density at the p/i interface which exceeds two orders of magnitude in the intrinsic layer will deteriorate the cell property.

Using I-V characteristics to investigate selected contacts for SnO 2 :F thin films

Abstract: Fluorine doped tin oxide (SnO2:F) thin films were prepared on glass substrates by the spray pyrolysis (SP) technique at different substrate temperatures between 380–480 °C. The microstructure of the films was explored using scanning electron microscope observations. An investigation of selected contacts for the films was performed through the analysis of the I–V measurements which were taken in the dark at room temperature. Indium, aluminum and silver were selected as contacts where two strips of each metal were vacuum-evaporated on the surface of the film. The resistivity of the films was estimated from the linear I–V plots. It was found that the smallest resistivity was obtained using silver contacts, while the largest resistivity was obtained by using indium contacts. This is because silver diffuses in the film and participates in doping, while aluminum and indium cause compensation effects when they diffuse in the film. The best linear fit parameters are those of films with aluminum contacts, and the worst ones are those of films with indium contacts. Annealing was found to improve the electrical properties of the films, especially those deposited at a low substrate temperature. This is because it is expected to encourage crystal growth and to reduce the contact potential which leads to the formation of an alloy. Annealed films are more stable than un-annealed ones.

A 700 V BCD technology platform for high voltage applications

Abstract: A 700 V BCD technology platform is presented for high voltage applications. An important feature is that all the devices have been realized by using a fully implanted technology in a p-type single crystal without an epitaxial or a buried layer. An economical manufacturing process, requiring only 10 masking steps, yields a broad range of MOS and bipolar components integrated on a common substrate, including 700 V nLDMOS, 200 V nLDMOS, 80 V nLDMOS, 60 V nLDMOS, 40 V nLDMOS, 700 V nJFET, and low voltage devices. A robust double RESURF nLDMOS with a breakdown voltage of 800 V and specific on-resistance of 206.2 mΩ·cm2 is successfully optimized and realized. The results of this technology are low fabrication cost, simple process and small chip area for PIC products.

Low threading dislocation density in GaN films grown on patterned sapphire substrates

Abstract: The growth process of three-dimensional growth mode (3D) switching to two-dimensional growth mode (2D) is investigated when GaN films are grown on cone-shaped patterned sapphire substrates by metal-organic chemical vapor deposition. The growth condition of the 3D-2D growth process is optimized to reduce the threading dislocation density (TDD). It is found that the condition of the 3D layer is critical. The 3D layer keeps growing under the conditions of low V/III ratio, low temperature, and high pressure until its thickness is comparable to the height of the cone-shaped patterns. Then the 3D layer surrounds the cone-shaped patterns and has inclined side facets and a top (0001) plane. In the following 2D-growth process, inclined side facets coalesce quickly and the interaction of TDs with the side facets causes the TDs to bend over. As a result, the TDD of GaN films can decrease to 1 10 8 cm 2 , giving full-width at half maximum values of 211 and 219 arcsec for (002) and (102) omega scans, respectively.

Charge transfer efficiency improvement of a 4-T pixel by the optimization of electrical potential distribution under the transfer gate

Abstract: The charge transfer efficiency improvement method is introduced by optimizing the electrical potential distribution under the transfer gate along the charge transfer path. A non-uniform doped transfer transistor channel is introduced to provide an ascending electrical potential gradient in the transfer transistor channel. With the adjustments to the overlap length between the R1 region and the transfer gate, the doping dose of the R1 region, and the overlap length between the anti-punch-through (APT) implantations and transfer gate, the potential barrier and potential pocket in the connecting region of transfer transistor channel and the pinned photodiode (PPD) are reduced to improve the electrical potential connection. The simulation results show that the percentage of residual charges to total charges drops from 1/104 to 1/107, and the transfer time is reduced from 500 to 110 ns. This means the charge transfer efficiency is improved.

A low-phase-noise ring oscillator with coarse and fine tuning in a standard CMOS process

Abstract: A low-phase-noise wideband ring oscillator with coarse and fine tuning techniques implemented in a standard 65 nm CMOS process is presented. Direct frequency modulation in the ring oscillator is analyzed and a switched capacitor array is introduced to produce the lower VCO gain required to suppress this effect. A two-dimensional high-density stacked MOM-capacitor was adopted as the switched capacitor to make the proposed ring VCO compatible with standard CMOS processes. The designed ring VCO exhibits an output frequency from 480 to 1100 MHz, resulting in a tuning range of 78%, and the measured phase noise is −120 dBc/Hz @ 1 MHz at 495 MHz output. The VCO core consumes 3.84 mW under a 1.2 V supply voltage and the corresponding FOM is −169 dBc/Hz.

Fabrication and temperature dependence of a GaInP/GaAs/Ge tandem solar cell

Abstract: GaInP/GaAs/Ge tandem solar cells were fabricated by a MOCVD technique. The photoelectric properties of the solar cells were characterized by a current—voltage test method. The dependence of the solar cell's characteristics on temperature were investigated from 30 to 170 °C at intervals of 20 °C. Test results indicated that with increasing temperature, Jsc of the cell increased slightly with a temperature coefficient of 9.8 (μA/cm2)/°C. Voc reduced sharply with a coefficient of −5.6 mV/°C. FF was reduced with a temperature coefficient of −0.00063/°C. Furthermore, the conversion efficiency decreased linearly with increasing temperature which decreased from 28% at 30 °C to 22.1% at 130 °C. Also, detailed theoretical analyses for temperature characteristics of the solar cell were given.

Analysis and implementation of an improved recycling folded cascode amplifier

Abstract: A generally improved recycling folded cascode (IRFC) is analyzed and implemented. Analysis and comparisons among the IRFC, the original recycling folded cascode (RFC) and the conventional folded cascode (FC) are made, and it is shown that with the flexible structure of IRFC, significant enhancement in transconductance, slew rate and noise can be achieved. Prototype amplifiers were fabricated in 0.13 μm technology. Measurement shows that IRFC has 3× enhancement in gain-bandwidth and slew rate over conventional FC, and the enhancement is 1.5× when compared with the RFC.

Design and implementation of an ultra-low power passive UHF RFID tag

Abstract: This paper presents a fully integrated passive UHF RFID tag chip complying with the ISO18000-6B protocol. The tag chip includes an RF/analog front-end, a baseband processor, and a 512-bit EEPROM memory. To improve power conversion efficiency, a Schottky barrier diode based rectifier is adopted. A novel voltage reference using the peaking current source is discussed in detail, which can meet the low-power, low-voltage requirement while retaining circuit simplicity. Most of the analog blocks are designed to work under sub-1 V to reduce power consumption, and several practical methods are used to further reduce the power consumption of the baseband processor. The whole tag chip is implemented in a TSMC 0.18 m CMOS process with a die size of 800 800 m 2 . Measurement results show that the total power consumption of the tag chip is only 7.4 W with a sensitivity of -12 dBm.