Showing papers in "Journal of Systems Architecture in 2009"

TL;DR: This paper surveys the state-of-the-art FTL software for flash memory, defines the problems, addresses algorithms to solve them, and discusses related research issues.

TL;DR: This paper argues that specific types of security goals may be expressed in a graphical fashion at the business process modelling level which in turn can be transformed into corresponding access control and security policies.

TL;DR: It is proved that the conditional diagnosability of n-dimensional Hypercube Q"n is 3(n-2)+1 for n>=5, which is about three times larger than the classical diagnosable ofQ"n.

TL;DR: Two new D flip-flop structures are proposed which employ the inherent capabilities of QCA in timing and data flow control, rather than ordinary replacement of CMOS elements with equivalent QCA ones.

TL;DR: A novel discrete cosine transform domain invisible-robust watermarking method that uses cryptography and watermarked methods simultaneously to provide a double-layer of protection to digital media is presented.

TL;DR: An abstract trust model is presented that applies complementary qualitative methodology which addresses the core of trust as socio-cognitive phenomenon and is applied in the web services environment that enables trust management in SOAs.

TL;DR: A performance prediction approach which employs state-of-the-art techniques from experiment design, machine learning and data mining is proposed which generates highly accurate estimations for unsampled points in the design space and shows the robustness for the worst-case prediction.

TL;DR: Two software-based mechanisms for reducing the impact of CAN bit stuffing are considered and compared and it is concluded that the SBS technique is more effective in the reduction of message-length variations, but at the cost of an increase in CPU time and memory overheads and a reduction in the available data bandwidth.

TL;DR: A tool called PacketBench is presented, which provides a framework for implementing network processing applications and obtaining an extensive set of workload characteristics, and shows a range of workload results that focus on individual packets and the variation between them.

TL;DR: A novel architecture based on a model of computation developed in the AETHER project to provide a safe and composable approach to concurrent programming is presented that demonstrates the required scalability of future many-core processor systems.

TL;DR: A design exploration framework is proposed that provides for rapid identification of a reduced set of profitable custom instructions and their area costs on commercial architectures without the need for time consuming hardware synthesis process.

TL;DR: The goal of this paper is to provide a map-dependent obfuscation procedure that enables the release of the maximum possibleuser's location information, that does not lead to a violation of the original user's location-privacy requirements, even when refined through map-based inference.

TL;DR: The motivation for this work was to provide an early implementation on conventional processors as well as supporting work from programming FPGA chips to Grids.

TL;DR: Additional requirements for securing VOs are described and a novel architecture and approach to managing VO access control policies are proposed, which helps business users focus on designing business processes, exposing web services and managing their VO partnerships.

TL;DR: The existence of an upper bound on the overhead caused by the transition time between frequencies in Rate Monotonic scheduled real-time systems is formally proved and the method can be applied to multicore or multiprocessor systems.

TL;DR: A framework to support role-based access control for distributed services focusing on the integration of customer preferences is introduced and aims to collect and generate policy-based security measures in cross-organisational scenarios.

TL;DR: The experimental results show that the proposed SA-based algorithm achieves near-optimal solution in a reasonable time, while the branch-and-bound algorithm takes a very long time to find the optimal solution, and the iterative algorithm fails to achieve good solution quality.

TL;DR: The obtained results show that the traffic models and load that ends processing elements has a direct effect on the energy consumption and area requirements of WK-recursive interconnect in heavy traffic load.

TL;DR: The idea behind the approach is to attribute to roles and permissions, multimedia signatures in which conditions based on users' context information described using multimedia objects are integrated in order to limit role activation and the abuse of permissions in a given environment.

TL;DR: In this paper, an efficient multipath multicast routing algorithm with hamiltonian cycle model (mulitpath-HCM) is presented, which utilizes communication channels more uniformly in order to reduce the path length of the routing messages, making the multicasting more efficient.

TL;DR: This work was funded by the European project 'Fault Injection for TTA' and it is divided into two parts: a verification of the dependability specifications of the TTP communication protocol, based on TTA, in the presence of faults directly induced in communication lines.

TL;DR: A way to include timing models in a full-system simulator (Simics) to provide a suitable tool for network subsystem simulation is proposed and it is possible to conclude that offloading allows a relevant throughput improvement in some circumstances that can be qualitatively predicted by the LAWS model.

TL;DR: This paper proposes a model of self- Adaptive systems and describes how to manage self-adaptivity at all levels (both hardware and software) by means of a decentralized control algorithm.

TL;DR: A simulation-based profile-driven quantitative analysis of packet-processing applications that locates the performance bottlenecks and architectural challenges of a packet- processing engine and extracts helpful architectural guidelines for design of a flexible and high-performance embedded processor.

TL;DR: A novel solution to distributed constraint maintenance issue in multi-user collaborative modeling environments is proposed, which can retain the effects of all concurrent modeling operations even though they may cause constraint violations.

TL;DR: A superscalar architecture that selectively anticipates the values produced by high-latency instructions is developed, focusing on multiply, division and loads with miss in L1 data cache, implementing a dynamic instruction reuse scheme for the MUL/DIV instructions and a simple last value predictor for the critical Load instructions.

TL;DR: This paper will use three-party key establishment to enable secure communications for Service Requester and Service Provider and aims at reducing communication and computation overheads.

TL;DR: A novel routing table compaction scheme to reduce the number of entries in the routing table using ternary content addressable memory (TCAM) features and a new sampling technique to alleviate port errors caused by caching.

TL;DR: This paper compares the design and performance of four hybrid distributed shared memory (DSM) organizations by detailed simulation of the same hardware platform and relates the experience implementing and simulating the software protocols for the four architectures.

TL;DR: The proposed modular multiplier can be applied to public key cryptosystems based on integer arithmetic such as RSA, DSA or ECC.