Showing papers in "Microelectronics Journal in 2016"

TL;DR: A high density, low-power standard cell architecture, developed using design/technology co-optimization (DTCO), as well as example SRAM cells are shown, and the PDK transistor electrical assumptions are explained, as are the FEOL and BEOL design rules.

TL;DR: This work summarizes the methods and models used to characterize and simulate nanoelectronic devices, and reviews the properties of GNRs, defect issues and the most recent approaches and manufacturing techniques that could be used to design GNR-based logic circuits.

TL;DR: An improved full adder in QCA technology is proposed that is considerably declined in terms of cell numbers and area, compared to other full adders and delay is kept at minimum.

TL;DR: A detailed comparative study reveals that the proposed QCA adder not only offers significantly high degree of fault-tolerance but also performs fairly well as compared to the existing adders with respect to other design metrics too, thereby ensures practical realizability of the proposed adder.

TL;DR: A new voltage mode design is presented for quaternary logic using CNTFETs and basic gates, half-adder, and full-adder are implemented using voltage divider to ensure the functionality of this promising proposed architecture.

TL;DR: The design and implementation of fractional- order filters based on promising CMOS structure of Differential Difference Current Conveyor, which was designed and fabricated using the 0.35µm CMOS AMIS process, and a technique for the quick derivation of high-order filters is introduced.

TL;DR: Investigation of analog/RF performance and small signal behavior of Transparent Gate Recessed Channel (TGRC) MOSFET in terms of transconductance, DIBL, channel resistance parasitic capacitances, cut-off frequency and maximum oscillator frequency shows improvement, reflecting its significance in high-frequency THz range applications.

TL;DR: A general fractional order oscillator based on two port network where two topologies of oscillator structure with two impedances are discussed, which enables the oscillation frequency band to cover from small Hz to hundreds MHz which is suitable range for most of measuring applications.

TL;DR: The analysis of noise in Circular Gate TFET in presence of interface traps (Gaussian) when the device is subjected to scaling of gate-drain underlap length and body thickness, and change in gate work function and gate dielectric constant shows that generation-recombination noise is dominant at low frequencies whereas diffusion noise is dominates at high frequencies.

TL;DR: In this article, a hardware architecture of scalar multiplication based on Montgomery ladder algorithm for binary elliptic curve cryptography is presented, where the point addition and point doubling are performed in parallel by only three pipelined digit-serial finite field multipliers.

TL;DR: The proposed model ensures high fault tolerance under single missing cell defect providing no other deviation from the ideal architecture than the fact of the missing cell, and a reliability estimation model for QCA is proposed.

TL;DR: A detailed survey of various current mirror topologies has been carried out and these topologies have been categorized on the basis of various characteristic parameters.

TL;DR: A novel topology suitable for emulating fractional-order capacitors and inductors using current excitation is achieved using a fractiona-order differentiator/integrator block and appropriately configured Operational Transconductance Amplifiers.

TL;DR: The experimental results show that the electric power efficiency of the bridge rectifiers circuit is higher than that of the double-voltage rectifier circuit at maximum electric power; however, the double the voltage of the cross-sectional rectifier is suitable for use in high voltage situations.

TL;DR: Two asymmetrically ground-gated MTCMOS SRAM circuits are presented for providing a low-leakage SLEEP mode with data retention capability and exhibit enhanced tolerance to process parameter variations and lower minimum applicable power supply voltages.

TL;DR: The idea is to remove the stringent trade-off between the input matching and power consumption by using the transconductance of the tail transistor, so it's suitable for multimode and Wireless Sensor Network applications.

TL;DR: The proposed instrumentation amplifier is versatile and hence capable of conditioning various bio-potential signals like Electrocardiogram (ECG), Electroencephalogram (EEG), Electromyogram (EMG) and Electrooculogram (EOG) as well as signals produced from sensors.

TL;DR: This paper presents sub-threshold, bulk-driven two-stage cascode compensated operational transconductor, which drive load up to 60pF, and a three-stage OTA, which includes one additional CS class AB buffer at the output of OTA1, to drive R-C shunt load.

TL;DR: An analytical subthreshold current model for undoped/lightly doped Cylindrical Nanowire FETs (CGNWFETS) including quantum effects including Quantum Mechanical Effects (QMEs) is proposed.

TL;DR: The measured results show that the power conversion efficiency performance at lower input RF power level has been improved in the proposed circuit as compared to the traditional VM circuit.

TL;DR: A wide band resistive feedback CMOS low noise amplifier (LNA) with Modified Derivative Superposition (MDS) technique is designed by using TSMC RF CMOS 0.18 μm technology, so third order nonlinear current of two transistors can be canceled out and high third order input intercept point (IIP3) can be attained.

TL;DR: A simple analytical PSpice model has been developed and verified for a 4H–SiC based MOSFET power module with voltage and current ratings of 1200 V and 120 A, which correlates well with the measured results over a wide temperature range.

TL;DR: An improved shunt peaking bandwidth (BW) extension technique is proposed in this paper that extends the flat BW up to 200% and post-layout simulation results of the proposed LNA circuit show +11dBm of IIP3 that indicates 12dB improvement comparing with conventional structures.

TL;DR: Analytical models for channel potential, threshold voltage, and subthreshold swing of the short-channel fin-shaped field-effect transistor (FinFET) make the model useful in the practical applications of the device.

TL;DR: The overall performance makes this filter deserved to be used in aggressive EEG detection systems and is utilized to reject the effect of the powerline interference at 50Hz.

TL;DR: This paper presents an 8-bit low-power clock gated successive approximation analog to digital converter (SA-ADC) using D-flip flop (D-FF) unit for biomedical applications.

TL;DR: A modified voltage differencing voltage transconductance amplifier (MVDVTA) based three circuits with a minimum number of only grounded passive components which are suitable for integrated circuit (IC) design are proposed.

TL;DR: This paper improved the output impedance of a Low Voltage Low Power (LVLP) current mirror by using body driven technique and transconductance enhancement and the comparison between the performance of this circuit and the primary one is verified by simulation in TSMC 0.18źm CMOS technology.

TL;DR: First novel design of a ternary SRAM (T-SRAM) cell based on the proposed binary (two-valued) modified GDI (m-GDI) method, which is appropriate for designing circuits using MVL, is presented and is an attractive choice for nano technology application in the presence of impact process and temperature variations.

TL;DR: This research work has analyzed the performance of various parameters for the cylindrical surrounding-gate MOSFET using surface potential based approach and further transformation of variable technique to find the solution of the same differential equation.