Showing papers in "Microelectronics Journal in 2018"

TL;DR: A survey of various wearable technologies that can be used to accurately quantify the rehabilitation progress in terms of fingers' hand joint angles and proposes a wearable glove for accurately measuring hand Joint angles with enhanced features for better diagnosis and rehabilitation.

TL;DR: In this article, a full-swing, low-power and energy-aware full-adder using hybrid logic scheme is presented, where a new energy-efficient 10T XOR-XNOR cell is designed by modifying inverter and pass transistor based 3T xOR-xNOR gates combined with a feedback loop.

TL;DR: A systematic procedure for the design of a single-stage operational-transconductance amplifier (OTA) using the gm/ID methodology and an automated optimization procedure is presented to maximize the speed of a unity-gain buffer under current consumption, DC gain, and input capacitance constraints.

TL;DR: This paper investigates the mathematical analysis of the proposed memristor ternary logic gates circuits and compares them with the previously published implementations showing better performance in terms of power, delay and area.

TL;DR: Unlike the conventional chaotic oscillators, the proposed digitally programmable multi-direction chaotic oscillator is fully integrated in one single chip, and it achieves lower supply voltage, lower power dissipation and smaller chip area.

TL;DR: A novel approach is proposed and discussed for designing CMOS double-tail dynamic comparator using the bulk-driven method, which achieves over 87% reduction in latch delay and 27% reduction of energy consumption over a conventional design.

TL;DR: A new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and requires smaller die area, and it is shown by simulation and analysis that the delay time is significantly reduced compared to a conventional dynamic latched comparator.

TL;DR: Design of a RF MEMS (Radio Frequency Micro Electro Mechanical system) capacitive shunt switch to study the switch performance which depends on various indices and Static analysis confirms the optimum dimensions of the switch that provide several advantages such as high isolation, low insertion loss and low pull in voltage in the switch circuit.

TL;DR: A matrix description has been proposed to describe the configurations of frequency compensating multistage amplifiers with feedback networks and according to simulations, the proposed configurations in both voltage and current states show excellence performance versus previous works.

TL;DR: A Silicon Carbide and Aluminum Nitride based DTMCPS (Double Touch Mode Capacitive Pressure Sensor) with a substrate notch with better performance than comparable designs reported in literature is introduced.

TL;DR: The proposed highly stable 8T-SRAM cell is capable to be arranged in a bit-interleaving fashion which can then use a conventional error correction code (ECC) to correct the single bit error caused by the exposer to cosmic radiation.

TL;DR: Simulation results such as Monte-Carlo analysis, eye diagram and noise analysis justify the proper performance of the proposed TIA which can be operated as a low-power building block in a 10 Gbps optical receiver system.

TL;DR: Lower gmCG without degrading the input matching, allows a large scaling factor for common source (CS) stage in noise cancelling technique, and adds a degree of freedom for transconductance of common gate stage (gmCG).

TL;DR: Three approximations of the Laplacian operator sα are introduced: Oustaloup, Matsuda, and Valsa by comparing their behaviors through two types of oscillator circuits and the exact solution is provided to investigate which approximation has the lowest error.

TL;DR: It is demonstrated by the experimental results that smartphone sensor data can reveal the health status of the user to some degree and smartphone can serve as an assistant for human health.

TL;DR: The possibility of realizing fractional capacitors by using carbon black nanostructured dielectrics is investigated and a dependance between the curing temperature and the fractional order has been shown.

TL;DR: The proposed analysis is applied to diverse types of RRAM cells, and a comparison between the performance of such cells is discussed, and the effect of the exponential memristor model on thememristor behaviour in terms of switching speed and the range of the Memristor resistance is discussed.

TL;DR: The proposed DOE and RSM based design optimization technique can be implemented for the design space exploration and optimization of complex MEMS devices which involve coupled multiphysics interactions.

TL;DR: This paper improves two key performance metrics, T − depth and T’−‹depth, for Quantum circuit realization using Clifford + T gates using Binary Decision Diagrams (BDD) as an intermediate representation for achieving scalability.

TL;DR: This paper utilizes voltage-controlled magnetic anisotropy spin transfer torque (VCMA-STT) magnetic tunnel junction (MTJ) as a memory element in accurate non-volatile full-adder and presents the corresponding writing circuit that improves 7.6x power consumption compared to the state-of-the-art work.

TL;DR: A transconductance-enhancement cascode Miller compensation technique is proposed for low supply-power, large or very large capacitive load multistage amplifiers and both the gain bandwidth and setting time are significantly improved.

TL;DR: A charge-sharing switching scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) in biomedical applications by using the charge sharing between two capacitor arrays to generate binary-weighted voltage-changes sequentially on the dummy capacitor.

TL;DR: It is confirmed that critical dimensions should be well-controlled to minimize the etch angles, which provide significant on-current reduction and program characteristics distortion and led to an appropriated standard to implement high stack 3D NAND flash memory.

TL;DR: The impact of the proposed nonvolatile logic gates for binary and ternary neural networks on energy consumption, delay, and area overhead reduction is demonstrated through circuit evaluations based on the parameters of the measured MTJ devices.

TL;DR: This paper implements a CIM scheme: ComRef (Complementary Reference) within STT-MRAM (Spin Transfer Torque Magnetic Random-Access Memory), and then compares its reliability and performance with the DualRef (Dual Reference) CIM implementation.

TL;DR: Experimental results reveal that the novel combination not only overcomes limitations of the above methods, but also improves delay and cost function (at least two times lower than the best previous QSCs).

TL;DR: An adaptive neural-fuzzy inference system (ANFIS) that predicts the droplet size generated in a flow-focusing microfluidic device based on six major parameters, that includes geometry, flow, and fluid properties is built.

TL;DR: A novel Analog to Digital Converter (ADC) framework for energy-aware acquisition of analog signals with Logic-in-Memory capabilities and outperforms other state of the art spin-based ADC designs by offering improved power dissipation.

TL;DR: This letter presents computations of the conductance of L-shaped graphene nanoribbons with two contacts and of T-shaped GANs with tree contacts, using tight-binding Hamiltonians and non-equilibrium Green's functions to compute their conductance.

TL;DR: A numerical multidimensional spline interpolation method for CAD implementation of silicon-on-insulator (SOI) four-gate transistors (G 4 FET) is presented and shown to work very well when independent variables do not exceed the range of training data set used for the model development.