Showing papers in "Microelectronics Reliability in 1988"

TL;DR: In this article, a method and apparatus for disposing a polymer film on an irregularly-shaped substrate at relatively high temperatures is presented, which is capable of being fashioned into circuit chip systems which are independently testable and which may be reconfigured after testing by removal of the polymer film itself.

TL;DR: In this paper, a method and circuit useful in the testing of integrated circuit chips (ICs) is presented. But this method is not suitable for the use of ICs in the real world.

TL;DR: The invention provides automatic test generation, including means for learning the characteristics of known good components and boards, and provides expert system programming for recording and analyzing test results data and for using this data to generate faster tests.

TL;DR: In this article, the performance of a feeding system in a paper mill having five units is discussed, out of which three are working almost on the same pattern, while the working of the other two are quite different.

TL;DR: In this paper, the electrodes of an IC chip are first coated each with an electroconductive thermally meltable adhesive resinous composition to form a resinous bump, and then the IC chip is mounted on the substrate with the adhesive-coated electrodes contacting with the respective electrodes of the substrate, and remelting and then solidifying the resinous bumps so that the electrodes are bonded and electrically connected together.

TL;DR: In this article, the authors proposed a very reliable semiconductor integrated circuit in which no deterioration of characteristics due to hot carriers occurs even when the circuit is constituted using short channel MOS transistors with an effective channel length of about 1 micron or less.

TL;DR: In this paper, a random search technique for finding the global minima of constrained nonlinear optimization problems is used to solve the reliability optimization problem of complex systems, where it is desired to maximize the reliability function of the system at the minimum possible cost.

TL;DR: In this article, the reliability analysis of the main part of a sugar mill is given, taking constant failure rates and general repair distribution the reliability of the system and mean time to system failure (MTSF) are evaluated.

TL;DR: The exact method of moments as mentioned in this paper is based on the exact and finite Taylor expansion of the top-event probability in terms of the basic-event probabilities in a fault tree, which allows calculation of the various moments with a readily quantifiable accuracy that can be arbitrarily improved.

TL;DR: In this article, a k-out-of-N : G redundant system with dependent failure rates, common-cause failures and repair facilities is presented, where the failure rates of the components increase as the number of components failed increases, while the repair rates are constant.

TL;DR: In this article, a fault indicating mechanism for an electronic system, such as a vehicle adaptive braking system, includes a series of visual indicators such as light emitting diodes, on one surface of the housing within which the electronic components comprising the system are sealed.

TL;DR: A VSLI chip is implemented with registers which log permanent and intermittent errors occurring within the chip as sensed by concurrent error detection circuitry (CED).

TL;DR: In this article, an availability analysis of a k-out-of-N:G redundant system with dependant failure rates, common-cause failures and repair facilities is presented.

TL;DR: In this article, a method for encapsulating microelectronic semiconductor and thin film devices was proposed. But, the method was not suitable for the case of metal foil capsules.

TL;DR: In this paper, a self-aligned photolithography process is used to form a thin oxide film on a side wall portion of the first polycrystalline silicon layer, using the silicon nitride film as a mask, and after the film is removed, a conductive film is formed on the entire surface.

TL;DR: In this article, a reconfigurable circuit operating in a test mode and a normal operating mode includes a memory array (10) which has a row decoder (12) for addressing the memory elements therein, and a fused switch (18) for referencing the output circuits thereon to either a standard reference voltage or an external reference voltage.

TL;DR: In this article, the mean time to system failure, steady state availablities and the impact of shocks on these are studied in two systems each consisting of one unit, and the effect of the preventive maintenance on MTSF and steady-state availabilities is investigated.

TL;DR: In this paper, the authors summarized four replacement policies for an n-unit parallel redundant system, and the expected cost rates for each policy were obtained and the optimum policies to minimize the expected costs were discussed.

TL;DR: A design and method of exhaustively verifying the boolean functionality of both combinational and sequential cells for Application Specific Integrted Circuit gate array and standard cell libraries is provided.

TL;DR: Disclosed is a method which speeds up interpretive test program code execution and allows rapid changes to the test code.

TL;DR: In this article, a process for the burn-in of either or both analog and digital integrated circuits where the various functions in the individual circuits are tested continuously and individually, while the circuits are cyclically caused to work at extreme temperatures, and the test is stopped when a predetermined error rate has been reached.

TL;DR: In this paper, a flexible beam lead frame is used for testing an IC chip at a given test position with respect to the fixture by inserting the positioning pin elements into the positioning perforations (26) through said window.

TL;DR: In this paper, an integrated electronic circuit comprising a microprocessor for executing instructions, an instruction cache for storing instructions for execution by the microprocessor, and circuitry for exchanging respective byte positions of at least two bytes of a respective instruction stored by the instruction cache is provided.

TL;DR: It is shown that metastable behavior can be avoided by usage of quantum synchronizers in principle, but not in practice, and that conventional synchronizers unavoidably show metastablebehavior in principle; but only in practice if properly designed.

TL;DR: In this article, a test structure for an integrated circuit for determining the incidence of various conduction effects on given layers and separating the surface effects from the wedge effects and the periphery effects into two perpendicular directions was proposed.

TL;DR: A semiconductor integrated circuit has a plurality of circuits to be tested for verification of operation thereof and first, second and third scanning registers to be used for self-testing, and it further has a register (3) for delay.

TL;DR: In this paper, a method for addressing redundant elements of an integrated circuit memory is presented, which consists of associating a battery with a row/column address pair, memorizing, through the blowing of certain fuses in the battery after the testing of a memory element, the address either of a column element if the faulty element is a row element or that of a row elements if the fault is a faulty element.

TL;DR: This paper identifies, analyzes and classifies various aspects of distributed systems.

TL;DR: In this article, an investigation of accelerated moisture resistance test was done using various types of samples through temperature-humidity-bias tests, and the results showed that the accelerated factor are specified by water vapor pressure (PH2O), temperature (T), and applied bias (V).

TL;DR: In this paper, a method of using the component data to modify the beta prior distribution is proposed and it is seen that such a method leads to an improvement in the lower confidence limit, that is, its conservatism is decreased.