Showing papers in "Microelectronics Reliability in 2002"

TL;DR: This compendium provides the main failure modes, the physical or chemical processes that lead to the failure, and reports some major technological countermeasures, which are used for realizing the very stringent reliability requirements imposed in particular by the electrical traction applications.

TL;DR: Several of the extraction methods currently used to determine the value of threshold voltage from the measured drain current versus gate voltage transfer characteristics, focusing specially on single-crystal bulk MOSFETs are reviewed.

TL;DR: An overview of recent issues concerning the low frequency (LF) noise in modern CMOS devices is given and the approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are presented and illustrated through experimental results obtained on advanced CMOS generations.

TL;DR: A rate-dependent plasticity was characterized to represent the inelastic deformation behavior for Sn–Ag-based lead-free solders to validate the validation of fracture strength of solder joints resulting from the tensile tests was verified with package-mounted board level reliability tests.

TL;DR: It was found that Ni bumps formed better interconnections than bumpless FCOF packages, and the performance of the ACF interconnects were affected by the degree of cured ACF, which was determined by the bonding temperature.

TL;DR: The role of hydrogen is reviewed in radiation-induced interface-trap formation in metal and polycrystalline-Si-gate devices, with an emphasis on understanding the transport and reaction mechanisms responsible for defect formation.

TL;DR: In this article, an electroless nickel-phosphorous (Ni-P) layer was deposited on the Cu pad of the flexible substrate as a diffusion barrier between Cu and the solder materials.

TL;DR: The authors found that the stress at a solder joint differs depending on the package structure, even if the motherboard strain is the same, and that underfilling eases the motherboard strains and disperses the stress concentrated on a solder Joint.

TL;DR: This article classifies the commonly used and referred to reliability prediction methodologies into some categories easy to understand, and recommends to use the methods in a combined fashion (simultaneously or successively) along the product development process.

TL;DR: A new dopant model to overcome problems for 3-dimensional DD simulations is proposed by employing the idea of splitting the Coulomb potential between the long-range and short-range parts associated with discretized dopants.

TL;DR: Progress of silicon IC technologies for the past 30 years is described at first, the difficulties of the further downsizing for future are explained in detail, and the efforts to solve difficulties and the possible solutions are described.

TL;DR: As the aggressive scaling of the metal-oxide-semiconductor structure continues, new reliability challenges in gateDielectric materials now came across as the gate dielectric thickness will be further down scaled to its technological constraint.

TL;DR: In this paper, a new distributed active MOSFET rail clamp network is introduced that offers surprising advantages in layout area efficiency, bus resistance tolerance, design modularity, and ease of reuse.

TL;DR: Any company that produces a safety or emission regulated product should assume that every complaint or return of that product is a failure, and take on full responsibility for ascertaining the root cause.

TL;DR: The methodology of thermal transient measurements in details is discussed, including the compensation of second order effects as non-linearity, non-constant powering etc.

TL;DR: From the performance test conducted on the MHP cooling modules with woven wicks, it is seen that the T jc (junction temperature of the processor) satisfies a demand condition of being between 0 and 100 ° C, which shows the stability of the M HP as a cooling system of notebook PCs.

TL;DR: The deposition of nickel and gold onto the I/O pad surfaces enables the subsequent use of both wire bond and flip chip (lead-based and lead-free alloys) interconnect methods and no critical nickel consumption was detected during reflow.

TL;DR: Recent achievements indicate that the present constraints for using Si-based materials in optoelectronics are mainly technological rather than physical, and once these technological difficulties are resolved, the realization and applications of Si-OEICs will grow rapidly.

TL;DR: A strong dependence of curing degree of the ACFs is shown on the chance of short-circuiting between adjacent joints under field effects, which may lead to abnormal display segments/pixels of the LCD.

TL;DR: In this article, the conduction mechanisms and the microstructure of rf sputtered Ta2O5 on Si, before and after oxygen annealing at high temperatures (873, 1123 K; 30 min) have been investigated.

TL;DR: Extension of the current fabrication processes to low (∼120 °C) temperature, enabling fabrication of flexible imaging array (on plastic) substrates, will be discussed along with preliminary results in terms of static characteristics of the active matrix switch.

TL;DR: Thermal conductivity and normalized thermal resistance measurements on eight bulk solders and three tri-layer samples were performed using the laser flash technique and it is shown that the total intrinsic thermal resistance measurement is confounded by sample voiding.

TL;DR: Experimental methods were developed to measure the surface tension and the contact angle of underfills at temperatures over 100 °C and showed that the contact angles for underfill on a substrate was time dependent, and the interaction between underfill and substrate affects not only gap filling, but also filleting.

TL;DR: It is reported that process-induced mechanical stress affects the performance of short-channel MOSFETs, and focuses on the effect of a plasma-enhanced CVD nitride contact-etch-stop layer.

TL;DR: A new methodology is proposed which utilizes strain data generated by this technique for predicting solder joint fatigue life for any desired package configuration based on a reference configuration which obviates brute-force temperature cycle testing for the qualification of every new variation of an existing package configuration.

TL;DR: The proposed method, begins with the experimental determination of transient thermal response followed by numerical extraction of the time constants and amplitudes for the significant exponential terms, is applied to a number of commercial Smartpack modules to obtain a dynamic model that can be used in circuit and numerical simulators, in order to predict the dynamic thermal behaviour of the device under any working condition.