Showing papers in "Microelectronics Reliability in 2005"

TL;DR: A comprehensive model for NBTI phenomena within the framework of the standard reaction–diffusion model is constructed and it is demonstrated how to solve the reaction-diffusion equations in a way that emphasizes the physical aspects of the degradation process and allows easy generalization of the existing work.

TL;DR: It is shown that the static noise margin of a SRAM memory cell is degraded by NBTI and the relative degradation increases as the operating voltage decreases, and there is evidence that donor interface state generation during N BTI stress is a significant component of the transistor degradation.

TL;DR: It is concluded that SiO2-based dielectrics can provide reliable gate dielectric, even to a thickness of 1 nm, and that CMOS scaling may well be viable for the 50 nm technology node.

TL;DR: An overview of evolution of transistor parameters under negative bias temperature instability stress conditions commonly observed in p-MOSFETs in recent technologies is presented and a physical model is proposed which could be used to more accurately predict the transistor degradation.

TL;DR: In this article, 3D finite element analysis (FEA) based on a multilevel submodeling approach in combination with high-resolution Moire interferometry is employed to examine the packaging effect on low k interconnect reliability.

TL;DR: A full device level reliability study of GaN-on-Si HFETs and environmental tests such as autoclave and ESD demonstrate the ruggedness of the material system and technology.

TL;DR: A gas flow model is used to show that the helium bomb test and bubble test methods in MIL-STD-883E are not applicable for hermeticity testing of packages with small internal volumes, typically encountered for microelectromechanical systems (MEMS).

TL;DR: A new approach to extract accurate compact models for fast electro-thermal simulations of IGBT modules used in hybrid electric vehicles is presented, showing that the proposed methodology brings advantages in terms of increased reliability, reduction of the costs, and shortening of the design cycle.

TL;DR: It was found that successful vacuum packaging could be achieved through the optimization of the bonding process by reducing leakage and the deposition of titanium coating for reducing out-gassing inside the cavity.

TL;DR: This paper proposes several examples where this problem of realistic mission profiles has been solved by proper analysis of the stresses, by dedicated physical modeling, and by efficient calculation tools.

TL;DR: The observed power low time dependencies of threshold voltage shifts are found to be affected mostly by the oxide trapped charge, and the model that explains experimental data is discussed in details.

TL;DR: A new test method called Capacitively Coupled Transmission Line Pulsing cc-TLP is applied to different test circuits which were mounted on specially designed package emulators with a defined background capacitance.

TL;DR: To obtain the true process capability, modified confidence bounds and critical values are presented to practitioners for their factory applications and show that the estimator using the sample data contaminated by the measurement errors severely underestimates the capability.

TL;DR: The paper illustrates the investigation on the contact dynamics between the rotor and bearing hub and the effects of gas-lubricated bearing which decrease the possibility of friction, contact, and wear in electrostatic micromotors.

TL;DR: The effort to predict delamination related IC & packaging reliability problems is presented, and several reliable non-linear Finite Element models are developed, able to predict the reliability impact of delamination on wire failures, different package structures, and passivation cracks in IC-packages.

TL;DR: A figure of merit is proposed, derived from a predictive model, which quantifies the capacitive RF MEMS reliability and open the door to the prediction of lifetime as well as its optimization and/or acceleration for testing.

TL;DR: From the experimental and theoretical studies, the roles of nitrogen are two folds, i.e., it provides more reaction sites, and it can also enhance the NBTI reaction by reducing the reaction energy.

TL;DR: In this article, a power supply protection clamp is presented which incorporates feedback techniques to improve ESD and normal operational mode behavior using a short duration RC trigger, which enables the clamp to tolerate very fast power supply ramp rates and exhibit reduced area and leakage.

TL;DR: The effect of inhomogeneous negative bias temperature stress (NBTS) applied to p-MOS transistors under analog and RF CMOS operating conditions is investigated and an analytical model is derived to physically explain the effect of stress on the device characteristics.

TL;DR: Long-term challenges for different applications of high k and low k materials are highlighted, and nanotechnology has the potential to deliver new nano-structured materials to support these requirements, but significant challenges must be overcome before they can be useful.

TL;DR: The results showed the decrease in the shear strength of the interface with aging time and temperature, influenced by IMC growth and Zn grain coarsening.

TL;DR: A 3000 hour DC life test is described and the last results derived from the data treatment of this test are presented and the transistor parameters show an evolution strictly related to the biasing point.

TL;DR: The performance of interconnects containing micro- and meso-porous interlevel dielectrics is influenced by material selection, integration scheme and virtually all fabrication steps, and it is generally reported that the reliability margin of the dielectric/barrier/copper system is shrinking.

TL;DR: This paper discusses several aspects of N-LDMOS hot carrier reliability including measurement techniques, degradation mechanism, and the effect of both one- and two-dimensional layout effects on the hot carrier degradation behavior of these devices.

TL;DR: An improved understanding of the wire bonding process was achieved by showing the dependence of the visual appearance of the Wire Bond process parameters on wire bond process parameters.

TL;DR: In the case of negative bias stressing, hole tunnelling from the silicon valence band to oxygen vacancy defects Si o Si o is shown to be responsible for positive oxide-trapped charge buildup, while subsequent electro-chemical reactions of interfacial precursors Sis–H with the charged oxide traps Si o + Si o and H+ ions are proposed to beresponsible for interface trap buildup.

TL;DR: In this article, the authors examined the diverse connotations of the term quality and proposed reshaped definitions of r-reliability and durability, and clarified the procedure to improve reliability and to identify the failure mode in order to find for right solutions and recommend a generalized life-stress failure model.

TL;DR: In this study, laboratory and field experiments were conducted to determine the junction temperatures of the main heat dissipating components in the amplifier circuit, and the performance of the current thermal grease compound with a range of commercially available alternatives.

TL;DR: Two ANN models based on inverse modeling are developed to simulate the behavior of the capacitive humidity sensor (CHS), which can be used to compensate the effect of ambient temperature error.

TL;DR: Simulation results show that, at a given bias conditions, the reduction of lateral electric field peak at the silicon surface due to the implementation of the retrograde doping profile accounts for the observed reduction of the hot carrier degradation effect.