Showing papers in "Microelectronics Reliability in 2012"

TL;DR: This paper provides the groundwork for an understanding of the reliability issues of LEDs across the supply chain and identifies the relationships between failure causes and their associated mechanisms, issues in thermal standardization, and critical areas of investigation and development in LED technology and reliability.

TL;DR: The present review summarizes the basic principles of how to model stochastic defect transitions with a particular focus on multi-state defects and introduces the relatively simple semiclassical approximation of multiphonon theory, which already provides a much better description.

TL;DR: This paper reviews the development of MTJ device technology and formulates considerations regarding its memory application, including SPRAM memory cell structure and operation, write voltage limitation, and thermal stability.

TL;DR: New types of die attach pastes comprising micron-sized Ag particles hybridized with submicron- sized Ag particles were considered as lead-free die attach materials for SiC power semiconductors, and the Ag die attach bond layer was stable against thermal cycles between −40 °C and 300 ° C.

TL;DR: A review of recent research on suitable replacement alloys as well as traditional Pb–Sn alloys, collating relevant properties and identifying areas where further development is required is concluded.

TL;DR: The finding of the study indicates that the best SAC composition for drop impact performance is not necessarily the best composition for optimum thermal cycling reliability, and the level of Ag-content in SAC solder alloy can be an advantage or a disadvantage depending on the application, package and reliability requirements.

TL;DR: This paper classifies firstly all the possible failures of STT-MRAM into “soft errors” and “hard errors’, and analyzes their impact on the memory reliability, and can find some efficient design solutions to address respectively these two types of errors and improve the reliability of STTs.

TL;DR: Time-Dependent Dielectric Breakdown models for silica(SiO 2 )-based dielectrics are revisited so as to better understand the ability of each model to explain quantitatively the generally accepted TDDB observations.

TL;DR: Through-silicon via (TSV) has been used for 3-dimentional integrated circuits and results suggest that Cu stress may lead to reliability as well as integration issues, while Si stress might lead to device performance concerns.

TL;DR: Various low temperature bonding technologies are reviewed and introduced, as well as the latest developments in world-wide companies and research institutes, to solve the performance degradation issue of the integrated devices.

TL;DR: An integrated multi-fin heat sink design with a fan on MCPCB substrate for a high-power LED array using the finite element method (FEM) provides useful information for LED heat dissipation and chip temperature estimation.

TL;DR: A thermal analysis of high power LED packages implementing chip-on-board (COB) architecture combined with power electronic substrate focusing on heat spreading effect is conducted, bypassing the need for detailed computational simulations using FEA.

TL;DR: A method for calendar ageing quantification of power batteries taking into account the State of Charge (SOC) and temperature ( T ) effects is presented, focused on a single parameter identified from Electrochemical Impedance Spectroscopy tests performed according to a specific protocol regarding thermal and electrical kinetics.

TL;DR: Self-healing concepts will be proposed to further improve LED’s reliability in order to increase reliability of SSL devices, components presenting self-repairing properties could be implemented.

TL;DR: Comparison analysis based on Monte Carlo simulation exhibits that the proposed design is capable of mitigating impact of Vt variation to a large extent.

TL;DR: A dynamic mechanical analysis was used to investigate the changes in the mechanical properties of the epoxy composites, which included neat epoxy and epoxy with various concentrations of graphene-based fillers, which had the highest thermal conductivity and storage modulus.

TL;DR: This paper summarizes the effects of alloying elements and particles on the wettability, mechanical properties, creep behavior, microstructures, etc. of SnAg-based lead free solder alloys.

TL;DR: The classification of Cu bonding, bonding mechanisms, process developments, its microstructure evolution, as well as other characterizations are reviewed.

TL;DR: This paper discusses different memory technologies based on alternative principles of information storage, highlights the most promising candidates for future universal memory, and makes an overview of the current state-of-the-art of these technologies.

TL;DR: Thermal performances of 3D IC integration system-in-package (SiP) with TSV (through silicon via) interposer/chip are investigated based on heat-transfer and CFD (computational fluid dynamic) analyses.

TL;DR: The particle filter approach, developed using the system model based on the VCE(ON), was demonstrated to provide mean time to failure estimates of IGBT remaining useful life with an error of approximately 20% at the time of anomaly detection.

TL;DR: The accelerated degradation of light bars was tested under different stresses called junction temperatures, which result from the combination of current and ambient temperature, and shows that the failure time of a light bar under operating conditions is about 11,571 h.

TL;DR: For the first time Laser Doppler Vibrometer measurements and thermal imaging were employed to determine the temperature-dependent deformations of bond wires at different frequencies under operation conditions to facilitate more precise life-time predictions of power modules in long term usage.

TL;DR: The COP module under natural and forced convection conditions was studied, and the results showed that the junction-to-air thermal resistances are sensitive to the flow conditions, but not for thermal resistsances from the junction to aluminum substrate and to heat sink.

TL;DR: The FEM model for bond wire fatigue achieves a good reproduction of the measured dependence of cycle numbers on Δ T j and a low impact of absolute temperature on N cyc is confirmed both by experiment and theory.

TL;DR: Due to the high thermal conductivity of CNT, the addition of C NTs into the SAC305 solder reduces the total thermal resistance and chip temperature of the LEDs device, and the thermal management of the LED devices is improved accordingly.

TL;DR: The dual stage model developed in this paper provides a mathematical formulation for modeling anomalous moisture diffusion behavior using commercial finite element analysis software and generates reasonable results for the diffusive properties and display outstanding experimental fits.

TL;DR: The failure mechanism of solder interconnection for c-Si PV Module is proved and water-jet techniques for cross-section and SEM are used to analyze the factor of resistance change and efficiency degradation.

TL;DR: Orientation imaging microscopy was adopted to characterize the microstructural changes in Sn–Ag-based solder interconnects during thermal cycling and shear testing, finding cracks were propagated intergranularly in the recrystallized microstructure.

TL;DR: It was found that the thermal improvement of the LED module led to the enhancement of the light output power and radiant intensity and the temperature calibrating factor, 0.046 nm/°C, was calculated from the peak wavelengths of the LEDs modules.