Showing papers in "Microelectronics Reliability in 2014"

TL;DR: This review discusses fundamental research activity and its focus on the solidification and interfacial reactions of Sn-based solder systems, and first explains the reactions between common base materials, coatings, and metallisations, and then proceed to more complex systems with additional alloying elements.

TL;DR: This review paper focuses on the reliability issues such as soft-error, electrical noise and process variation, and their impact on TFET based circuit performance compared to sub-threshold CMOS.

TL;DR: The long voyage of TiO2 based RRAM is represented, towards the improvement of the reliability aspects of the device performance in a comprehensive manner and the prediction of possible future research trends are predicted.

TL;DR: A compact model of MTJ with STT stochastic behavior is proposed, in which technical variations and temperature evaluation are properly integrated and its accurate performances allow a more realistic reliability analysis involving the influences of ambient environment and technical process.

TL;DR: The results indicate that both the thickness and roughness of the IMC layer have influence on the strength and failure mode of the solder joint.

TL;DR: A capacitance ageing law is proposed based on the identification of voltage and temperature degradation kinetics from three experimental floating ageing tests performed at different Voltage and temperature constraints.

TL;DR: It is proposed to use the active thermal management to reduce the switching losses or to move them to less stressed devices, during transients, such as a module can reach an higher current, without violating thermal constraints, and the need of overdesign can be reduced.

TL;DR: To enable future technology scaling, a co-optimization approach is essential including interconnect process development, circuit design and chip integration to enable overall EM reliability and optimized performance.

TL;DR: From microstructures evaluation, it was clear that composite solders containing ZrO 2 ceramic nano-particles significantly impact on the formation of intermetallic compounds (IMCs) at their interfaces as well as refined microstructure in the solder ball regions.

TL;DR: In this article, the reliability risk factors of high temperature, high voltage and electrochemical O2 generation during anodic bonding are discussed, and electrical interconnections through a hermetic package, i.e. electrical feedthrough, is discussed.

TL;DR: A bi-exponential model for the degradation curve of HPWLEDs is presented, which performs better than the exponential model based on the two-staged method and the estimation of the model parameters are easily obtained using the nonlinear least square method.

TL;DR: In this article, the authors investigated the reliability enhancement by integrated liquid cooling structure in HEV/EV IGBT module and found that the thermal resistance of junction to heat sink can be reduced more than 50% by direct liquid cooling as eliminating thermal grease layer, so both active and passive temperature swings decrease significantly.

TL;DR: The growth of the interfacial Cu–Sn intermetallic compounds (IMC) layer (Cu6Sn5 + Cu3Sn) of Sn37Pb/Cu solder joints subjected to isothermal aging exhibited a linear function of the square root of aging time, indicating that the formation of Cu– Sn IMC was mainly controlled by the diffusion mechanism.

TL;DR: This paper proposes an easy-to-develop and flexible FPGA-based fault injection technique that utilizes debugging facilities of Altera FPGAs in order to inject single event upset and multiple bit upset fault models in both flip-flops and memory units.

TL;DR: The model can successfully predict long time DC and AC stress data and has been used to determine device degradation at end of life as EOT is scaled for different HKMG devices.

TL;DR: Evaluating the impact on ION and IOFF currents of variations in process parameters for a set of predictive FinFET technologies from 20 nm to 7 nm is evaluated to identify relevant behavioural standards with respect to the use of FinFet technology in digital designs.

TL;DR: The DG-OTFT device performs better than SG-OT FT mainly in terms of mobility, on–off current ratio and sub-threshold slope, and bootstrapping technique is applied to the dual gate inverters that further boosts the noise margin and gain for DLL and ZVLL configurations.

TL;DR: The results show that the failure mechanisms of BGA lead-free solder joint vary as the acceleration PSD amplitude increases, which is a concern in microelectronic industry.

TL;DR: Evaluated heat dissipation efficiency of high power LED package operating under multiple vibrating fans found the best performance relative to natural convection was found to be at (δ = 0.1) which decreased the thermal resistance using single fan by about 38%, whereas the dual fan accounted for 49.5% in case of configuration A, and 50.6% for configuration B.

TL;DR: One of the first attempts to use a non-homogeneous gamma process to model the threshold voltage degradation of a commercial SiC MOSFET is proposed and is described as a first step toward prognostic of Remaining Useful Life in embedded power electronics.

TL;DR: The intermetallic phases and the microstructure of standard chip to substrate solder joint will be analysed and compared to deteriorated joints coming from modules which have undergone an active thermal cycling.

TL;DR: The results show that increasing the exposure time leads to degradation of BPA-PC optical properties, i.e. decrease of light transmission and increase in the yellowing index (YI).

TL;DR: The results indicate that the fracture is inside the bulk solder in low speed shear test regardless of the aging effect, thus the maximum load reflects the solder strength rather than the interfacial strength.

TL;DR: In this paper, a new form of the electrothermal model of the ferromagnetic core for SPICE and the way in which the parameters of the model are determined are described.

TL;DR: Results show that thermal ageing leads to a significant decrease in the luminous flux and chromatic properties of plates, and a significant decay of CCT, postulating that the degradation of the remote phosphor plates affects the efficiency of light and the colour of emitted light as well.

TL;DR: This review is dedicated to the scientific understanding of the various regimes of breakdown in high-κ gate stacks using electrical, physical and statistical techniques along with an application of these findings to predict the impact they will have from a technology perspective.

TL;DR: The organic complementary SRAM cell is designed such that the access transistors are pentacene based p-type instead of often used n-type transistor and shows reasonably lower write access time in comparison to the cell with n- type access OTFTs.

TL;DR: The results showed that the fatigue life of the three solders increases as the solder thermal interface thickness increases, and the optimal solder material of choice is given as SAC405, which has higher operational life span and good reliability capabilities.

TL;DR: X-ray observation and shear tests revealed that the increase of solder paste volume significantly decreases the void percentage in the solder layer and thus improved the shear strength of the packages.

TL;DR: This study presents a qualitative perspective to identifying and understanding these trade-offs and probing the various sources of variability in high-κ RRAM.