Showing papers in "Microelectronics Reliability in 2021"

TL;DR: In this article, the thermal performance of nano-enhanced phase change material (NePCM) based thermal energy storage system for cooling of electronic components was analyzed for a fixed volume fraction of fin material.

TL;DR: In this article, a novel method fusing the incremental capacity analysis (ICA) and Gaussian process regression (GPR) for RUL prediction of lithium-ion batteries is proposed.

TL;DR: In this paper, the board-level reliability of the assembly of BGA components was investigated, and three types of assemblies were compared: mixed (hybrid) Sn-Bi/SAC305 assembly, which is made by soldering BGAs with SAC305 solder balls using eutectic Sn Bi solder pastes so that the low reflow temperature avoids the SAC 305 solder joints from being molten, homogeneous eUTectic sn-bi assembly, made with solder balls and pastes that are both eutective Sn-bi and SAC-305

TL;DR: In this paper, a review of the constituents of no-clean flux, their characteristics and their compositional ranges are presented, and the effects of flux residue on the underfill and reliability of flip-chip packaging are discussed.

TL;DR: In this paper, the effect of die encapsulation on the reliability of the assembly was also assessed by employing a protective foil, and the successful integration of ultra-thin chip on the low-cost printed flexible substrate was obtained by optimizing the bonding parameters with both anisotropic conductive films (ACF) and ACP.

TL;DR: In this paper, a thermo-electric accelerated test (TEC) method, as well as its corresponding failure mechanism, was discussed to consider the feasibility of reducing the reliability test duration.

TL;DR: In this paper, the impact of interface trap charges (ITCs) on electrical characteristics of dielectric pocket SOI-TFETs proposed for the reduction of ambipolar conduction and improvement of high-frequency (HF) performances has been demonstrated in details.

TL;DR: In this paper, the authors present an extensive survey on the advance of low temperature Cu-based bonding technologies and introduce low temperature SiO2 hybrid bonding as an emerging bonding technology to solve the coplanarity and filling issue.

TL;DR: In this paper, the impact of interface trap charges (ITCs) on the electrical performance characteristics of a source pocket engineered (SPE) Ge/Si heterojunction (HJ) vertical TFET (V-TFET) with an HfO2/Al2O3 laterally stacked heterogeneous gate oxide (LSHGO) structure was reported.

TL;DR: In this paper, a spin-coated Schottky barrier Diodes (SBD) was fabricated and the electrical properties of the fabricated SBD were analyzed at various temperatures and compared with each other.

TL;DR: In this article, the authors studied the radiation response of three different 65 CMOS planar technologies at the ultra-high doses expected to be reached in the HL-LHC, the upgraded large hadron collider of CERN.

TL;DR: This work performs a two-stage design optimization of the folded beam multi-resonant piezoelectric energy harvester using evolutionary algorithm and a subsequent local optimization by classical non-linear programming, which resulted in designs, which shows promising characteristics in simulation.

TL;DR: In this paper, an attempt was made through an experimental study to estimate the service life of high power LED (HPLED) through an array of 77W capacity HPLED was built on an aluminum heat sink.

TL;DR: In this article, the effect of porous Cu addition on the microstructure, IMC layer, shear behavior and hardness of the solder joints during isothermal aging was studied.

TL;DR: In this article, the impact of intermetallic compound (IMC) thickness on thermo-mechanical reliability of lead-free SnAgCu solder joints in crystalline silicon solar cell assembly with regard to fatigue life was evaluated.

TL;DR: In this article, a review of the applications of micro-Raman spectroscopy (μRS) to characterize the residual strain and/or stress in electronic packaging is presented.

TL;DR: In this paper, a cross-sectioned SAC305 solder joint was used for testing for electromigration and a crack and void started to form in an example experiment, and their evolution was recorded using real-time imaging.

TL;DR: In this paper, the COTS power transistors based in GaN were exposed to TID effects by 10-keV X-rays and were tested in the On- and Off-state bias conditions.

TL;DR: In this article, the effect of introducing zinc acetate and chloride salts on the structure, chemical and physical properties of the obtained zinc oxide (ZnO) films was investigated, and Scanning electron microscope (SEM) and atomic force microcopy (AFM) were utilized to both justify the nanostructure growth of the ZnO thick films deposited by hydrothermal growth method and to identify their morphology.

TL;DR: Evaluation of deep neural networks reliability against fault injection attacks, which can serve as a basis to outline the susceptibility of DNNs to physical attacks which can be considered a viable attack vector whenever a device is deployed in hostile environment.

TL;DR: In this paper, a large-scale molecular dynamic simulation is performed to investigate the concentration-dependent vacancy volume relaxation in Al, Cu, and Au lattice, and the simulation results are calculated and correlated to the microstructure change based on MD results.

TL;DR: A learning method of a wafer map classifier that can process data of an undefined pattern without compromising the classifier's accuracy is presented and its performance is evaluated by applying the learning method to a model widely known in image classification.

TL;DR: In this paper, an energy-based lifetime prediction method is proposed for failure of IGBT modules by explicit emulation of solder layer degradation, where the large-area solder layer is evenly divided into meshed elements, birth and death technique in finite element analysis (FEA) is used to successively emulate crack propagation.

TL;DR: This paper evaluates the performance of three system-level models based on magnetostatic finite element simulations, including a lookup table, a semi-analytical compact model and a parametric reduced order model constructed by matrix interpolation method.

TL;DR: In this article, an overview on some state-of-the-art characterization methods of 4H-SiC metal oxide semiconductor field effect transistors (MOSFETs) is presented.

TL;DR: In this paper, the formation of radial cracks in copper metallized through-glass via (TGV) substrates made of Corning® high purity fused silica (HPFS® fusedsilica), after subjection to 420°C annealing treatment was investigated.

TL;DR: Overall, it is shown that, by applying the proposed various DL-based methods, one can largely increase the level of automation in hardware assurance of digital ICs and improve its accuracy.

TL;DR: In this article, the impact of threading dislocations in the epitaxial layer of a GaN power switching device is discussed and the effects of substrate type on dislocation density are discussed for optimization of switching two terminal devices.

TL;DR: In this article, the effects of pitch distance, temperature, voltage, and contamination on the leak current measured on surface insulation resistance (SIR) test boards were investigated using the DoE methodology.

TL;DR: The prediction using cuckoo search-based extreme learning machine for junction temperature is developed to reach a high-accuracy solution without measured-location sensitivity and results reveal that the determination coefficient (R2) by ICS-ELM model achieves the optimal value, i.e. 0.9975.