Showing papers in "Microprocessing and Microprogramming in 1989"

TL;DR: A class of preemptive, priority-driven algorithms can be used to find feasible schedules with a small average error that finds feasible schedules meeting the time constraints and minimizing the total error of all tasks, whenever feasible schedules exist.

TL;DR: The paper will give an outline of network topology and the ideas for the operating system basic structure and the design philosophy of massively parallel distributed computing systems.

TL;DR: The procedural interface provides a very flexible way to simulate a neural network application in a non-neural environment and an interruptive mode is supported that allows for the automated optimization of the network topology and its parameters.

TL;DR: A number of CAE tools will be described supporting the realisation of PLC application projects and provide an environment for graphical and textual programming, module library administration, documentation, and application program generation.

TL;DR: Cellular automata generating cyclic groups are proposed for on-chip deterministic test pattern generation and the method of selection of the most appropriate group rule has been reported.

TL;DR: A method and a graphic language for specification of real-time systems that is modelled at different abstraction levels using the same language constructs so that the specification models can be transformed automatically to a selected implementation.

TL;DR: A declarative neural network description language is presented as part of the neural network simulator that is developing at Universitat Stuttgart, a tool to build and test medium sized neural networks and to obtain technical experience in the construction of network simulators.

TL;DR: This paper presents a simple and efficient heuristic algorithm for assigning program tasks with precedence and communication constraints to the PEs in a Message-based Multiple-bus Multiprocessor System, M 3, so that the total execution time for the program is minimized.

TL;DR: This work presents a parallel algorithm to evaluate the reliability of multiprocessor systems with degradable nodes on SIMD hypercube computers that is general in the sense that it do not impose any restriction in the problem space dimenssions and is adaptable to any hypercube dimension.

TL;DR: How the transputer family of processors' scheduling and parallel operations are implemented is described, which allows more than one process to run on one processor.

TL;DR: A protocol for file locking and deadlock detection in a multi-user Ada environment that ensures integrity of files concurrently accessed by several tasks belonging either to the same or to distinct Ada programs.

TL;DR: Implementation of these arbiters considering both equal acceptance and priority to infrequent or i / o requests is presented, including introduction of self-checking circuits to improve the reliability.

TL;DR: An analytical technique to optimize the placement of functional blocks as a constrained non-linear optimization problem that incorporates the dimensions of fixed-shaped blocks as well as the bounds on the aspect ratios of variable- shaped blocks.

TL;DR: Two definitions for locality and storage utilization are given and applied to available data with explanations based on results from statistical linguistics, and the split organization shows better performance for the instruction cache with efficiency higher than for the data cache of the same size.

TL;DR: In this paper, a prototype version of a fully distributed calendar and appointment system implemented on a network of workstations is described, including the software architecture, the appointment scheduling strategies and heuristics, the distributed implementation language, and the graphical user interface.

TL;DR: Testing CMOS circuits for stuck-open faults has been a matter of concern in research for a few years but seems not to fit well with more recent practical results, because stuck- open faults seem better testable than expected under worst-case assumptions.

TL;DR: This paper introduces two new static task scheduling algorithms, called Heavy Node First (HNF) and Weighted Length (WL), which considers a more global view of the program graph, taking into account the weight of the successor subgraph for each node.

TL;DR: New closed-form solutions for the reliability, performability and computational availability in the case of closed and homogeneous gracefully degrading processor arrays are derived using the behavioral decomposition technique.

TL;DR: The implementation of the principle of systems semantics on a computer done in Esprit project 881, “Forfun” is described, which includes defining a computer understandable system description language, executable semantic functions, some computer assistance for transformational design, and a multi-user environment.

TL;DR: The linear-throughout Semantic Database Machine is an attempt to bring a massively parallel database machine closer to realization by building a more homogeneous database system in which processors and disks are combined together.

TL;DR: The purpose of this note is formal description of telematic services that allows their modular decomposition, and the formal description technique LOTOS is chosen for application.

TL;DR: The paper stresses the constraints that affect the support because of occam staticity, and describes a possible support to a parallel object model, called PO for a massively parrallel architecture, which has been implemented in occam for an architecture based on several Transputers.

TL;DR: The design tool, PARUT (Post-programming Automated Recovery UTility) provides a method of enhancing existing program code to optimise the recovery capability following a transient disturbance.

TL;DR: An object-oriented database system that supports databases consisting of an extensible set of self-sufficient modules loosely coupled with each other, which makes it suitable for storage of data in areas such as CAD/CAM, office information systems and artificial intelligence.

TL;DR: A structured analysis (RT-SA) based method for SQ/HW-partitioning of real-time embedded systems and the principles of supporting simulation based analyses are presented.

TL;DR: The Gate Forest approach for testable module compilation is introduced and with suitable tooling architectured in an open CAD environment, this allows for almost Full Custom layout efficiency.

TL;DR: A method, based on the concept of folding, for partitioning wavefront algorithms on 2-D meshes of Transputers of fixed size, has been applied to the solution of triangular system equations.

TL;DR: This paper allows the designer to indicate a set of bindings between behaviour and structure in order to add some of the designer's knowledge to the design process, and these bindings can be used to exclude inefficient designs.