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Showing papers in "Microprocessors and Microsystems in 2013"


Journal ArticleDOI
TL;DR: This paper will show how the ACROSS MP soC overcomes the limitations of existing MPSoC architectures in order to make the multi-core technology available to the safety-critical domain.

59 citations


Journal ArticleDOI
TL;DR: A novel energy-aware scheduling algorithm named Cycle Conserve Dynamic Voltage Scaling for Sporadic Tasks (CC-DVSST) algorithm which is an improvement to DVSST and can reduce the total amount of energy consumption up to 46% while retaining the quality of service by meeting the deadlines.

51 citations


Journal ArticleDOI
TL;DR: A reverse engineering method that takes a bitstream as input and produces an NCD (Native Circuit Description) file for a Xilinx FPGA chip and the accuracy can be guaranteed if the scale of the chip is increased.

48 citations


Journal ArticleDOI
TL;DR: The design and implementation of a high performance FPGA hardware with a small footprint and low power consumption that computes OF at a speed exceeding real-time performance is presented and is made available in full for research and academic use.

42 citations


Journal ArticleDOI
TL;DR: The most efficient cipher for hardware implementation in terms of throughput-to-area ratio is Mickey V2 cipher while the worst cipher forHardware implementation is Grain V1.

39 citations


Journal ArticleDOI
TL;DR: Four new different hardware architectures are proposed to improve the performance of SHA-256 algorithms, reducing the critical path by reordering some operations required at each iteration of the algorithm and computing some values in advance, as possible as data dependence allows.

38 citations


Journal ArticleDOI
TL;DR: The methodology for the design and testing of fault tolerant systems implemented into an FPGA platform with different types of diagnostic techniques is presented and experimental results show the fault coverage and SEU occurrence causing faulty behavior of verified architectures.

36 citations


Journal ArticleDOI
TL;DR: This paper proposes a reference framework and design flow concept that combines system-level power optimization techniques with platform-based rapid prototyping, and proposes an efficient code annotation technique for timing and power properties enabling fast host execution as well as adaptive collection of power traces.

36 citations


Journal ArticleDOI
TL;DR: This paper provides a detailed study on the floorplans of optical NoCs in two popular two-dimensional topologies: mesh and torus, and proposes several approaches to optimize the power efficiency of Optical NoCs by minimizing the number of waveguide crossings in the floorplan.

35 citations


Journal ArticleDOI
TL;DR: A new method using polynomial residue number systems (PRNS) is introduced in this paper to protect the Advanced Encryption Standard (AES) against faults attacks and is the world's first PRNS AES implementation.

35 citations


Journal ArticleDOI
TL;DR: This work examines how a scalable and fully connected ONoC topology can be reduced to fit specific connectivity requirements in heterogeneous 3D architectures and successfully applies the proposed reduction method to multiple heterogeneous3D architectures.

Journal ArticleDOI
TL;DR: The obtained results show the effects of different hardware configurations on power and energy for a given application and that system level energy consumption analysis can help the design team to make informed architectural trade-offs during the design process.

Journal ArticleDOI
TL;DR: An overview of the research being currently performed in the scope of the European project ASAM of the ARTEMIS program is presented, which system, design, and electronic design automation (EDA) concepts seem to be adequate to address the challenges and solve the problems.

Journal ArticleDOI
TL;DR: The Modified Binary Particle Swarm Optimization (Modified BPSO) algorithm and Novel Binary Particles Swarm (Novel B PSO) Optimization are applied to solve the real-time task assignment in heterogeneous multiprocessor.

Journal ArticleDOI
TL;DR: The paper proposes a finite field arithmetic unit (FFAU) that reduces the number of clock cycles required to compute the elliptic curve point multiplication (ECPM) operation for ECC and presents an improved point addition (PADD) algorithm to take advantage of the novel FFAU architecture.

Journal ArticleDOI
Qi Guo1, Tianshi Chen1, Yunji Chen1, Ling Li1, Weiwu Hu1 
TL;DR: The key of this approach is utilizing inherent program characteristics as prior knowledge (in addition to microarchitectural configurations) to build a universal predictive model, so that no additional simulation is required for evaluating new programs on new configurations.

Journal ArticleDOI
TL;DR: A novel methodology for mapping multiple applications adaptively with unbounded or bounded number of cores with minimized communication energy consumption and execution time for multiple applications is presented.

Journal ArticleDOI
TL;DR: Efficient first-order collision attacks against all NTRU and three countermeasures are given, which cannot be avoided by any padding scheme.

Journal ArticleDOI
TL;DR: An autoregressive moving average (ARMA) model, used for nonlinearly degraded image deconvolution, is identified using a neural network (NN) and improved using a novel swarm optimization algorithm called Artificial Bees Colony (ABC), inspired from the foraging intelligence of honey bees.

Journal ArticleDOI
TL;DR: This paper summarizes the major results achieved in the MADNESS project regarding the system adaptivity and fault-tolerant processing and reports the results of the integration between platform level and middleware level support for Adaptivity and Fault-tolerance.

Journal ArticleDOI
TL;DR: An energy-efficient scheduling algorithm called AEE based on ant colony optimization for multi-FPGA reconfigurable systems with multiple FPGAs is proposed and can successfully complete tasks without violating deadline constraints and the energy dissipation is largely reduced.

Journal ArticleDOI
TL;DR: The use of techniques inspired by aspect-oriented technology and scripting languages for defining and exploring hardware compilation strategies are described and the results show the impact of various strategies when targeting custom hardware and expose the complexities in devising these strategies, hence highlighting the productivity benefits of this approach.

Journal ArticleDOI
TL;DR: A regular and scalable VLSI architecture for the implementation of parallel radix-4 rotational CORDIC algorithm and thorough comparison of the proposed architecture with the available architectures has been carried out to show the latency and the hardware improvement.

Journal ArticleDOI
TL;DR: The architecture and a detailed pre-fabrication analysis of a digital measurement ASIC facilitating long-term irradiation experiments of basic asynchronous circuits are presented, which demonstrates the suitability of the general approach for obtaining accurate radiation failure models developed in the FATAL project.

Journal ArticleDOI
TL;DR: The proposed rectification architecture is a ready-to-use hardware solution to be used in stereo vision real-time embedded systems after calibrating the employed stereo camera following the MATLAB Calibration Toolbox procedure.

Journal ArticleDOI
TL;DR: This article proposes a heuristic algorithm based on simulated annealing and its online execution that can significantly reduce the power consumption of DPM and DVS in the context of hard real-time systems on cluster-based multi-core processor platforms.

Journal ArticleDOI
TL;DR: This paper presents an energy efficient architecture to provide on-demand fault tolerance to multiple traffic classes, running simultaneously on single network on chip (NoC) platform, capable of providing required reliability, while significantly reducing the energy overhead.

Journal ArticleDOI
TL;DR: The proposed approach employs adaptive group testing techniques to autonomously maintain FPGA resource viability information as an organic means of transient and permanent fault resolution and demonstrates a readily-implemented yet robust organic hardware application that features a high degree of autonomous self-control.

Journal ArticleDOI
TL;DR: This new model relies on graph-theoretic concepts and incorporates static and dynamic power in order to present a more accurate evaluation of 3D NoC power consumption and is validated through two case studies to address symmetric and asymmetric multicore applications.

Journal ArticleDOI
TL;DR: An energy efficient error control code for the on chip interconnection link capable of correcting any type of error patterns including random and burst errors up to five and low residual flit error rate and low link power are proposed.