Showing papers in "MRS Proceedings in 2006"

Transparent, Conductive and Flexible Carbon Nanotube Films and Their Application in Organic Light Emitting Diodes

Abstract: We have successfully used a transfer printing technique to directly transfer vacuum-filtered nanotube film to glass and plastic substrates. Our typical SWNT-film has a transparency of ∼80% and a sheet resistance around 400 Ohm/square. Further improvement to the nanotube film includes SOCl 2 doping and PEDOT passivation, which significantly improve the sheet conductance and surface quality of the nanotube films. We have applied the optimized SWNT films as hole injection electrodes to demonstrate OLEDs on both rigid glass and flexible substrates.

Backplane Requirements for Active Matrix Organic Light Emitting Diode Displays

Abstract: Organic light emitting diode (OLED) displays are a serious competitor to liquid crystal displays in view of their superior picture quality, higher contrast, faster on/off response, thinner profile, and high power efficiency. For large area and/or high-resolution applications, an active matrix OLED (AMOLED) addressing scheme is vital. The active matrix backplane can be made with amorphous silicon (a-Si), polysilicon, or organic technology, all of which suffer from threshold voltage (VT) shift and/or mismatch problems, causing temporal or spatial variations in the OLED brightness. In addition, the efficiency of the OLED itself degrades over time. Despite these shortcomings, there has been considerable progress in development of AMOLED displays using circuit solutions engineered to provide stable and uniform brightness. Indeed the design of AMOLED pixel circuits, particularly in low-mobility TFT technologies such as a-Si, is challenging due to the stringent requirements of timing, current matching, and low voltage operation. While circuit solutions are necessary, they are not sufficient. Process improvements to enhance TFT performance are becoming inevitable. This paper will review pertinent material requirements of AMOLED backplanes along with design considerations that address pixel architecture, contact resistance, and more importantly, the VT-stability and associated gate overdrive voltage, VGS-VT. In particular, we address the question of whether conventional PECVD can be deployed for high mobility and high VT-stability TFTs, and if micro-/nano-crystalline silicon could provide the solution.

Ambipolar Thin-Film Transistors Fabricated by PECVD Nanocrystalline Silicon

Abstract: We report on directly deposited plasma-enhanced chemical vapor deposition (PECVD) nanocrystalline silicon (nc-Si:H) ambipolar thin-film transistors (TFTs) fabricated at 260 °C. The ambipolar operation is achieved adopting Cr metal contacts with high-quality nc-Si:H channel layer, which creates highly conductive Cr silicided drain/source contacts, reducing both electron and hole injection barriers. The n-channel nc-Si:H TFTs show a field-effect electron mobility (µeFE) of 150 cm2/Vs, threshold voltage (VT) ~ 2 V, subthreshold slope (S) ~0.3 V/dec, and ON/OFF current ratio of more than 107, while the p-channel nc-Si:H TFTs show a field-effect hole mobility (µhFE) of 26 cm2/Vs, VT ~ ‒3.8 V, S ~0.25 V/dec, and ON/OFF current ratio of more than 106. Complementary metal-oxide-semiconductor (CMOS) logic integrated with two ambipolar nc-Si:H TFTs shows reasonable transfer characteristics. The results presented here demonstrate that low-temperature nc-Si:H TFT technology is feasible for total integration of active-matrix TFT backplanes.

Thermo-Mechanical Reliability of 3D-integrated Microstructures in Stacked Silicon

Abstract: This paper investigates the thermo-mechanical reliability of inter-chip-vias (ICV) for 3D chip stacking after processing and under external thermal loads relevant for the envisaged field of application (mobile, automotive) by Finite Element simulation. First the materials are characterised by nano-indentation to determine elasto-plastic data. Finite Element simulations are used to reproduce these data and to extract local material properties like E-modulus and yield stress. Accumulated plastic strain is used as failure indicator under periodic thermal loading of an ICV. Geometrical, material and process-related parameters are varied to obtain first design guidelines for this new technology. The locations of stress and strain accumulation are given.

High-Performance Temporary Adhesives for Wafer Bonding Applications

Abstract: Myriad structures for stacking chips, power devices, smart cards, and thin substrates for processors have one thing in common: thin silicon. Wafer thinning will soon be an essential process step for most of the devices fabricated and packaged henceforth. The key driving forces for thinned wafers are improved heat dissipation, three-dimensional stacking, reduced electrical resistance, and substrate flexibility. Handling of thin and ultrathin substrates however is not trivial because of their fragility and tendency to warp and fold. The thinned substrates need to be supported during the backside grinding process and through the subsequent processes such as lithography, deposition, etc. Using temporary adhesives to attach the processed device wafer to a rigid carrier wafer offers an efficient solution. The key requirements for such materials are ease of application, coating uniformity with minimal thickness variation across the wafer, good adhesion to a wide variety of surfaces, thermal stability in processes such as dielectric deposition and metallization, and ease of removal to allow high throughput. An additional requirement for these materials is stability in harsh chemical environments posed by processes such as etching and electroplating. Currently available materials meet only a subset of these requirements. None of them meet the requirement of high-temperature stability combined with ease of removal. We have developed adhesives that meet a wide range of post-thinning operating temperatures. Additionally, the materials are soluble in industry-accepted safe solvents and can be spin-applied to required thicknesses and uniformity. Above all, the coatings can be removed easily without leaving any residue. This paper reports on the development of a wide range of temporary adhesives that can be used in wafer thinning applications while applying both novel and conventional bonding and debonding methods.

Prediction of Long Term Corrosion Behaviour in Nuclear Waste Systems

Abstract: The corrosion resistance of container materials in underground repositories is an important issue for the safe disposal of High Level Nuclear Waste (HLNW). The reliable prediction of container degradation rate and engineering barrier integrity over extended periods, up to several thousands years or even several hundreds of thousands of years, represents one of the greatest scientific and technical challenges. The first and the second International Workshops on Prediction of Long Term Corrosion Behaviour in Nuclear Waste Systems, which were held in 2001 (Cadarache) and 2004 (Nice), sought to compare the scientific and experimental approaches that are being developed in various organisations worldwide for predicting long term corrosion phenomena, including corrosion strategies for interim storage and geological disposal. The lessons learned during these Workshops, include the necessity of developing two approaches based on semi-empiricism and determinism in a complementary manner for effective prediction. The use of archaeological artefacts to demonstrate the feasibility of long term storage and to provide a database for testing and validating modelling work was also emphasized.

Design and Fabrication of 3D Microprocessors

Abstract: Stacking multiple device strata can improve system performance of a microprocessor (μP) by reducing interconnect length. This enables latency improvement, power reduction, and improved memory bandwidth. In this paper we review some of our recent design analysis and process results which quantitatively show the benefits of stacking applied to μPs. We report on two applications for stacking which take advantage of reduced wire length- “logic+logic” stacking and “logic+memory” stacking. In addition to optimizing minimum wire length, we considered carefully the thermal ramifications of the new designs. For the logic+memory application, we considered the case of reducing off-die wiring by stacking a DRAM cache (32 to 64MB) onto a high performance μP. Simulations showed 3x reduced off-die bandwidth, Cycles Per Memory Access (CPMA) reduction of 13%, and a 66% average bus power reduction. For logic+logic applications, we considered a high performance μP where the unit blocks were repartitioned into two strata. For this case, simulations showed that stacking can simultaneously reduce power by 15% while increasing performance by 15% with a minor 14° C increase in peak temperature compared to the planar design. Using voltage scaling, this translates to 34% power reduction and 8% performance improvement with no temperature increase. We found that these results can be further improved by a secondary splitting of the individual blocks. As an example, we split a 32KB first level data cache resulting in 25% power reduction, 10% latency reduction, and 20% area reduction. We also discuss the fabrication of stacked structures with two complimentary process flows. In one case, we developed a 300mm wafer stacking process using Cu-Cu bonding, wafer thinning, and through-silicon vias (TSVs). This technology provides reliable bonding with non-detectable bonding-interface resistance and inter-strata via pitch below 8μm. We investigated the impact of this wafer stacking process to the transistor and interconnect layers built using a 65nm strained-Si/Cu-Low-K process technology and found no impact to either discrete N- and P-MOS devices or to thin 4Mb SRAMs. We verified fully functional SRAMs on thinned wafers with thicknesses down to 5μm. Although wafer stacking leads itself well to tight-pitch same-die-size stacking, die stacking enables integration of different size dies and includes opportunity to improve yield by stacking known good dies. We demonstrated a die stack process flow with 75μm thinned die, TSV, and inter-strata via pitch below 100μm. We also found negligible impact to transistors using this process flow. Multiple stacks of up to seven 75μm thin dies with TSVs were fabricated and tested. Prospects for high volume integration of 3D into μPs are discussed.

Development of a high-growth rate 3C-SiC on Si CVD process

Abstract: Growth rates from 10 to 38 μm/h were achieved for heteroepitaxial 3C-SiC on Si (100) substrates by using the propane-silane-hydrogen gas chemistry with HCl as a growth additive. A low-pressure horizontal hot-wall CVD reactor was employed to perform the deposition. The growth rate dependences on silane mole fraction, the process pressure and the growth time were determined experimentally. The growth rate dependence on silane mole fraction was found to follow a linear relationship. The 3C-SiC films were characterized by Normaski Optical Microscopy, Scanning Electron Microscopy, Fourier Transform Infrared Spectroscopy, Atomic Force Microscopy and X-ray Diffraction. The X-ray rocking curve taken on the (002) diffraction plane displayed a FWHM of 360 arcsec which indicates that the films are monocrystalline.

Wrinkling of ultrathin polymer films

Abstract: This paper presents a bilayer model to account for surface effects on the wrinkling of ultrathin polymer films Assuming a surface layer of finite thickness, effects of surface properties on the critical strain, the equilibrium wavelength, and the wrinkle amplitude are discussed in comparison with conventional analysis Experimental measurements of wrinkling in polymer films with thickness ranging from 200 nm to 5 nm are conducted The bilayer model provides a consistent understanding of the experiments that deviate from conventional analysis for thickness less than 30 nm A set of empirical surface properties is deduced from the experimental data

NanoParticle Tracking Analysis; The Halo System

Abstract: A new technique for nanoparticle sizing that allows visualisation of nanoscale particles in liquids on an individual basis is described. The technology comprises a metallised optical element illuminated by laser beam at the surface of which nanoscale particles in suspension can be directly visualised, sized and counted in real time using only a conventional optical microscope fitted with a low cost camera and a dedicated analytical software package.

Dynamical Fracture Instabilities Due to Local Hyperelasticity at Crack Tips

Abstract: When materials break and cracks propagate, bonds between atoms are broken generating two new material surfaces. Most existing theories of fracture assume a linear elastic stress-strain law. However, the relation between stress and strain in real solids is strongly nonlinear due to large deformation near a moving crack tip, a phenomenon referred to as hyperelasticity or nonlinear elasticity. Cracks moving at low speeds create atomically flat mirror-like surfaces, whereas cracks at higher speeds leave misty and hackly fracture surfaces. This change in fracture surface morphology is a universal phenomenon found in a wide range of different brittle materials, but the underlying physical reason has been debated over an extensive period. Using massively parallel large-scale atomistic simulations employing a new, simple atomistic material model allowing a systematic transition from linear elastic to strongly nonlinear material behaviors, we show that hyperelasticity can play a governing role in dynamical crack tip instabilities in fracture of brittle materials. We report a generalized model that treats the instability problem as a competition between different mechanisms controlled by local stress field and local energy flow near the crack tip. Our results indicate that the fracture instabilities do not only appear in defected materials, but instead are an intrinsic phenomenon of dynamical fracture. Our findings help to explain controversial experimental and computational results, including experimental observation of crack propagation at speeds beyond the shear wave speed in rubber-like materials.

CMOS-Compatible Through Silicon Vias for 3D Process Integration

Abstract: As the limits of traditional CMOS scaling are approached, process integration has become increasingly difficult and resulting in a diminished rate of performance improvement over time. Consequently, the search for new two- and three- dimensional sub-system solutions has been pursued. One such solution is a silicon carrier-based System-on-Package (SOP) that enables high-density interconnection of heterogeneous die beyond current first level packaging densities. Silicon carrier packaging contains through silicon vias (TSV), fine pitch Cu wiring and high-density solder pads/joins, all of which are compatible with traditional semiconductor methods and tools. These same technology elements, especially the through silicon via process, also enable three dimensional stacking and integration. An approach to fabricating electrical through-vias in silicon is described, featuring annular-shaped vias instead of the more conventional cylindrical via. This difference enables large-area, uniform arrays to be produced with high yield as it is simpler to integrate into a conventional CMOS back-end-of-line (BEOL) process flow. Furthermore, the CTE-matched silicon core provides improved mechanical stability and the dimensions of the annular via allows for metallization by various means including copper electroplating or CVD tungsten deposition. An annular metal conductor process flow will be described. Through-via resistance measurements of 50, 90, and 150μm deep tungsten-filled annular vias will be compared. Two silicon carrier test vehicle designs, containing more than 2,200 and 9,600 electrical through-vias, respectively, were built to determine process yield and uniformity of via resistance. Through silicon via resistances range from 15-40 mΩ, and yields in excess of 99.99% have been demonstrated.

A Novel Optical Technique to Measure Pad-Wafer Contact Area in Chemical Mechanical Planarization

Abstract: Real contact area between a CMP pad and wafer is a key factor in local contact pressure, friction and pad wear, all of which impact material removal and defect formation. A new optical method is introduced that quantifies the real contact area during polishing. Confocal reflectance interference contrast microscopy (C-RICM) uses a single focal plane to image the pad-wafer contact interface. A sapphire cover slip is used to provide optical transparency and to match the refractive index of the pad. Imaging the pad surface through the cover slip reveals areas of no reflection (pad-cover slip contact), areas of reflection (non-contact), and interference fringes (near contact). The C-RICM method was validated using micro-fabricated pads having uniform arrays of cylindrical surface structures of known contact area. Experiments conducted on porous polyurethane pads revealed that the real contact area is less than 10% of the total presented area. However Greenwood-Williamson (G-W) theory, widely used in CMP material removal models, predicts a contact area at least a factor of ten smaller. The discrepancy was found to result at least in part because the individual contact zones are not elliptical as assumed in G-W theory. In fact many contacting structures are crescents located at the perimeter of individual pores. These findings underscore the need for accurate control of pore density and morphology in polishing pads, in both initial manufacture and surface conditioning during CMP. The C-RICM method allows non-destructive benchmarking of polishing media in terms of pad-wafer contact, essential for developing improved pad architectures that achieve lower CMP defect levels.

Development of the Supercontainer Design for Deep Geological Disposal of High-Level Heat Emitting Radioactive Waste in Belgium

Abstract: ONDRAF-NIRAS has recently selected a Supercontainer with a Portland Cement (PC) buffer as the preferred new reference design for disposal of HLW and spent fuel. The selection process involved a multi-criteria analysis of alternative design options, which were evaluated against a range of long-term safety and feasibility criteria. A PC concrete has been chosen for the buffer because this will provide a highly alkaline chemical environment, which will last for thousands of years. In this environment the external surface of the overpack will be passivated and overpack corrosion will be inhibited. The concrete buffer also has low-hydraulic conductivity to slow the infiltration of external fluids to the overpack surface, and provides radiological shielding. ONDRAF-NIRAS has made a preliminary evaluation of the viability of the reference Supercontainer design. The following areas were reviewed and investigated: radiolysis, thermo-hydraulic (TH) behaviour of the concrete buffer, metal corrosion, the chemical and mineralogical evolution of the concrete buffer, and relevant industrial experience. This paper describes the main findings, and identifies remaining design and performance uncertainties. Prioritisation and recommendations for future work are also given.

High Density Direct Bond Interconnect (DBI) Technology for Three Dimensional Integrated Circuit Applications

Abstract: A novel direct wafer bonding technology capable of forming a very high density of electrical interconnections across the bond interface integral to the bond process is described. Results presented include an 8 um interconnection pitch, die-to-wafer and wafer-to-wafer bonding formats, temperature cycling reliability × 10 greater than the JEDEC requirement, connection yield ∼ 99.999, > 50% part yield on parts with ∼ 450,000 connections, and < 0.1 Ohm connection resistance at 1pA without requiring a voltage surge to induce current.

Son68 Glass Dissolution Kinetics at High Reaction Progress: Mechanisms Accounting for The Residual Alteration Rate

Abstract: In a highly confined medium corresponding to geological repository conditions, the alteration rate of the French SON68 inactive nuclear reference glass drops by about four orders of magnitude below the initial rate. However, extended experiments lasting months or years provide evidence of a virtually constant or slowly decreasing residual alteration rate. Although very low, this rate could account for most of the altered glass thickness after 10 000 years. Experiments at high temperatures and especially high glass-surface-area-to-solution-volume ratios were performed to reveal and quantify the predominant mechanisms underlying the residual rate. The authors describe the characterization of the solution chemistry, the crystallized secondary phases, and the amorphous gel observed after alteration of the French SON68 inactive reference glass, and discuss their implications in terms of long-term behavior modeling. A slow diffusion mechanism is identified in the solid, involving alkalis in particular but also boron. This mechanism results in higher concentrations in solution that affect the system chemistry, not only by slightly modifying the pH and element speciation in solution (e.g. silicon), but also by inducing the precipitation of new crystallized secondary phases that can consume glass constituent elements in the same way as simple solution renewal. Diffusion and the precipitation of secondary phases are two mechanisms to be considered to account for the residual rate.

Millisecond Annealing: Past, Present and Future

Abstract: The challenge of achieving maximal dopant activation with minimal diffusion has re-awakened interest in millisecond-duration annealing processes, almost two decades after the initial research in this field. Millisecond annealing with pulsed flash-lamps or scanned energy beams can create very shallow and abrupt junctions with high concentrations of electrically active carriers, but solutions for volume manufacturing must also meet formidable process control requirements and economic metrics. The repeatability and uniformity of the temperature cycle is the key for viable manufacturing technology, and the lessons from the development of commercial rapid thermal processing (RTP) tools are especially relevant. Advances in the process capability require a fuller understanding of the trade-off between dopant activation, defect annealing. diffusion and deactivation phenomena. There is a strong need for a significant expansion of materials science research into the fundamental physical processes that occur at the short time scales and high temperatures provided by millisecond annealing.

Amorphization/templated recrystallization method for hybrid orientation substrates

Abstract: The present invention provides an improved amorphization/templated recrystallization (ATR) method for fabricating low-defect-density hybrid orientation substrates. ATR methods for hybrid orientation substrate fabrication generally start with a Si layer having a first orientation bonded to a second Si layer or substrate having a second orientation. Selected regions of the first Si layer are amorphized and then recrystallized into the orientation of the second Si layer by using the second Si layer as a template. The process flow of the present invention solves two major difficulties not disclosed by prior art ATR methods: the creation of “corner defects” at the edges of amorphized Si regions bounded by trenches, and undesired orientation changes during a high temperature post-recrystallization defect-removal annealing of non-ATR'd regions not bounded by trenches. In particular, this invention provides a process flow comprising the steps of (i) amorphization and low-temperature recrystallization performed in substrate regions free of trenches, (ii) formation of trench isolation regions that subsume the defective regions at the edge of the ATR'd regions, and (iii) a high-temperature defect-removal anneal performed with the trench isolation regions in place.

Silver Zeolites: Iodide Occlusion and conversion to Sodalite – a potential 129I waste form?

Abstract: Silver exchanged zeolites A, X and Y were used to occlude silver iodide (AgI) at 400°C. Heating to 900°C in a hot isostatic press caused decomposition of the zeolite materials and the formation of more dense phases. Silver zeolites A and X both formed sodalite, seen as a potential 129I waste form, while silver zeolite Y formed an x-ray amorphous phase containing AgI. Silver zeolite A produced the best potential waste form, a monolithic sodalite with negligible porosity.

Accurate Sheet Resistance Measurement on Ultra-Shallow Profiles

Abstract: Comparison of state-of-the-art zero-penetration sheet resistance tools on ultra-shallow Boron CVD layers on top of a medium doped As layer.

Piezoresistive Sensors on Textiles by Inkjet Printing and Electroless Plating

Abstract: We have printed arrays of strain sensors on textiles by inkjet printing of conducting lines and piezoresistive polymer (PEDOT) in order to provide detailed information about the response of a fabric in use. Conducting polymer has been printed onto polyamide and cellulose woven fabrics to form sensors using a modified HP inkjet print-head and X-Y linear positioning table. Good penetration and attachment is found on mercerized cotton but not on polyamide. Silver nitrate lines have been printed onto polyamide and converted to silver connectors by electroless plating. We observed that resistance of silver lines ranged from 0.7-1.5Ω/cm whereas for the conducting polymer it was 1-3 kΩ/mm by a four point probe method. The conducting polymer formed a surface coat on the fabric and also penetrated the weave. On stretching, the surface layer tended to crack but the embedded polymer acts as a strain gauge with a gauge factor of about 5. On the other hand the silver showed minimal change in resistance with stretching, as is required for connectors. Sensitivity towards temperature and humidity and the effect of orientation to stress and weave directions will be reported. Preliminary experiments show that these sensors attached to a sleeve could be effective for monitoring human joint motion.

Development of 3D-Packaging Process Technology for Stacked Memory Chips

Abstract: A 3D packaging technology for 4 Gbit DRAM has been developed. It is targeting to realize 4Gb density DRAM by stacking 8-DRAM chips into one package. Interconnect between stacked chips will be done by through-silicon-via for the requirement of 3Gbps operation. Key process technologies for chip stacking are through-silicon-via formation, wafer back side process and micro-bump bonding. These chip-stacking processes have been developing using TEG, which can evaluate electrical characteristics.

Leaching Behaviour of Zirconolite in 0.001M Citric Acid at 90°C Under Various Flow Regimes

Abstract: Nd-bearing zirconolite was leached at 90°C for 157 days in 0.001M citric acid under single-pass-flow-through conditions (modified MCC-4 protocol). Three different flow rates were used, ranging in an order of magnitude from 10 mL per day to 100 mL per day, to determine the effect of the rate of leachant replenishment on the durability of the zirconolite. Results of previous studies on the role of complexing agents on the leaching behaviour of single-phase zirconolite have been included in the discussion. The pH of the citric acid solution was adjusted to 5 using KOH, mimicking that of the water in the parallel tests, to avoid the influence of pH on chemical durability of the zirconolite. Simulated groundwater containing 0.001M citric acid at 90°C led to congruency in elemental releases and a diminution of release rate with time of about an order of magnitude, reaching virtual constancy after about 50 to 60 days to a level of about 10 −5 g m −2 day −1 . The most significant finding was that the elemental release rates of Nd, Ti and Zr (and Ca and Al where detected) were similar for all flow rates. Clearly, varying flow rate by up to an order of magnitude had no effect on elemental releases i.e. there is no solubility limit control on releases at 0.001M citric acid concentration. An important finding of previous studies using identical leaching protocols with 0.001M citric acid, and inferred in our latest investigations reported here, was that there is no secondary layer development at the surface of the zirconolite to affect leach rates. In contrast, parallel tests carried out in deionised water instead of citric acid showed that hydroxides form in situ on the zirconolite surface, effectively forming hydrolysed zirconolite. This controls further dissolution of the zirconolite matrix due to the solubility limit being reached with respect to the hydrolysed phases rather than with zirconolite. Complexation by citrate ions prevents such control by hydrolysed species on zirconolite solubility. Even under the more aggressive conditions imposed in these studies (0.001M citric acid), and regardless of flow rate of the leachant, elemental releases from zirconolite are very low for a candidate wasteform and demonstrate its attributes as a ceramic-based wasteform for the containment of actinides.

Recent Advances in 3D Integration at IMEC

Abstract: IMEC is focusing its 3D-integration technology developments in 3 distinct directions: 3D-System-in-a-Package (3D-SiP), 3D-Wafer-Level-Packaging (3D-WLP) and 3D-Stacked-IC (3D-SiC). First, the background of these separate approaches will be given. Next the materials and technologies involved, the typical characteristics and the ongoing developments will be discussed. Finally, the roadmap for the 3D-integration in IMEC will be presented.

Suspension of Silver Oxide Nanoparticles in Chitosan Solution and its Antibacterial Activity in Cotton Fabrics

Abstract: New stable silver oxide suspension in chitosan solution was prepared from a mixture of silver nitrate and chitosan in dilute acetic acid as precursor, in which the complex interactions between silver ion and chitosan was also investigated through various instrumentation method seriously. The suspension was charactized through laser scan, infrared ray spectroscopy (IR), ultraviolet-visible spectroscopy (UV-vis) and X-ray diffraction (XRD), which indicated that the interactions between silver and chitosan in its precursor were destroyed partially. The measurements of the nanoparticles through scanning electron microscopy (SEM) and transmission electron microscopy (TEM) disclosed the spherical profiles of these silver oxide nanoparticles of 10-20nm in average. Cotton fabrics treated by this emulsion were entitled remarkable antibacterial activity against S aureus and E. coli at pH 5 and 7 with sightless color effect and good washing fastness.

Control of Trenching and Surface Roughness in Deep Reactive Ion Etched 4H and 6H SiC

Abstract: An optimized deep reactive ion etching (DRIE) process for the fabrication of SiC microstructures has been developed. The optimized process enables the etching of 4H and 6H SiC to depths > 100 microns with the required characteristics of (1) high rate (>0.5 microns/min), (2) vertical sidewalls, (3) minimal microtrenching at the sidewall base, and (4) smooth etched surfaces. The optimized process was determined based on the results of an experiment (full factorial design) which determined how the etch characteristics are affected by four important process parameters: temperature of the wafer chuck, pressure within the chamber, and concentrations of O2 and Ar in a gas flow comprised of O2, Ar and SF6. This study is believed to be the first systematic investigation of the effect of temperature on SiC DRIE characteristics; substrate heating was found to be a key in producing the desired etch properties.

Advances in SiGeSn/Ge Technology

Abstract: We recently reported the CVD growth of binary Ge1−ySny and ternary Ge1−ySixSny alloys directly on Si wafers using SnD4, Ge2H6 (di-germane), SiH3GeH3, and (GeH3)2SiH2 sources. Ge1−ySny is an intriguing infrared material that undergoes an indirect-to-direct bandgap transition for y ≥ 0.09. In addition, we have found that Ge1−ySny layers have ideal properties as templates for the subsequent deposition of other semiconductors: (a) they are strain-relaxed and have low threading-defect densities (105 cm−2) even for films thinner than 1 μm; (b) their low growth temperatures between 250°C and 350°C are compatible with selective growth, and the films possess the necessary thermal stability for conventional semiconductor processing (up to 750°C depending on composition); (c) they exhibit tunable lattice constants between 5.65 A and at least 5.8 A, matching InGaAs and related III-V systems; (d) their surfaces are extremely flat; (e) they grow selectively on Si and not on SiO2; and (f) the film surface can be prepared by simple chemical cleaning for subsequent ex-situ epitaxy. The incorporation of Sn lowers the absorption edges of Ge. Therefore, Ge1−ySny is attractive for detector and photovoltaic applications that require band gaps lower than that of Ge. Spectroscopic ellipsometry and photoreflectance experiments show that the direct band gap is halved for as little as y = 0.15. Studies of a Ge0.98Sn0.02 sample yield an absorption coefficient of 3500 cm−1 at 1675 nm (0.74 eV). Thus infrared detectors based on Ge0.98Sn0.02 could easily cover the U-(1565 nm-1625 nm), L-(1565 nm-1625 nm), and C-(1530 nm-1565 nm) telecomm bands. Photoluminescence studies show bandgap emission on thin GeSn layers sandwiched between higher bandgap SiGeSn barriers. We have made advances in p and n doping of GeSn and present results on electrical characterizations. GeSn also has application in band-to-band laser heterodiodes. The ternary system Ge1−x−ySixSny grows on Ge1−ySny-buffered Si. It represents the first practical group-IV ternary alloy, since C can only be incorporated in minute amounts to the Ge-Si network. The most significant feature of Ge1−x−ySixSny is the possibility of independent adjustment of lattice constant and band gap. For the same value of the lattice constant one can obtain band gaps differing by more than 0.2 eV, even if the Sn-concentration is limited to the range y < 0.2. This property can be used to develop a variety of novel devices, from multicolor detectors to multiple junction photovoltaic cells. A linear interpolation of band gaps lattice constants between Si, Ge and α-Sn shows that it is possible to obtain SiGeSn with a band gap and a lattice constant larger than that of Ge. We shall use this feature to make a tensile-strained Ge-on-SiGeSn telecomm detector with improved performance. The tensile-strain-induced direct gap of Ge can be used also for laser diodes and electroptical modulators.

Polymer-Based Microelectrode Arrays

Abstract: We have developed flexible, polymer-based electrodes for potential medical applications including neural recording and stimulation. Using various combinations of liquid crystal polymer (LCP) substrates, implantable grade silicone and polyimide, we have developed and tested several prototype multi-layer polymer electrodes. We report here on two specific electrodes. In the first case, a multilayer electrode consisting of high-melt temperature liquid crystal polymer (LCP) material with patterned electrodes of sputter deposited and plated gold, laminated together with a lower-melt temperature LCP was produced. Iridium oxide was deposited on the exposed electrode sites to facilitate effective charge transfer for neural stimulation. The electrode was designed for acute implantation in a cat cochlea and contained 12 contacts, with a pitch of 200 microns. The small contact spacing allowed testing of electric field focusing techniques both in vitro and in vivo. We subjected the electrodes to electrical and mechanical tests to assess potential suitability as a long-term biomedical implant. Chronic electrical leakage testing indicated higher than desired ionic permeability of the low and high temperature LCP interface. In a second case we produced a mock circuit using high-melt LCP and medical grade low durometer silicone in place of the low-melt LCP as the interlayer adhesive. Mechanical and electrical testing of the hybrid design indicated the potential to fabricate cochlear electrodes containing up to 72 contacts with a footprint and mechanical performance similar or better than current commercially available cochlear implant arrays (containing up to 24 elements). Multi-layer polymer electrode technology offers the opportunity to create new electrodes with higher numbers of channels, offering improved performance in neural stimulation applications including cochlear implants, retinal arrays, deep brain stimulators and paraplegic remobilization devices.

Novel approaches of light management in thin-film silicon solar cells

Abstract: In order to improve light trapping in thin-film silicon solar cells two novel approaches are investigated in this article: angle-selective management of light scattering inside the solar cell and wavelength-selective manipulation of high reflectance or transmittance of light. Diffraction gratings are analyzed as a representative of the first approach. Haze and angular distribution function of scattered (diffracted) light in reflection are measured for aluminum-based rectangular periodic gratings with different period and height of the rectangles. High haze values in specific wavelength region and scattering angles of the investigated gratings measured in air and water agree very well with the theoretical predictions. Considering the actual optical situation in microcrystalline silicon solar cells, optimal period and height of the rectangular gratings applied as a back reflector are calculated for obtaining the total reflection at the front interfaces. In the frame of the second approach, photonic-crystal-like structures are introduced. By means of optical simulations photonic-crystal-like structures are investigated for two possible applications: an intermediate reflector in a micromorph silicon solar cell with wavelength-selective reflectivity and a dielectric back reflector with a high reflectance in the long-wavelength region. The photonic crystal structure consisting of sequences of n-doped amorphous silicon and ZnO layers is designed for the efficient intermediate reflector. For the back reflector with a high reflectance the structures with intrinsic amorphous silicon, SiO2, MgF2 and TiO2 are proposed.

Culture of Mammalian Cells on Single Crystal SiC Substrates

Abstract: Crystalline silicon carbide (SiC) has the potential to become an important biomaterial and a versatile interface between the electronic and biological world. In this work, single crystal SiC biocompatibility is investigated by culturing mammalian cells directly on SiC substrates. The cell morphology and the quality of the cell adhesion have been studied using fluorescence microscopy, while MTT [3-(4,5-dimethylthiazol-2-yl)-2,5-diphenyltetrazolium bromide] assays have been performed to quantify cell viability and number. Standard culture-wells and silicon (Si) substrates were used as controls in the final assessment of crystalline SiC biocompatibility.