Showing papers in "Proceedings of SPIE in 2007"

Pitch doubling through dual-patterning lithography challenges in integration and litho budgets

Abstract: We present results from investigating critical challenges of pitch doubling through Double Patterning to meet manufacturing requirements for 32nm 1/2 pitch on 12NA lithography system Simulations of lithography alternatives identified manufacturable Dose-Focus latitudes for a dual-line positive process option which led to an experimental setup based on a single hardmask process Key challenges of the selected process relate to the presence or absence of the hardmask layer during 1st or 2nd patterning step This has an effect on wafer topography, process setup, etch bias and wafer litho-to-etch CDU offsets, which will create two final CDU populations Therefore, there are two metrology challenges, separation between the two CD populations and overlay-at-resolution using CDSEM They were addressed by designing appropriate CD and overlay targets and by implementing an adequate dense sampling allowing modeling of wafer and field CD distributions We introduced a new CDU model to calculate double patterning budgets based on defining CD from its edges and pooling CD variance from two adjacent patterns within 2*Pitch distance For a single line and 135NA system, the model predicted 31nm variance with mask CDU and etch bias being the major contributors We achieved an experimental resolution of 32-nm 1/2 pitch on 12NA system, which equals 020k1 Experimental results at 32-nm resolution were confirmed in a pre-manufacturing environment on a full lot of 24 wafers, with raw CDU of 6nm (3s) After modeling and correcting for interfield (wafer) and intrafield spatial distributions, CDU was improved to 25nm (3s) Best overlay results equaled scanner SMO capability of ~7nm (mean+3s)

Fixed mobile convergence (FMC) architectures for broadband access: integration of EPON and WiMax

Abstract: EPON and WiMAX are two promising broadband access technologies for new-generation wired and wireless access. Their complementary features motivate interest in using EPON as a backhaul to connect multiple dispersed WiMAX base stations. In this article we propose four broadband access architectures to integrate EPON and WiMAX technologies. The integrated architectures can take advantage of the bandwidth benefit of fiber communications, and the mobile and non-line-of-sight features of wireless communications. Based on these integrated architectures, we elaborate on related control and operation issues to address the benefits gained by this integration. Integration of EPON and WiMAX enables fixed mobile convergence, and is expected to significantly reduce overall design and operational costs for new-generation broadband access networks.

A litho-only approach to double patterning

Abstract: Double patterning has become one of the candidates to bring us to the next node of the ITRS-roadmap. As an alternative to immersion lithography with higher index fluids and EUV lithography which both require considerable changes in infrastructure, double patterning makes use of the existing infrastructure. Because of this, double patterning has gained considerable attention during the past few years. It has become a serious candidate to reach the 45 nm node and even the 32 nm node. Most of the currently known double patterning techniques have relatively complex process flows, which may prevent them from being used in production. One of the complicating factors is the use of an etch step in between the two lithography steps. This etch step is necessary to transfer the pattern of the first resist layer into an underlying hard mask before a second exposure can be done. Another complicating element, arising in several known double patterning techniques, is the translation of overlay error in CD-error. This translation occurs when a feature is printed in two exposures, i.e. not features but the spaces between them are patterned, patterning the left and right edge of a feature in different exposures. In this paper, we examine and evaluate a novel double patterning method that does not include transfer etch in between the lithography steps. This method would simplify the double patterning process. Furthermore, each feature is patterned completely in one exposure, for which CD-value is not affected by overlay error. This paper discusses the feasibility of the new double patterning method and compares it to conventional double patterning schemes. Furthermore, an assessment will be made whether the proposed technique has the potential to be used in production.

Supercontinuum generation in optical fibers

Abstract: In this paper, we studied SC generation in fiber lasers and in optical fibers pumped by different light sources which include fs and ps pulse sources, and continuous-wave (CW) amplified spontaneous emission (ASE) light sources. First, we demonstrated SC generation with a 10dB spectral bandwidth of 430nm in a fiber ring laser with conventional nonlinear fiber. Second, we proposed and demonstrated a new and efficient approach to generation of a CW SC in optical fibers pumped by a CW ASE light. A bandwidth of 268nm (at -15dB level) with an average spectral density of 2.7mW/nm was demonstrated. Various approaches to flattening the spectrum and increasing the spectral width were also studied. The application of this SC source in WDM passive optical access networks (WDM-PONs) was investigated. Third, the approach of SC generation in a fiber combination of standard SMF and nonlinear DSF pumped by an all-fiber fs pulse Master Oscillator Power Amplifier (MOPA) system was developed. A spectral bandwidth of over 1000nm was demonstrated. Finally, the generation of broad comb-like-spectral light based on the pulse compression of 40GHz optical pulses in a new nonlinear dispersion-decreasing fiber with high SBS threshold was studied. A continuum light source with over 125 channels and a channel spacing of 40 GHz was achieved. The use of this continuum light source as WDM source in WDM-PONs was investigated.

Issues and challenges of double patterning lithography in DRAM

Abstract: Double patterning lithography has been one of the candidates for sub-40nm patterning era, and has a lot of process issues to be confirmed. Last year, we presented the issues in double patterning lithography with a real flash gate pattern. Process flow was suggested and CD uniformity due to overlay was analyzed. And the layout decomposition and the two types of double patterning of positive and negative tone were studied with 1-dimensional pattern. In this paper, the implementation to DRAM patterns is examined, which consist of 2-dimensional patterns. Double patterning methods and the selection of their tone for each layer are studied, and the difficulties from the randomness of core pattern are also considered. As a result, DRAM patterns have more restrictions on the double patterning method and selection of tone, and the aggressive layout decomposition should be designed to solve the difficulty in core patterning. Therefore, 37nm DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles.

Manufacturability issues with double patterning for 50-nm half-pitch single damascene applications using RELACS shrink and corresponding OPC

Abstract: A double patterning (DP) process is discussed for 50nm half pitch interconnects, using a litho-etch-litho-etch approach on metal hard mask (MHM). Since an 0.85NA immersion scanner is used, the small pitch of 100nm is obtained by DP, the small trenches are made by a Quasar exposure followed by a shrink technique. The RELACS ® process is used, realizing narrow trenches with larger DOF and less LER. Fo r mask making, a design split is carried out, followed by adjustments of the basic design to make the patterns more litho-friendly. Assist features are placed next to isolated trenches to ensure sufficient DOF. Furthermore, an adjusted OPC calculation is carried out, taking into account proximity effects of both the exposure and the subsequent shrink process. After mask fabrication, this DP process is used for a single damascene application, with BDIIx as low-k material and TaN or TiN as MHM. Various problems are encountered, such as CD gain of the trenches during both MHM etch steps, poisoning and BARC thickness variations due to topography during the second litho step. For all these problems, solutions or work-arounds have been found, After the second MHM-etch, the 50nm half-pitch pattern is tr ansferred successfully in th e underlying low-k material. Keywords: double patterning, 50nm half pitch, RELACS

ILT for double exposure lithography with conventional and novel materials

Abstract: Multiple paths exists to provide lithography solutions pursuant to Moore's Law for next 3-5 generations of technology, yet each of those paths inevitably leads to solutions eventually requiring patterning at k1 < 0.30 and below. In this article, we explore double exposure single development lithography for k1 ≥ 0.25 (using conventional resist) and k1 < 0.25 (using new out-of-sight out-of-mind materials). For the case of k1 ≥ 0.25, we propose a novel double exposure inverse lithography technique (ILT) to split the pattern. Our algorithm is based on our earlier proposed single exposure ILT framework, and works by decomposing the aerial image (instead of the target pattern) into two parts. It also resolves the phase conflicts automatically as part of the decomposition, and the combined aerial image obtained using the estimated masks has a superior contrast. For the case of k1 < 0.25, we focus on analyzing the use of various dual patterning techniques enabled by the use of hypothetic materials with properties that allow for the violation of the linear superposition of intensities from the two exposures. We investigate the possible use of two materials: contrast enhancement layer (CEL) and two-photon absorption resists. We propose a mathematical model for CEL, define its characteristic properties, and derive fundamental bounds on the improvement in image log-slope. Simulation results demonstrate that double exposure single development lithography using CEL enables printing 80nm gratings using dry lithography. We also combine ILT, CEL, and DEL to synthesize 2-D patterns with k1 = 0.185. Finally, we discuss the viability of two-photon absorption resists for double exposure lithography.

Broadband wavefront correction algorithm for high-contrast imaging systems

Abstract: Great strides have been made in recent years toward the goal of high-contrast imaging with a sensitivity adequate to detect earth-like planets around nearby stars. It appears that the hardware − optics, coronagraph masks, deformable mirrors, illumination systems, thermal control systems − are up to the task of obtaining the required 10-10 contrast. But in broadband light (e.g., 10% bandpass) the wavefront control algorithms have been a limiting factor. In this paper we describe a general correction methodology that works in broadband light with one or multiple deformable mirrors by conjugating the electric field in a predefined region in the image where terrestrial planets would be found. We describe the linearized approach and demonstrate its effectiveness through laboratory experiments. This paper presents results from the Jet Propulsion Laboratory High Contrast Imaging Testbed (HCIT) for both narrow-band light (2%) and broadband light (10%) correction.

Double Exposure Using 193nm Negative Tone Photoresist

Abstract: Double exposure is one of the promising methods for extending lithographic patterning into the low k 1 regime. In this paper, we demonstrate double patterning of k 1-effective =0.25 with improved process window using a negative resist. Negative resist (TOK N- series) in combination with a bright field mask is proven to provide a large process window in generatin g 1:3 = trench:line resist features. By incorporating two etch transfer steps into the hard mask material, frequency doubled patterns could be obtained. Keywords : Double exposure, double patterning, 193 nm, negative tone 1. INTRODUCTION Resolution is expressed by P/2 = k 1 O /NA, where P/2 is the minimum half pitch, k 1 is a process factor, O is the wavelength of the exposure light, and NA is the numerical aperture of the projection optics. In order to extend the resolution limit, many resolution enhancement techniques have been developed. Among those many potential techniques, double exposure methods are being considered to be promising in 193 nm lithography (Fig. 1). Recently, several double exposure techniques have been reported such as UV resist-modification [1], double dipole [2], spacer technique [3], and double patterning [4]. Among those, double patterning schemes (Fig.2) are known to be feasible because all of the processes involved utilize common integration schemes, and thus there is no need to develop a special technique including the resist aspect. A common characteristic of this technique is that it often involves an etch step between two separate lithographic processes. The 2

Dark field double dipole lithography (DDL) for back-end-of-line processes

Abstract: The back-end-of-line metallization of a state-of-the-art CMOS process is the most critical level regarding the final density of the chip. While the gate level requires the most emphasis on linewidth control and critical dimension uniformity (CDU) of all lithography steps, the smallest pitch in the process is typically printed on the first metallization level. For this reason, a natural starting point for application of dipole lithography is not the gate level, which in many cases can be printed with quadrupole and other off-axis schemes with good process latitude, but the metal level with pitches that are typically between 10 and 25% smaller than the gate pitch. If the same generation exposure tool is used for both gate and metallization levels, then a more aggressive off-axis illumination is needed for the metal level. In this paper, we investigate the application of double dipole lithography on the first metallization level (M1). We propose a simple bias to account for EMF effects compared to the thin mask approximation which is used in optical proximity correction. We discuss resist and BARC processes that are required at this pitch, and describe process windows. Using a 1.2 NA lithography system, we investigate the performance of this lithography technique at a pitch of 100 nm.

Double patterning with multilayer hard mask shrinkage for sub-0.25 k1 lithography

Abstract: In order to reduce the overall size of device features, continuing development in the low k1 lithography process is essential for achieving the feature reduction. Although ArF immersion lithography has extended the feature size scaling to 45nm node, investigation of low k1 lithography process is still important for either ArF dry or wet lithography. Double patterning is one procedure pushing down the k1 limit below 0.25. It combines the multilayer hard mask application and resist shrinkage process to get the feature size reduced to quarter pitch of the illumination limit. In recent spin-on hard mask studies, silicon containing bottom antireflective coatings (BARC) have been developed to combine the function of reflective control and great etching selectivity to the photoresist. Trilayer resist including the photoresist, silicon containing BARC and planarizing organic underlay can improve the reflectivity by optical index tuning of dual hard mask layer effectively and reduce photoresist thickness to avoid the pattern collapse with small features. In our study, we found some interesting characteristics of trilayer resist could be used for double patterning technology and made the low k1 process more feasible. This procedure we investigated can make the feature size of half pitch reduce to 37nm and beyond at 0.92NA under ArF dry lithography. Among the resolution enhancement for ArF dry illumination, double patterning scheme, overlay controllability and pattern transfer process by reactive ion etching (RIE) will be discussed in this paper.

A study of double exposure process design with balanced performance parameters for line/space applications

Abstract: As the semiconductor fabrication groundrule has reached the 32nm node, in general there are several possible approaches for the photolithography solution such as the double exposure with 1.35 NA immersion, the high refractive index immersion, the extremely ultra violet (EUV) lithography, nanoimprint lithography etc. Among the four, the easiest approach seems to be the double exposure method at an effective numerical aperture (NA) of 1.35. However, there are still challenges in the design and optimization of the process, such as, the use of appropriate illumination condition, the choice of a good photoresist, and the design of an optical proximity correction (OPC) strategy. Besides these considerations, there is a question as whether we really need the double etch process. To study the double exposure mechanism, we have used a 248 nm deep-UV exposure tool and several well chosen photoresist (one is for Space application and the other is for Line application) to study the photo performance parameters in the merge of two photo exposures. At a numerical aperture (NA) around 0.7, the minimum groundrule we can achieve is the one for a 75 nm logic process with minimum pitch around 220 nm. One approach will be that the features with pitches wider than 440 nm are completed in a single exposure, which includes various isolated lines and spaces, line and space ends, two-dimensional structures, etc. This strategy essentially puts the single exposure pattern under the 0.18 um logic like pitches where mild conventional illumination can produce a balanced performance. Under typical illumination conditions, the photolithographic process under 0.18 um like ground rule is well understood and the optical proximity correction is not complicated. The remaining issues are in the dense pitches, where the double exposure kicks in. We have demonstrated that the double exposure with single development can achieve a process window large enough for a 75 nm logic like process and the OPC behavior such as line through pitch is manageable although OPC correction strategy may require substantial improvement to accommodate two individual exposures. In this paper, we will demonstrate the result of our study of the basic photolithographic performance indicators, such as the exposure latitude (EL), the depth of focus (DOF), the CD through pitch, the line edge roughness (LER) and the mask error factor (MEF) for the optimized process. And we will discuss the choice of photoresists for this special application. It seems that a photoresist with a balanced performance for both the line and space is necessary to realize a good double exposure process. In this paper, we will also present our simulation result of effective resist diffusion length to explore the limit of such approach.

Compressive phase retrieval

Abstract: The theory of compressive sensing enables accurate and robust signal reconstruction from a number of measurements dictated by the signal's structure rather than its Fourier bandwidth. A key element of the theory is the role played by randomization. In particular, signals that are compressible in the time or space domain can be recovered from just a few randomly chosen Fourier coefficients. However, in some scenarios we can only observe the magnitude of the Fourier coefficients and not their phase. In this paper, we study the magnitude-only compressive sensing problem and in parallel with the existing theory derive sufficient conditions for accurate recovery. We also propose a new iterative recovery algorithm and study its performance. In the process, we develop a new algorithm for the phase retrieval problem that exploits a signal's compressibility rather than its support to recover it from Fourier transform magnitude measurements.

The Modeling of Double Patterning Lithographic Processes

Abstract: Double patterning (DP) appears to be the most probable patterning technology for initial 32 nm node manufacturing. This work explores how it may be accurately simulated. In the first instance, the process is approximated using two planar exposures in a commercial lithographic simulation package. This work is then followed up by more accurate calculations using a prototype simulator (based of Rigorous Coupled Wave Analysis propagation techniques) which allows the topography generated from the first exposure pass to influence the light propagation in the second exposure. The accuracy of the prototype simulator is demonstrated by validating its' output against the vector model in PROLITH V10, for the planar topography case. Results from the RCWA simulations show that for an example poly gate double patterning process, the presence of the topography enhances the process window of the second exposure, in terms of both exposure and focus latitude. The topography simulator is also used to study the robustness of the second exposure process window to fluctuations in the CD printed during the first exposure pass and of the influence of misalignment between the two passes.

New double exposure technique without alternating phase-shift mask

Abstract: The double exposure technique using alternating phase shift mask (alt-PSM) has been proposed and it is well used for the gate layer of the high performance logic devices as strong resolution enhancement technology (RET). This technique has advantage that the fine resist profile is obtained on wafer with extensive process margin. However, this double exposure technique is very expensive because of the alt-PSM cost. This time, the new double exposure technique without alt-PSM is developed for gate layer of 45 nm node logic devices. In this new double exposure method, attenuated phase shift mask (att-PSM) or binary mask (BIM) is used with dipole illumination. It is thought that this new double exposure method is effective for random logic devices which have various pattern pitches by the optimization of dipole illumination condition and pattern placement. Firstly, the optical contrast and depth of focus (DOF) is calculated. From these results, dipole illumination condition is optimized. It is found that DOF of new double exposure method is wider than that of conventional method. In addition, mask pattern is optimized to obtain wide process margin. For dense pattern, mask biasing is effective and optimization of shifter width is effective for isolated pattern. Furthermore, it is found that assist pattern is very effective for isolated pattern. From experimental results, it is proved that new double exposure method have wider process margin than that of conventional one. The strong design for manufacturing (DFM) rule that required the severe line width control is placed at single direction is proposed to realize the new double exposure method. Finally, it is found that the lithographic performance of new double exposure method has same level as conventional method with alt-PSM for gate layer of 45 nm logic devices.

Feasibility study of splitting pitch technology on 45nm contact patterning with 0.93 NA

Abstract: As semiconductor process technology moves to smaller generations (65nm and beyond), the contact pattern printing becomes the most difficult challenge in the lithography field. The reason comes from the smaller feature size and pitch of contact/via pattern printing that is similar to 2D (two-dimensional) patterning. Contact and via patterns need better image contrast than line/space patterns in pattern printing. Hence, contact/via printing needs a higher k1 value than others. In 65nm generation experience, the k1 is ~0.44 on a 0.85 NA exposure tool. A larger NA exposure tool is expensive and developed slower than the motivation of generation. Hence, the process is difficult to achieve by obtaining larger NA exposure tools. The k1 requirement of 45nm (logic) contact pattering (minimum pitch: 140nm) is ~0.34 on a 0.93 NA exposure tool that is available currently. RET (resolution enhancement technology) is necessary to achieve the difficult process goal. Splitting pitch technology is an RET approach to solving 45nm contact pattering. In this paper, we use a 2P1E (2 photo exposure and 1 etching) approach to meet our process requirements. The original layout is split into dense pitch pattern and semi-iso to iso pattern parts by software. Utilizing strong OAI (off-axis-illumination) on dense pattern part and weak OAI on semi-iso to iso pattern part can obtain better process results.

A study of process window capabilities for two-dimensional structures under double exposure condition

Abstract: Among the three candidate approaches for 32 nm, the double exposure/patterning with 1.35 NA immersion, the high refractive index immersion, and the extremely ultra violet (EUV) lithography, the easiest approach seems to be the double exposure/patterning method at an effective numerical aperture (NA) of 1.35. However, the design and optimization of the process, such as, the choice of illu mination condition, the choice of a photoresist, and the design of an optical proximity correction (OPC) strategy for both the singly and doubly exposed patterns still need to be developed. In this paper, we will focus on the finding of a suitable methodology in the printing of two-dimensional (2D) structures under the double exposure and single development scheme since it is the easiest and there is virtually no overlay concern. We have used a 248 nm exposure tool and a well-chosen photoresist to study the photo performance parameters in the merge of two photo exposures. At a numerical aperture (NA) around 0.7, the minimum ground rule we can achieve is 110 nm, similar to the one for a 75 nm logic-like process with minimum pitch of 220 nm. In the experiment, the single exposure structures are limited to pitches wider than 440 nm. In this paper, we will present a study on main process window parameters, such as, exposure latitude (EL), depth of focus (DOF), and mask error factor (MEF) for a typical 2D structure, the isolated opposing line end. We will demonstrate a near ly analytical method for the description of the line end shortening. Key words : Double Exposure, Line end shortening, LES, Effec tive resist diffusion length, partially coherent illumination

PROPER: an optical propagation library for IDL

Abstract: PROPER is a library of IDL (Interactive Data Language) routines for simulating optical propagation in the near and far fields using Fourier-based Fresnel and angular spectrum methods. The goal of PROPER is to provide a free, easy-to-use, and versatile means for simulating systems that require diffraction-based rather than geometrical analyses, such as spatial filtering systems with intermediate optics (e.g. a stellar coronagraph for extrasolar planet imaging). It has routines for creating complex apertures and obscurations, wavefront errors (defined by Zernikes, power spectra, or user-supplied maps), amplitude modulators (e.g. coronagraphic occulters), simple lenses, and deformable mirrors. The routines automatically select which propagator (near or far-field) is best at each surface based on analytically propagating a Gaussian pilot beam. The library includes a comprehensive manual and is distributed as IDL source code.

The improvement of photolithographic fidelity of two-dimensional structures through double exposure method

Abstract: With the semiconductor fabrication groundrule approaching the 32 nm node, double exposure or patterning method with 1.35 NA immersion seems to be the primary candidate due to its relative easiness to implement when compared to the other two competitors, the high refractive index immersion and the 13.4 nm extremely ultraviolet (EUV) lithography. However, the splitting of one mask into two is not a trivial task. In this paper, we would like to discuss about the best splitting method for several typical 2D structures, such as the isolated opposing line (or space) end shortening, T-like structures with narrow gaps, etc. From our recent experimental studies, we have found that, for line and space photolithography, the optimized illumination condition has a sigma value very close to 0.5. When compared to the single exposure processes, which will typically use more annular condition, a sigma of 0.5 can generate worse process windows for isolated features. This will put more pressure on the precision of the already challenging optical proximity correction (OPC) because the doubly exposed patterns and singly exposed patterns follow two different models. In our study, we find that the extra degrees of freedom in the double exposure method can be utilized to repair some intrinsic printing deficiency, such as, line end shortening. In this paper, we will analyze each typical 2D structure and, for each splitting method of the typical 2D features we study, we will discuss its capabilities in realizing good process windows, the MEF, and OPC correction easiness.

Use of a commercial laser tracker for optical alignment

Abstract: Laser trackers have been developed that project laser beams and use optical systems to provide three dimensional coordinate measurements. The laser trackers incorporate a servo system to steer a laser beam so that it tracks a retroreflector, such as a corner cube. The line of sight gimbal angles and the radial distance to the retroreflector are used to determine the coordinates of the retroreflector relative to the tracker. In this paper, we explore the use of the laser tracker to define the metrology for aligning optical systems, including the use of mirrors and windows. We discuss how to optimize the geometry to take advantage of the tracker’s most accurate measurements. We show how to use the tracker for measuring angles as well as points.

Double patterning design split implementation and validation for the 32nm node

Abstract: Single exposure capable systems for the 32nm 1/2 pitch (HP) node may not be ready in time for production. At the possible NA of 1.35 still using water immersion lithography, one option to generate the required dense pitches is double patterning. Here a design is printed with two separate exposures and etch steps to increase the pitch. If a 2x increase in pitch can be achieved through the design split, double patterning could thus theoretically allow using exposure systems conceived for the 65nm node to print 32nm node designs. In this paper we focus on the aspect of design splitting and lithography for double patterning the poly layer of 32nm logic cells using the Synopsys full-chip physical verification and OPC conversion platforms. All 32nm node cells have been split in an automated fashion to target different aggressiveness towards pitch reduction and polygon cutting. Every design split has gone through lithography optimization, Optical Proximity Correction (OPC) and Lithography Rule Checking (LRC) at NA values of 0.93, 1.20, and 1.35. Final comparisons are based on simulations across the process window. In addition, we have experimentally verified selected single-patterning problem areas on a 1.20 NA exposure tool (ASML XT:1700Fi at IMEC). With this information, we establish guidelines for double patterning conversions and present a new design rule for double patterning compliance checking applicable to full-chip scale.

A wide-angle view at iterated shrinkage algorithms

Abstract: Sparse and redundant representations − an emerging and powerful model for signals − suggests that a data source could be described as a linear combination of few atoms from a pre-specified and over-complete dictionary. This model has drawn a considerable attention in the past decade, due to its appealing theoretical foundations, and promising practical results it leads to. Many of the applications that use this model are formulated as a mixture of l 2 -l p ( p ≤ 1) optimization expressions. Iterated Shrinkage algorithms are a new family of highly effective numerical techniques for handling these optimization tasks, surpassing traditional optimization techniques. In this paper we aim to give a broad view of this group of methods, motivate their need, present their derivation, show their comparative performance, and most important of all, discuss their potential in various applications.

Patterning with amorphous carbon spacer for expanding the resolution limit of current lithography tool

Abstract: Double patterning technique using spacer which can avoid CD (Critical Dimension) uniformity problem mainly caused by overlay issue is one of the methods that could be applied to apply to manufacturing of memory devices. Though double exposure and etch technology (DEET) has comparative advantage in the number of process steps, it is required to dramatically improve overlay performance of current exposure tools for the realization of manufacturing. In this study, negative type-double pattering technique using spacer has been developed as the best way for the application of NAND flash memory device from the view point of CD uniformity and the number of mask layers used to complete double patterning. Negative type-double patterning technique using spacer consists of subsequent steps such as formation of poly line, spacer on sidewall of poly line, SOG gap fill into space between poly lines, SOG etch back, removal of spacer, and finally hard mask etch. We have used amorphous carbon as a spacer material to easily remove spacer from poly lines and adopted SOG material to easily fill in space between poly lines. When negative type-double patterning technique using spacer is applied to NAND flash memory device, we can expect that k1 factor of about 0.14~0.20 could be accomplished successfully.

HD Photo: a new image coding technology for digital photography

Abstract: This paper introduces the HD Photo coding technology developed by Microsoft Corporation. The storage format for this technology is now under consideration in the ITU-T/ISO/IEC JPEG committee as a candidate for standardization under the name JPEG XR. The technology was developed to address end-to-end digital imaging application requirements, particularly including the needs of digital photography. HD Photo includes features such as good compression capability, high dynamic range support, high image quality capability, lossless coding support, full-format 4:4:4 color sampling, simple thumbnail extraction, embedded bitstream scalability of resolution and fidelity, and degradation-free compressed domain support of key manipulations such as cropping, flipping and rotation. HD Photo has been designed to optimize image quality and compression efficiency while also enabling low-complexity encoding and decoding implementations. To ensure low complexity for implementations, the design features have been incorporated in a way that not only minimizes the computational requirements of the individual components (including consideration of such aspects as memory footprint, cache effects, and parallelization opportunities) but results in a self-consistent design that maximizes the commonality of functional processing components.

Overview of novel integrated optical ring resonator bio/chemical sensors

Abstract: In parallel to a stand-alone microsphere resonator and a planar ring resonator on a wafer, the liquid core optical ring resonator (LCORR) is regarded as the third type of ring resonator that integrates microfluidics with state-of-the-art photonics. The LCORR employs a micro-sized glass capillary with a wall thickness of a few microns. The circular cross section of the capillary forms a ring resonator that supports the whispering gallery modes (WGMs), which has the evanescent field in the core, allowing for repetitive interaction with the analytes carried inside the capillary. Despite the small physical size of the LCORR and sub-nanoliter sensing volume, the effective interaction length can exceed 10 cm due to high Q-factor (106), significantly improving the LCORR detection limit. The LCORR is a versatile system that exhibits excellent fluid handling capability inherent to capillaries and permits non-invasive and quantitative measurement at any location along the capillary. Furthermore, the LCORR uses the refractive index change as a transduction signal, which enables label-free detection. Therefore, the LCORR is a promising technology platform for future sensitive, miniaturized, lab-on-a-chip type sensors. In this paper, we will introduce the concept of the LCORR and present the theoretical analysis and the experimental results related to the LCORR sensor development.

Recent advances in optically pumped semiconductor lasers

Abstract: Optically pumped semiconductor lasers offer significant advantages with respect to all traditional diode-pumped solid state lasers (including fiber lasers) in regards to wavelength flexibility, broad pump tolerance, efficient spectral and spatial brightness conversion and high power scaling. In this talk we will describe our recent progress in the lab and applying this technology to commercial systems. Results include diversified wavelengths from 460 to 570nm, power scaling to >60W of CW 532nm, and the launch of a low cost 5W CW visible source for forensic applications.

Overview of the near-infrared spectrograph (NIRSpec) instrument on-board the James Webb Space Telescope (JWST)

Abstract: The James Webb Space Telescope (JWST) mission is a collaborative project between the National Aeronautics and Space Administration (NASA), the European Space Agency (ESA) and the Canadian Space Agency (CSA). JWST is considered the successor to the Hubble Space Telescope (HST) and although its design and science objectives are quite different, JWST is expected to yield equivalently astonishing breakthroughs in infrared space science. Due to be launched in 2013 from the French Guiana, the JWST observatory will be placed in an orbit around the anti- Sun Earth-Sun Lagrangian point, L2, by an Ariane 5 launcher, provided by ESA. The payload on board the JWST observatory consists of four main scientific instruments: a near-infrared camera (NIRCam), a combined mid-infrared camera/spectrograph (MIRI), a near-infrared tunable filter (TFI) and a nearinfrared spectrograph (NIRSpec). The instrument suite is completed by a Fine Guidance Sensor (FGS). Besides the provision of the Ariane 5 launcher, ESA, with EADS Astrium GmbH (D) as Prime Contractor, is fully responsible for the funding and the furnishing of NIRSpec and, at the same time, for approximately half of MIRI costs through special contributions from the ESA member states. NIRSpec is a multi-object, spectrograph capable of measuring the spectra of about 100 objects simultaneously at low (R=100), medium (R=1000), and high (R=2700) resolutions over the wavelength range between 0.6 micron and 5.0 micron. In this article we provide a general overview of its main design features and performances.

Double pattern EDA solutions for 32nm HP and beyond

Abstract: The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k1 for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k1 for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

Overview of the inter-orbit and the orbit-to-ground laser communication demonstration by OICETS

Abstract: The experiment results on the inter-orbit laser communications between OICETS and a geostationary satellite and the results of two kinds of orbit-to-ground laser communications between OICETS and ground stations are summarized. The geostationary satellite for the inter-orbit demonstrations is the European Space Agency's geostationary satellite, ARTEMIS, and the ground stations for the orbit-to-ground demonstrations are of the National Institute of Information, and Communications Technology (NICT) in Japan and the German Aerospace Center (DLR), respectively. The descriptions of those experiments contain some statistically analyzed results as well as data samples measured during the demonstrations. The authors present the overview of these demonstration progresses and discuss on the results.

Nonlinear filters with log-homotopy

Abstract: We derive and test a new nonlinear filter that implements Bayes' rule using an ODE rather than with a pointwise multiplication of two functions. This avoids one of the fundamental and well known problems in particle filters, namely "particle collapse" as a result of Bayes' rule. We use a log-homotopy to construct this ODE. Our new algorithm is vastly superior to the classic particle filter, and we do not use any proposal density supplied by an EKF or UKF or other outside source. This paper was written for normal engineers, who do not have homotopy for breakfast.