Showing papers in "Solid-state Electronics in 1974"

Minority carrier MIS tunnel diodes and their application to electron- and photo-voltaic energy conversion—I. Theory☆

Abstract: If the insulating layer in a metal-insulator-semiconductor (MIS) diode is very thin ( A for AlSiO2Si), measureable tunnel current can flow between the metal and the semiconductor. If the insulating layer is even thinner ( A ), tunnel currents are so large that they can significantly disturb the semiconductor from thermal equilibrium. Under such conditions, MIS diodes exhibit properties determined by which of the following tunneling processes is dominant; tunneling between the metal and the majority carrier energy band in the semiconductor, between the metal and the minority carrier energy band, or between the metal abd surface state levels. In the present paper, minority carrier MIS tunnel diodes are analysed using a very general formulation of the tunneling processes through the insulator, transport properties in the semiconductor, and surface state effects. Starting from solutions for diodes with relatively thick insulating layers where the semiconductor is essentially in thermal equilibrium, solutions are obtained for progressively thinner insulating layers until non-equilibrium effects in the semiconductor are observed. It is shown that such minority carrier MIS tunnel diodes with very thin insulating layers possess properties similar to p-n junction diodes including exponential current-voltage characteristics which approach the “ideal diode” law of p-n junction theory. The theory adequately describes the observed properties of experimental devices reported in a companion paper. The diodes have application as injecting contacts, as photodiodes or elements of photodiode arrays, and as energy conversion devices employing the electron- or photo-voltaic effects.

A simple theory to predict the threshold voltage of short-channel IGFET's

Abstract: A simple expression for the threshold voltage of an IGFET is derived from a charge conservation principle which geometrically takes into account two-dimensional edge effects. The expression is derived for zero drain voltage and is valid for short and long-channel lengths. The dependence of the threshold voltage on the source and drain diffusion depth, r j , and channel length, L , is explicitly given. In the limit, L / r j → ∞, the threshold voltage equation reduces to the familiar expression for the long-channel case. The theory is compared with the measured threshold voltages on IGFET's fabricated with 1·4, 3·8 and 7·4 μm channel lengths. The dependence of the threshold voltage under backgate bias voltages ranging from zero to breakdown agrees closely with the theory.

Contact size effects on the van der Pauw method for resistivity and Hall coefficient measurement

Abstract: Effects on van der Pauw's resistivity and Hall coefficient measurement due to finite size contacts with selected shapes on a square sample were investigated. For the sheet resistivity measurement, correction factors for the apparent measured values at zero magnetic field were determined from both electrolytic tank experiments and computerized over-relaxation calculations. For the Hall coefficient, correction factors for the effect of voltage shorting due to current electrodes and for the effect of current shorting due to Hall electrodes were calculated (by use of a fast-convergent over-relaxation technique) through a range of Hall angle from tan θ = 0·1–0·5. The current shorting contribution to the correction factor at zero magnetic field was also closely estimated by use of an electrolytic tank. In the symmetrical structures studied the Hall errors introduced by the voltage and current electrodes were approximately equal. The study shows that contacts of appreciable size relative to that of the sample can be a good approximation to van der Pauw's infinitesimal contact. Thus, one can utilize the simplicity and other advantages of finite size ohmic contacts for these measurements in normal semiconductor materials evaulation and still obtain precise data by using the appropriate correction factors determined in this paper.

Current multiplication in metal-insulator-semiconductor (MIS) tunnel diodes☆

Abstract: In contrast to thick insulator structures, metal-insulator-semiconductor (MIS) diodes with very thin insulating layers (< 30 A for the silicon-silicon dioxide system) allow appreciable tunnel current flow between the metal and the semiconductor causing the semiconductor to depart significantly from thermal equilibrium conditions when the diode is biased. Under such conditions, recent experiments have demonstrated that multiplication of minority carrier current can occur in the contact region. This multiplication process is described in detail by deriving analytical expressions characterizing this process and its dependence upon the metal, insulator, and semiconductor parameters for one specific class of diode. Numerical methods are used to investigate the multiplication properties under more general conditions. Solutions obtained by this method indicate that values of the small signal multiplication factor, M, in the range of 102–103 can be obtained with appropriately designed diodes. The applications of the multiplication process to a transistor structure and to a photodiode with internal multiplication properties are described briefly.

Properties of Au, Pt, Pd and Rh levels in silicon measured with a constant capacitance technique

Abstract: Measurements of emission rates and majority carrier capture cross-sections of Au, Pt, Pd and Rh centres in silicon are reported, and the activation energies associated with the different levels of these centres are determined. Where appropriate, our results are compared with values reported in the literature; other results have not been previously reported. The measurement depends on the emission and capture of majority carriers on the centres in the depletion layer of a p-n junction or Schottky barrier. The change in charge state of the centres is monitored by measuring the change in reverse bias applied to the junction necessary to keep the junction capacitance constant. The advantage of this technique, compared with the usual method of keeping the bias voltage constant and measuring the change in capacitance, is demonstrated.

Famos—A new semiconductor charge storage device

Abstract: A new non-volatile charge storage device is described. The floating gate avalanche injection MOS (FAMOS) structure is a p -channel silicon gate field effect transistor in which no electric contact is made to the silicon gate. It combines the floating gate concept with avalanche injection of electrons from the surface depletion region of a p - n junction to yield reproducible charging characteristics with long term storage retention.

Saturation capacitance of thin oxide MOS structures and the effective surface density of states of silicon

Abstract: The capacitance vs voltage curve of thin oxide (30–40 A) MOS structures in strong accumulation was studied. The results were interpreted in terms of equivalent surface density of state masses, which was found to be 0·2 m 0 for the silicon valence band and 0·06 m 0 for the conduction band, for both 111 and 100 surfaces. The experimental density of state masses were shown to be much lower than the bulk values. Equivalent density of states masses were calculated from a surface quantization model and in this case agreement with the experiments was obtained for the valence band only.

Theory of transient emission current in MOS devices and the direct determination interface trap parameters

Abstract: The physics is discussed of the emission of electrons from interface states in metal-insulator-semiconductor (MIS) systems, under isothermal, non-steady-state conditions. Generalized equations are then derived which permit the determination of the non-steady-state, emission current vs time characteristics for MOS systems containing an arbitrary distribution of surface states; the special case of a discrete surface state is also studied. More important, however, by appropriate plotting of the data, it is shown how to directly extract from the experimental data the energy distribution and the capture cross section of the interface traps in the upper-half of the band gap in the case of n-type semiconductors, and in the lower-half of the band gap in the case of p-type semiconductors.

Fabrication and some applications of large-area silicon field emission arrays

Abstract: A method of fabricating large-area arrays of sharply-pointed field emitters at densities up to 1·5 × 10 5 per cm 2 from single crystal silicon wafers is described. The point emitters are formed by etch-undercutting a precision oxide pattern which is delineated on the silicon surface by projection photolithography. Observations indicate that emitters with very small tip dimensions in the 200Arange are formed. In the presence of an external electric field, such as produced by a voltage applied to a closely-spaced, planar anode, multiple-emitter arrays are shown to field-emit electrons uniformly over areas up to 3 cm dia. Two important applications currently being explored, are discussed: (1) High resistivity, p -Si has been utilized to develop experimental field emission photocathodes with which field emission imaging has been demonstrated. These photoemitters exhibit very high photo-sensitivities at visible and near i.r. wavelengths. For example, at 0·86 μm, the measured quantum efficiency is 25 per cent which is about five-times higher than the red-sensitive S-20 photocathode and comparable to the highest reported sensitivities of the III–V photosurfaces; (2) N -type emitter arrays show considerable promise as high current, cold cathodes and total emission currents of 1/4 A from 1 cm 2 areas of 100 Ω-cm n -type emitters have been obtained. Measurements were made under pulse conditions because of anode dissipation considerations.

Electrical characteristics of the SiO2Si interface near midgap and in weak inversion

Abstract: The electrical characteristics of the SiO 2 Si interface in depletion are well understood, but very little information is available on the behavior of surface states in the midgap and weak inversion regions. In this work we develop a general numerical model for the surface state branch which is valid in all bias regions. The model is compared to experimental results in detail, and the surface state density and electron capture cross-section are deduced in the lower half of the bandgap (weak inversion) for two thick oxide samples. The electron capture cross-section was found to be relatively independent of energy through midgap and into weak inversion, in contrast to the exponential dependence on energy reported by others in depletion. The ratio of electron capture cross-section to hole capture cross-section is measured at midgap and found to have a systematic dependence on midgap surface state density, independent of substrate orientation or sample annealing. It is possible that this observation arises because of inadequacies in the model.

Quenched-in centers in silicon p + n junctions

Abstract: Silicon p+n junctions heat treated at high temperatures (1200°C) for a long time (2–20 hr) and then quenched to room temperatures or below shows two deep donor levels (EC−264meV andEC−542meV) in the n-type side of the junction depletion layer which appear to originate from the same imperfection center. The concentration of these levels ranges from 1013 to 1014 cm−3. The junction leakage current comes from carrier generation at the deeper level in the depletion region. Phosphorus gettering was found ineffective in reducing the concentration of these quenched-in levels, but they are annealed out by very slow cooling (25°C/hr to 650°C then quench to room temperatures). The thermal emission and capture rates of electrons and holes at these levels are measured as a function of temperature and electric field by the junction high frequency capacitance and d.c. leakage current transient techniques. It is demonstrated that the detailed balance relationship does not hold. The origin of this double donor center is yet to be identified.

The GaAs inversion-type MIS transistors

Abstract: The alloying technique for source and drain n + regions and the chemical-vapor-deposited double layer films of Al 2 O 3 and SiO 2 were found to be useful for the realization of the inversion channel GaAs MIS transistors. This is because the alloying was carried out at much lower temperature than donor diffusion and the stability was remarkably improved by using the double layer above mentioned. The transistor had an effective mobility of 2240 cm 2 /V.sec, and the threshold voltage was controlled by changing the thickness ratio of the two films. The characteristics of the transistor were compared with the theoretical curves which were calculated by considering several limiting factors; bulk charges, a saturation velocity of carriers and series resistances. The fairly good agreement between the two was found. Some discrepancies, recognized in some cases, seemed to be attributable to some unknown parameters in the theory and to influences of interface states.

Very low resistance NiAuGeNi contacts to n-GaAs

Abstract: The contact resistance of alloyed NiAuGeNi contacts has been measured on n -GaAs. The quality of the contacts was strongly influenced by the pre-evaporation cleaning of the semiconductor surface. Compared to chemical etching, sputter cleaning considerably reduced the contact resistance and improved reproducibility. Optimization of the alloying cycle led to contact resistances lower than the state of the art.

Field-enhanced carrier generation in MOS capacitors

Abstract: When sufficiently high voltage steps are used for driving a metal-oxide-semiconductor capacitor (MOSC) towards deep inversion, the temporal evolution of the current and of the high-frequency capacitance during the return to equilibrium cannot be interpreted on the basis of a theory assuming a constant bulk generation lifetime. A more general theory, which takes into account field-dependent carrier emission rates, is developed and it is shown how current and h.f. capacitance measurements can be used to determine the field dependence of the bulk generation lifetime. The results of experiments performed on differently processed MOSC's are presented; they support the hypothesis that field-enhancement of carrier emission rates takes place according to a mechanism of the Poole-Frenkel-type.

Theory of non-steady-state interfacial thermal currents in MOS devices, and the direct determination of interfacial trap parameters

Abstract: Generalized equations are derived that permit the determination of the non-steady-state, thermal current vs temperature characteristics due to the emission of charge from interface states in MOS devices when the temperature increases uniformly with time. The equations are applicable to any trap distribution that extends over more than about 4kT in energy; the equations for discrete traps are also presented. The important result emerging from this work is that in the case of distributed traps the I−T characteristic is a direct reflection of the energy distribution of the interface traps. Furthermore, it is shown how the attempt-to-escape frequency ν of the traps and, hence, their capture cross-section may be determined. The determination of the trap density and energy and ν for discrete trap levels is also discussed.

Non-ionic room temperature instabilities in MOS devices

Abstract: Recently it has been pointed out that considerable instabilities can occur in MOS devices under negative voltage bias at room temperature. These instabilities are observed by appling at room temperature a voltage to the gate of an MOS device, cooling under this voltage bias to 77°K and subsequently measuring the CV curve or the threshold voltage with the applied voltage bias as parameter. The instabilities are due to the generation of positive charges in the oxide and cause negative voltage shifts. The generation of positive charges appears to be due to two types of centres (type 1 and type 2). Whereas the charge in the type 2 centres is stable at 77°K, the charge in the type 1 centres disappears at 77°K as soon as free electrons are present at the surface. Furthermore there is an increased fast interface state density, which is closely related to the positive charge in the type 2 centres. In this paper the charging of both centres is described in terms of a thermally assisted tunnelling process. In this way the observed time and temperature dependencies of the charging are explained and activation energies are determined. A model is presented that explains among other things the different discharge behaviour of the type 1 and type 2 centres.

The gate-controlled diode s0 measurement and steady-state lateral current flow in deeply depleted MOS structures

Abstract: A detailed analysis of steady state lateral current flow in the deeply depleted gate-controlled diode structure is performed primarily to ascertain the minority carrier quasi-Fermi level positioning and lateral variation near the oxide-semiconductor interface. From a consideration of limiting case solutions it is quantitatively established that, under typical conditions, the semiconductor surface will be weakly inverted over all but a small fraction of the surface channel for gate biases far below the voltage required to strongly invert the surface. It follows from this weak inversion positioning of the minority carrier quasi-Fermi level that the s0-value deduced from the previously published interpretation of gate-controlled diode data will be less, typically much smaller, than the true depleted surface recombination velocity. A method for ascertaining the minimum error in the previously published s0 determination procedure is presented and illustrated.

The work function difference of the MOS-system with aluminium field plates and polycrystalline silicon field plates

Abstract: The work function difference of the AlSiO 2 Si-system was measured by the MOS-capacitance-voltage technique for n - and p -type silicon as substrate and was compared to the results obtained by different authors applying the photoemission technique. It could be seen that the work function differences measured in this work differ largely from the values measured by the photoemission technique. On the basis of the results obtained the work function differences of the p + polySiSiO 2  nSi - and n + polySiSiO 2  p Si-system were defined by comparative measurements. From this it was evident that the location of the Fermi level in heavily doped polycrystalline silicon is identical to the location of the Fermi level in monocrystalline silicon of the same impurity concentration.

Surface-state spectra from thick-oxide MOS tunnel junctions

Abstract: The conductance and capacitance of thick-oxide MOS tunnel junctions (SiO2 thickness 40 to 65 A) have been measured from 35 Hz to 210 kHz. It is demonstrated that the use of a thick-oxide MOS tunnel junction makes it possible to obtain the surface-state data throughout the whole silicon band gap with better resolution and better sensitivity than the conventional MOS capacitance techniques. A slight departure from equilibrium may occur in the voltage range where large tunnel current flows. Corrections to the energy scale must be made in this voltage range. A method for the evaluation of the junction quality is discussed. The simplified equivalent circuits necessary for the calculation of surface-state data are constructed under various bias conditions by an approach different from that used in a previously published work. The present work supports the model that at least some of the observed surface states are a consequence of the diffusion of contact metals into the oxide.

Determination of the energy distribution of interface traps in MIS systems using non-steady-state techniques

Abstract: Experimental techniques are described for determining the energy distribution of interface traps at the semiconductor-insulator interface of MIS devices The device used here was an MNOS capacitor in which the semiconductor was n -type The first technique which is described is that of measuring the thermally stimulated currents The method consists of biasing the capacitor into the accumulation mode at a low temperature thereby filling the traps at the semiconductor oxide interface The device is then biased into the deep-depletion mode in which state the traps remain filled because the temperature is too low to allow the electrons to be thermally excited out of the traps The temperature of the device is then raised at a uniform rate, and the current associated with the release of electrons from the trap is monitored The shape of the I−T characteristic is a direct image of the interface trap distribution is a broad peak with a maximum at 0·35 eV below the bottom of the conduction band, and of height approximately 6 × 10 13 cm −2 eV −1 The experiments were carried out at two heating rates (0·1°K/sec and 0·01°K/sec), and the trap densities so obtained were identical The second method consists of biasing the device into the accumulation mode at a fixed temperature thereby filling the traps at the silicon-silicon oxide interface It is then short-circuited and the non-steady state transient current associated with the release of electrons from the interface traps is monitored The energy distribution of the interface traps in the upper half of the forbidden gap is shown to be readily obtained from the transient currents, and is found to be identical to that obtained using the thermal technique

Mechanism of light production in metal-insulator-semiconductor diodes; GaN:Mg violet light-emitting diodes

Abstract: The mechanism of electroluminescence in MIN GaN:Mg violet light-emitting diodes was analyzed by considering observed structural features of the diodes as well as their electrical and optical characteristics. Comparison of the observed I – V characteristic, including dependence upon temperature and upon film thickness, with all possible mechanisms for conduction in insulators lead to a proposed conduction mechanism of quantum mechanical tunneling, with the I – V characteristic being well represented by the Fowler-Nordheim equation. The proposed mechanism of light production involved impact ionization of luminescent centers near the i - n junction, with subsequent radiative recombination. This proposed mechanism was supported by measurements of carrier multiplication in the device and a steep voltage gradient at the i - n junction. The impact ionization process occurs in discrete regions coincident with sub-grain boundaries in the GaN film.

VMOS—A new MOS integrated circuit technology

Abstract: A new V-groove MOS integrated circuit technology (VMOS) is described It makes use of preferential etching of silicon to define the channels of the MOS transistors The fabrication involves either a three or four mask process and is capable of producing either silicon gate or standard metal gate transistors The technology results in very short channel length devices using non-critical alignment tolerances Despite the short channel length, the VMOS transistor exhibits lower output conductance and higher breakdown voltage than a standard MOS transistor A first order theory is presented for the VMOS transistor along with measurements made on test devices of various channel lengths Some integrated circuit applications of the technology are also presented, including an R-S fiip-flop and a 27-stage bucket brigade shift register The advantages of the VMOS technology in such applications are discussed

Characterization of multiple deep level systems in semiconductor junctions by admittance measurements

Abstract: The small signal admittance, Y, of a junction device, in the presence of deep lying majority carrier traps, is obtained as a solution to a simple differential equation (dC/dχ) = (C2/e)−(ρac/ψac), where C Y/jω is the complex capacitance, x is the distance within the depletion region from the neutral bulk semiconductor, ρac is the a.c. incremental change in charge density at χ when the bias is incremented by ψac. This equation can be numerically integrated with one boundary condition, the flat band capacitance of the bulk semiconductor. An analytic solution to the above differential equation is possible over a wide frequency range without the use of a truncated space charge approximation. The admittance of one half of a junction device can then be modelled by a 3p + 1 lumped element equivalent circuit involving 3p + 2 device parameters, where p is the number of species of deep lying majority carrier traps that are virtually unionized in the bulk. These circuit elements bear simple direct relationships to the deep level parameters. Impedance vs frequency measurements at a single bias and temperature yield only 2p + 1 equations and are not sufficient to define the elements uniquely. One therefore needs p + 1 additional equations for a unique synthesis. We also show how additional equations can be obtained from impedance vs voltage or temperature measurements.

On heavy doping effects and the injection efficiency of silicon transistors

Abstract: A study of heavy doping effects on the current gain of diffused bipolar silicon transistors is continued, with emphasis on the variation of the current gain with injection level. The sensitivity of the calculations to some assumptions and approximations made previously is appraised. Numerical solutions of the heavy doping model simultaneously with the carrier transport equations are included.

Preparation and properties of plasma-anodized silicon dioxide films

Abstract: The preparation and properties of thin films of silicon dioxide formed at ∼ 200°C by anodization in an RF plasma are described. A suitable procedure for obtaining good quality films is given along with information on the effects of film sputtering and internal stress build-up during anodization. Measurements on MOS capacitors utilising the plasma-grown oxide yielded information on oxide charges, Si/SiO2 interface state density, oxide permittivity, leakage resistance and film breakdown strength. Additional measurements determined the physical properties of stochiometry, impurity content, refractive index and etching behaviour. The plasma-anodized films can be routinely grown to a quality comparable with the best thermally-grown oxides.

A detailed analysis of the metal-semiconductor contact

Abstract: A general quantum and electronic theory able to explain the electric and photoelectric experimental properties of the metal-semiconductor contacts is proposed. The theory consists firstly in calculating the electric space charge due to the quantum mechanical tunneling of the electrons from the metal into the semiconductor, and vice-versa, and to the metal and semiconductor bands bending. Then the electric charge so obtained is utilised to solve in an appropriate and complete way the Poisson equation so as to determine the electric field and potential as functions of the abscissa x. The electric field F(x) is employed to obtain a new expression for the junction capacitance C, holding in the general case of a non-uniform charge, whereas the electric potential νi(x) is used to calculate general expressions for the thermionic and photoelectric currents i and iph, respectively, taking into account in this both the tunneling probability through the energy barrier and the many-valley structure of the semiconductor energy bands. Finally, from νi(x), C, i and iph four new expressions of the energy barrier height of the contact are deduced. The theoretical results relative to the barrier height so determined (which hold for both n-and p-type semiconductors) are compared with published experimental values obtained, by means of capacitance and photocurrent measurements: (a) on contacts between n-type CdS and Au, Cu, Ag and Pt; (b) on contacts between n-type GaAs and Au, Ag, Cu, Sn, Al and Pt and; (c) on contacts between p-type GaAs and Au and Al. The agreement between the theoretical and experimental values is very good.

A small signal analysis of an impatt device having two avalanche layers interspaced by a drift layer

Abstract: A small signal analysis of an IMPATT device (p−n−i−p−n structure) having two avalanche layers interspaced by a drift layer is carried out. When the widths of the two avalanche layers are different the device exhibits discrete negative conductance frequency bands separated by positive conductance frequency bands. Oscillations are expected to occur more favourably in the lowest frequency band where the maximum and minimum values of magnitudes of negative conductance and negative Q occur, respectively. When the two avalanche layer widths are equal, the device impedance is a high Q-reactance whose magnitude depends on the d.c. current.

Questionability of drift-diffusion transport in the analysis of small semiconductor devices

Abstract: Analysis and design of such semiconductor devices as bipolar and field-effect transistors now relies, in part, on the assumption that current flows by drift and diffusion. The minute size of existing devices raises questions about the appropriateness of this assumption, however, because an internal region critical to device performance may become so small that carriers crossing it fail to experience many collisions. To demonstrate possible consequences of continuing to base analysis on assumed drift and diffusion, we contrast the predictions of two models for the electrical base region of a bipolar transistor. The first model assumes that carriers in transit across the base will experience many collisions, which requires a base region of sufficiently large dimensions. The second model assumes that a carrier in transit will suffer no collisions, displaying what tends to occur in the limiting case of small dimensions. A comparison of saturation current, temperature dependence, and base transit time shows that significant differences exist.

Application of the small-signal transmission line equivalent circuit model to the a.c., d.c. and transient analysis of semiconductor devices

Abstract: It is shown that the use of the small signal transmission line equivalent circuit model is not restricted solely to the small signal a.c. analysis of semiconductor devices. Simple algorithms are described which allow it to be used to compute the d.c. and the large signal transient properties of semiconductor devices to any desired precision. The approach is demonstrated by computing the a.c., d.c. and transient properties of an N + P junction diode.

Electrolytic etching and electron mobility of GaAs for FET's

Abstract: An electrolytic etching technique for n-GaAs is presented. The procedure is applied to post-growth etching of FET wafers to achieve uniformly thin layers from excessively thick and nonuniform material. Measurements on a Hall sample, thinned by this technique, show mobilities in good agreement with theoretical bulk mobility calculations for films as thin as 2100 A. From Hall measurements on layers covered by the anodic native oxide, it is determined that the oxide interface traps 3·9 × 1011 electrons per cm2 more charge than the as-grown surface.