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Showing papers in "Solid-state Electronics in 1990"


Journal ArticleDOI
TL;DR: In this paper, the authors define the multiplication factor and the ionization rate together with their interrelationship, multiplication and breakdown models for diodes and MOS transistors.
Abstract: After defining the multiplication factor and the ionization rate together with their interrelationship, multiplication and breakdown models for diodes and MOS transistors are discussed. Different ionization models are compared and test structures are discussed for measuring the multiplication factor accurately enough for reliable extraction of the ionization rates. Multiplication measurements at different temperatures are performed on a bipolar NPN transistor, and yield new electron ionization rates at relatively low electrical fields. An explanation for the spread of the experimental values of the existing data on ionization rate is given. A new implementation method for a local avalanche model into a device simulator is presented. The results are less sensitive to the chosen grid size than the ones obtained from the existing method.

209 citations


Journal ArticleDOI
TL;DR: In this paper, a first principles approach to the problem of thermal breakdown in semiconductor devices is developed using Green's function formalism, which allows all three dimensions of the defect to take on the full range of values.
Abstract: A first principles approach to the problem of thermal breakdown in semiconductor devices is developed using Green's function formalism. The problem of thermal runaway at a defect of arbitrary geometry, subject to an arbitrary power profile, is considered. A solution is presented for the specific case of a rectangular parallelepiped shaped defect, subject to constant input power. It is expected that this geometry will model the defect in many semiconductor devices more accurately than the defect geometries used in the past. Unlike previous work, this allows all three dimensions of the defect to take on the full range of values. The theory developed here provides a natural framework for the explanation of results previously reported in the literature. It is shown that there are four time domains and not three as previously thought, and these exist for all shapes of defect. Thus, it is wrong to conclude that a pulse power/time to failure dependence of the form P f α t f − 1 2 necessarily implies a roughly two-dimensional defect. Several relationships are found to exist within the model which allow estimates to be made of the defect dimensions and failure temperature. Experimental data drawn from the literature, produce Pf/tf profiles similar to those indicated by the theory.

206 citations


Journal ArticleDOI
TL;DR: In this paper, Ni/n-CdF2 Schottky barrier type diodes were fabricated on unpolished CdF 2 surface, etched with 1 : HCl and showed an MIS structure with interface states and deep donor bulk defects.
Abstract: Current-voltage (I-V) and capacitance-voltage (C-V) measurements were performed in the temperature range 45–330 K on Ni/n-CdF2 Schottky barrier type diodes fabricated on unpolished CdF2 surface, etched with 1 : HCl. The diodes showed an MIS structure with interface states and deep donor bulk defects. Under forward bias and for T ⩾ 280 K, the electric current transport was controlled by the thermionic emission process. However, for T ⩽ 280 K, the current was controlled by thermionic field emission. The zero bias and zero temperature barrier height, φ0 = (0.67 ± 0.07) V was obtained from the I-V measurements and agreed very well with the value of φ0 = (0.60 ± 0.06) V, determined from the C-V data. The energy density of interface states estimated from the room temperature I-V measurements was ≈ 1012 cm−2 eV−1. The interface states were responsible for the non-ideal behavior of the forward I-V characteristics of the diodes. However, the non-linearity in the C−2vsV curves under reverse bias was introduced by the deep donor levels. From the C-V measurements under reverse bias, two deep levels with energies of EC - (0.7 ± 0.1) eV and EC - (1.0 ± 0.1) eV were detected.

157 citations


Journal ArticleDOI
Yasuyuki Ohkura1
TL;DR: In this paper, the charge distribution at the semiconductor-insulator interface is calculated for electrons by solving Schrodinger's and Poisson's equations self-consistently for particles obeying Fermi-Dirac statistics at 300 K.
Abstract: The charge distribution at the semiconductgor-insulator interface is calculated for electrons by solving Schrodinger's and Poisson's equations self-consistently for particles obeying Fermi-Dirac statistics at 300 K. The results are applied to carriers in the channel of a crystalline MOSFET with the (100) axis perpendicular to the gate oxide. The inversion charge density calculated quantum mechanically is smaller than that calculated classically. This affects the shift of the subthreshold curves. The shift is larger at higher substrate impurity concentrations, and is especially pronounced at more than 10 17 cm −3 , which is the concentration used in recent MOS devices. The shift is as large as 0.18 V when the substrate impurity concentration is 8.5 × 10 17 cm −3 . Comparisons with measurement are also shown and it agrees well with quantum mechanical calculations. The inversion layer depth is compared, and a new efficient method is derived by transferring the quantum mechanical effect into the classical calculation. The results of this new method agree well with the quantum mechanical calculations and with the measurements.

129 citations


Journal ArticleDOI
TL;DR: In this paper, the concepts of trap charging, generation, annealing, and hydrogenation are introduced to delineate and classify the fundamental mechanisms of charging and generation of electronic or electron and hole traps located in the interfacial layers of silicon MOS transistors and integrated circuits.
Abstract: The concepts of electronic and protonic traps are introduced to delineate and classify the fundamental mechanisms of charging, generation, annealing and hydrogenation of electronic or electron and hole traps located in the interfacial (gate-conductor/oxide, oxide/nitride and oxide/silicon), insulator (oxide, nitride and oxynitride) and semiconductor surface layers of silicon MOS transistors and integrated circuits. Two matrix tables, one without tunneling (3 × 3) and one with tunneling (3 × 4) are used to classify the trap charging and electronic injection mechanisms according to the initial and final (band or bound) states of the electronic transition and the energy exchange mechanisms (thermal, optical and Auger-impact). The importance of tunneling to and from traps (TTT) as an oxide charge build-up mechanism is discussed. A theoretical tunneling rate to traps is given showing that traps shallower than about 2 eV from the oxide conduction band edge or 3 eV from the oxide valence band edge cannot be charged by the TTT transitions alone. Experimental examples illustrating the use of these mechanism tables as well as the importance of breaking hydrogen and strained intrinsic bonds by hot electron impact and by thermal hole capture are discussed, including: (i) annealing of the oxide/Si interface traps via hydrogenation during 380C chip bonding and during Fowler-Nordheim tunneling electron injection (FN-TEI) and avalanche electron injection (AEI) stresses, (ii) interface trap generation and positive oxide charge build-up during electron injection via FN-TEI or AEI, and (iii) electrical deactivation of boron and other group-III acceptors (Al, Ga, In) in the silicon surface layer during FNTEI or AEI stresses. Examples at three d.c. bias conditions to delineate the dominant degradation mechanisms in silicon MOS transistors are given showing that trap charging via tunneling (FNTEI, FNTHI and TTT) dominates below about 3.3 V in both n -MOS and p -MOS but trap generation via bond breaking by thermal hole capture may also occur in low voltage p -MOS. Higher than about 10 V, tunneling (FNTEI, FNTHI and TTT) and avalanche injection (AEI and AHI) as well as hydrogen and intrinsic bond-breaking may all be important degradation mechanisms.

125 citations


Journal ArticleDOI
TL;DR: In this article, a model based on two carrier conduction (electrons and holes) at both injecting boundaries (semiconductor bulk and gate electrode) is introduced to interpret the ERASE/WRITE characteristics of scaled SONOS devices.
Abstract: In this paper, a model based on two carrier conduction (electrons and holes) at both injecting boundaries (semiconductor bulk and gate electrode) is introduced to interpret the ERASE/WRITE characteristics of scaled SONOS devices. The amphoteric statistics describe the positive and negative charging of the deep-level traps in the nitride “memory” layer. Scaled SONOS/MONOS (polysilicon-oxide-nitride-oxide-semiconductor)/(metal-oxide- nitride-oxide-semiconductor) transistors and capacitors with the bottom (‘tunnel’) oxide layer thickness around 20 A, the final nitride layer thickness below 100 A, and the top (‘blocking’) oxide layer thickness between 35–50 A, have been fabricated and characterized. The results of the model are consistent with the experimental data, which permits physical insight into the mechanisms of charge injection, transport and storage during the ERASE/WRITE operation. Lattice imaging electron microscopy (TEM), ellipsometry, electrical capacitance, and chemical etchback techniques have been used to determine scaled SONOS/MONOS material parameters. The linear voltage ramp technique, which simultaneously measures the flatband voltage shift and separates the charges at the injecting boundary, and the dynamic pulse techniques of flatband tracking and threshold monitoring, which measure ERASE/WRITE, retention and endurance operations, have been employed to electrically characterize the scaled SONOS/MONOS devices. We have demonstrated a differential, saturated ERASE/WRITE flatband shift of 3.8 V with a ±5 V programming voltage for scaled-down SONOS/MONOS devices with dimensions of 20 A for the tunnel oxide, 50 A for the nitride, and 35 A for the blocking oxide. With ±5 V saturated ERASE/WRITE programming voltages and 10 6 ERASE/WRITE cycles, extrapolated retention gives a projected 10 year 0.5 V memory window at room temperature.

110 citations


Journal ArticleDOI
TL;DR: The paper reviews the evolution of the mobility model of the MINIMOS program for the two-dimensional simulation of miniaturized MOS devices over a period of 10 years.
Abstract: The paper reviews the evolution of the mobility model of the MINIMOS program for the two-dimensional simulation of miniaturized MOS devices over a period of 10 years.

89 citations


Journal ArticleDOI
TL;DR: In this article, a general analytical model for the 1-dimensional MISIS (metal-insulator-semiconductor-inulator-semiconductor) structure which occurs in SOI MOS devices is presented.
Abstract: A general analytical model is presented for the 1-D MISIS (metal-insulator-semiconductor-insulator-semiconductor) structure which occurs in SOI MOS devices. The model takes into account inversion, depletion and accumulation layer widths in both semiconductor regions, fixed isolator charges as well as interface trap charges. The model is compared with numerical simulations and shows very good agreement. Finally, it is applied for calculating the threshold voltage and the subthreshold slope in SOI n MOS transistors and is proven to be superior to conventional analytical models, especially in the thin film regime.

68 citations


Journal ArticleDOI
TL;DR: In this article, a model in which there is a range of barriers with a normal distribution was introduced, and the photoyield was calculated using the photo-emission model.
Abstract: Current-voltage-temperature ( I - V - T ) characteristics of p -type moderately doped PtSi Schottky barrier diodes have been measured as a function of temperature from 77 to 120 K. From thermionic emission theory, the saturation current at each temperature is plotted against inverse temperature. According to this theory, the slope should give the barrier height. However, the experimental data obtained do not correlate well with a straight line relationship. These effects are explained by introducing a model in which there is a range of barriers with a normal distribution. A mean barrier of 0.242 eV with a standard deviation of σ = 0.011 eV is obtained. Photoresponse measurements have also been performed at a temperature of 78.0 K to verify the I - V - T results and to test the distributed model. It is found that the cut-off wavelength for PtSi Schottky diodes is well beyond that predicted by a single barrier, giving further evidence for multiple barriers. To test the distributed model, the parameter extracted from the model, i.e. the spread of the barrier, σ is introduced into the photoemission model. The photoyield thereby calculated compares well with experimental results.

64 citations


Journal ArticleDOI
David D. Nolte1
TL;DR: In this article, a comparison of the average dangling bond energy between InP and GaAs was made to determine the location of the maximum density of surface states in the bandgap and control the formation of native amphoteric defects which compensate shallow dopants.
Abstract: Surface recombination and free-carrier saturation both influence the performance and scaling of bipolar semiconductor devices. These two apparently unrelated material properties have a common origin in the band structure of the semiconductor. Although InP and GaAs have similar bandgaps as well as similar effective masses and dielectric constants, InP has dramatically different surface recombination velocities and free-carrier saturation limits than GaAs. These differences can be explained by a single comparison of the average dangling bond energy in the two materials. The dangling bond energy determines the location of the maximum density of surface states in the bandgap and controls the formation of native amphoteric defects which compensate shallow dopants. Semiquantitative predictions based on this principle are presented for InGaAsP/InP.

60 citations


Journal ArticleDOI
TL;DR: In this article, a Gummel-Poon model for abrupt and graded GaAlAs/GAAs/GaAs heterojunction bipolar transistors (HBTs) is developed.
Abstract: A Gummel-Poon model for abrupt and graded GaAlAs/GaAs/GaAs heterojunction bipolar transistors (HBTs) is developed. The effect of carrier recombination at the emitter-base heterojunction, space charge region (SCR) width modulation effect, and base-widening effect at large collector currents have been considered. Results from this model are compared with numerical results, experimental results, and results from the most recent analytical models. The results show that the common-emitter current gain behavior in the low collector current region can be predicted more accurately by this model, and that interface and surface recombination affect the current gain more dominantly than the other recombination processes. Dependence of cutoff frequency on collector current obtained from the present model agrees well with the experimental results. This model can also predict both current gain and cutoff frequency falloffs at large collector current. This model can be easily implemented in the SPICE program.

Journal ArticleDOI
TL;DR: In this paper, it was shown that the original formulation of Ramo's theorem is still valid in the presence of a space charge and the generalized version of this theorem was proved to be wrong.
Abstract: It is shown that the original formulation of Ramo's theorem is still valid in the presence of a space charge. The generalized version of this theorem which has been around for a very long time, is proved to be wrong. The consequences for the theories of semiconductor detectors and generation-recombination noise in p-n junctions are described.

Journal ArticleDOI
TL;DR: In this paper, a new approach for simulating carrier transport in semiconductor devices is proposed and demonstrated by dividing a device into a number of small elements and defining scattering matrices, which relate the fluxes incident upon each element to the emerging fluxes.
Abstract: A new approach for simulating carrier transport in semiconductor devices is proposed and demonstrated. The approach begins by dividing a device into a number of small elements and defining scattering matrices, which relate the fluxes incident upon each element to the emerging fluxes. By cascading the scattering matrices for each element, carrier transport through the entire device is simulated. When the scattering matrices are computed by solving the Boltzmann equation, low-, high- and nonstationary transport effects can be simulated, but the scattering matrix may also be computed from a wave perspective to treat quantum interference effects within a slab. The ability of this new approach to treat sophisticated transport effects in modern devices is demonstrated by simulating high-field transport in bulk silicon and nonstationary transport in a submicron silicon structure.

Journal ArticleDOI
TL;DR: In this article, the effects of heavy impurity doping on material parameters important for GaAs-based bipolar devices are examined, and the significant uncertainties and characterization needs that remain are identified, and parameteric fits to the measured results are presented when appropriate.
Abstract: Heavy impurity doping perturbs the energy-band structure of GaAs thereby influencing both the optical and electrical properties of devices. This paper examines the effects of heavy doping on material parameters important for GaAs-based bipolar devices. A broad range of experimental work directed at characterizing the doping-dependent equilibrium np product, minority carrier mobility, and minority carrier lifetime is reviewed. To facilitate device modeling, parameteric fits to the measured results are presented when appropriate. Implications for devices are then considered, and shown to be strong. Finally, the significant uncertainties and characterization needs that remain are identified.

Journal ArticleDOI
TL;DR: In this article, a model of charge transport and trapping in therml SiO2 implanted with Si is presented, which gives a comprehensive representation of the physical mechanisms associated with Si implant-induced trapping sites.
Abstract: A model of charge transport and trapping in therml SiO2 implanted with Si is presented. The model gives a comprehensive representation of the physical mechanisms associated with Si implant-induced trapping sites in SiO2 and describes most of the effects experimentally observed in this material.

Journal ArticleDOI
TL;DR: In this article, a semi-empirical approach for modeling of ion-implanted impurity distributions has been proposed, which is based on the use of two Pearson functions describing two scattering mechanisms encountered in ion implantation into single-crystal silicon.
Abstract: A semi-empirical approach for modeling of ion-implanted impurity distributions has an inherent advantage of high computational efficiency which is a vital issue for the simulation of a large number of processing steps required in the fabrication of high density integrated circuits with submicrometer feature sizes. The accuracy of this modeling technique has been substantially improved with the introduction of the dual Pearson modeling approach for simulation of implanted impurity distributions in single-crystal silicon so that the entire profile, including the broad channeling tail, is accurately predicted[1]. The dual Pearson modeling approach is based on the use of two Pearson functions describing two scattering mechanisms encountered in ion implantation into single-crystal silicon. Since semi-empirical approaches are based on experimental data, it is crucial to maintain a sizable data base of modeling parameters extracted from measured profiles in order to fully exploit the advantages of semi-empirical approaches. In this paper, a computer program which extracts all nine parameters for the dual Pearson modeling approach will be introduced. This program provides an easy and efficient way of extracting very accurate parameters in a two-step extraction process. The first step obtains a preliminary set of nine parameters which is then used as the initial condition for the second step in which the Levenberg-Marquardt algorithm is used to find the final set of accurate parameters. The incorporation of the first step for self-generation of the initial conditions makes the program easy to use, even for those with no previous experience with Pearson functions or the curve-fitting processes.

Journal ArticleDOI
TL;DR: In this paper, a new method for measuring the threshold voltage of small geometry MOS devices is presented, based on the drain current equation in the sub-threshold region, defined as the gate voltage required for a surface band-bending of 2 φ F, can be accurately determined experimentally by the Quasi-Constant Current (QCC) method.
Abstract: A new method for measuring the threshold voltage of small geometry MOS devices is presented. Based on the drain current equation in the subthreshold region, the threshold voltage ( V TH ), defined as the gate voltage required for a surface band-bending of 2 φ F , can be accurately determined experimentally by the Quasi-Constant-Current (QCC) method. Compared with some other commonly used methods, this technique has the advantages of better fitting accuracy in subthreshold region, extracting the V TH with a unique value, and being suitable for small geometry devices over a wide range of voltage biases, temperatures, and process parameter variations. It can be used either for circuit simulation like the MOS3 model in SPICE, or as a routine monitor of processing like channel doping profile, gate oxide thickness or source and drain junction depths.

Journal ArticleDOI
TL;DR: In this article, the authors investigated the effect of interface traps on MOS transistor characteristics using a sheet charge model and showed that the interface states are located within a 0.5 nm thick layer of SiO 2.
Abstract: Interface traps due to excess Si introduced into the SiSiO 2 system by ion implantation are investigated. Implanted oxides are shown to have interface traps at or slightly above the Si conduction band edge with densities proportional to the density of off-stoichiometric Si at the SiSiO 2 interface. Diluted oxygen annealing is shown to result in physical separation of interface traps and equilibrium substrate electrons, demonstrating that “interface” states are located within a 0.5 nm thick layer of SiO 2 . Possible charge trapping mechanisms are discussed and the effect of these traps on MOS transistor characteristics is described using a sheet charge model.

Journal ArticleDOI
TL;DR: In this article, a study of flicker noise in MOS transistors operated in the linear and non linear regions at room and liquid helium temperatures is proposed, and a theoretical analysis of the drain current noise characteristics is developed in the framework of the mobility fluctuation model as well as of the carrier number fluctuation models.
Abstract: A study of flicker noise in MOS transistors operated in the linear and non linear regions at room and liquid helium temperatures is proposed. Besides, a theoretical analysis of the drain current noise characteristics is developed in the framework of the mobility fluctuation model as well as of the carrier number fluctuation model. It is shown experimentally that a close correlation between the drain current spectral density and the transconductance squared dependencies with gate voltage (or drain current) and drain voltage is observed in our devices both at room and liquid helium temperatures. Therefore, it is concluded that the carrier number fluctuation model is not only applicable to MOS devices operated at room temperature but also at liquid helium temperature in ohmic and non ohmic regimes. In addition, peculiarities of the drain current noise related to the appearance of a kink effect at liquid helium temperature in the saturation current characteristics are also discussed.

Journal ArticleDOI
TL;DR: In this article, a simple physical model describing conductivity modulation effects under high level injection is derived for Schottky barrier diodes with long drift regions, where the electron and hole carrier profiles, current densities, electric field, voltage drop and the amount of stored charge as a function of the total current density are presented.
Abstract: The J - V characteristics of Schottky barrier diodes with long drift regions are discussed in this paper. A simple physical model describing conductivity modulation effects under high level injection is derived. Solution for the electron and hole carrier profile, current densities, electric field, voltage drop and the amount of stored charge as a function of the total current density is presented. An empirical model which spans low and high injection levels is also proposed. The model uses the traditional formula for low injection condition and switches gradually to the high level injection model derived here when the amount of minority carrier injection becomes appreciable. The validity of the complete model is verified by comparison with simulated and experimental results.

Journal ArticleDOI
TL;DR: In this paper, an overview of the types of problems encountered in semiconductor technology development that are actively studied today via simulation methods is presented, including process simulations, such as the diffusion of dopant atoms, oxidation, etching, deposition, and epitaxial growth, and device simulations, which predict the flow of charge carriers and field distribution within a semiconductor device, given its material structure and operating conditions.
Abstract: An overview is presented on the types of problems encountered in semiconductor technology development that are actively studied today via simulation methods Most of the simulation examples presented here are ones that have been explicitly used in actual industrial semiconductor device design cycles to aid in the optimization of device structures The examples described here include process simulations, such as the diffusion of dopant atoms, oxidation, etching, deposition, and epitaxial growth, as well as device simulations, which predict the flow of charge carriers and field distribution within a semiconductor device, given its material structure and operating conditions The main aim here is to illustrate, by example, some of the capabilities of state-of-the-art simulators used in characterizing and predicting semiconductor process and device-related phenomena We will attempt to outline the degree of sophistication of the physics incorporated in such simulation programs, and provide some contrast to the fundamental physics required for a complete physical description As will be indicated, simulation development necessarily involves molding the appropriate physical models and numerical algorithms into a package that can be handled in a reasonable length of time by modern computing systems We briefly outline some of the advances that have been made, and some concerns that remain, in such simulation development

Journal ArticleDOI
TL;DR: In this paper, it was shown that the kink in the drain current ID can be interpreted as a switching from a high to a low threshold voltage Vt, which corresponds with an increase in the well potential VBS of about 1.1 V, i.e. the voltage of the source diode.
Abstract: From a detailed investigation of nMOST characteristics at liquid helium temperatures (T < 40 K), it is inferred that the kink in the drain current ID can be interpreted as a switching from a high to a low threshold voltage Vt. The low Vt state corresponds with an increase in the substrate (well) potential VBS of about 1.1 V, i.e. the “on” voltage of the source diode. This increase is caused by the space charge limited flow of the substrate current IB through the well impedance. Based on these observations a simple, one-dimensional analytical model is constructed, relating the kink amplitude δID to the square root of IB. From this model, the influence of device dimensions, well/substrate contact separation and temperature T on the kink is derived. As will be shown, other mechanisms like the “forced depletion layer formation” contribute to the kink/hysteresis behaviour, especially at temperatures below 10 K.

Journal ArticleDOI
TL;DR: In this paper, the authors demonstrate that the impedance of the p - i - n diode is definable as a function of frequency and depends on the diode's geometry and electronic properties.
Abstract: The purpose of this paper is to demonstrate that the impedance of the p - i - n diode is definable as a function of frequency and depends on the diode's geometry and electronic properties. The impedance analysis includes the effects of different electron and hole mobilities, making the model suitable for modeling the a.c. impedance of both silicon and gallium arsenide - i - n diodes. The small signal model shows that for frequencies near the inverse of the intrinsic region carrier lifetime, the diode shows either capacitive or inductive reactance, depending on its geometry. The analysis also indicates that p - i - n diodes with certain combinations of geometry and carrier lifetime show a nearly constant resistance and negligible reactance at all frequencies. At high frequencies for p - i - n diodes of any geometry, the reactive component essentially disappears and the impedance is purely resistive. The series equivalent p - i - n diode impedance model is compared with measured impedance vs frequency data for both silicon and gallium arsenide - i - n diodes.

Journal ArticleDOI
TL;DR: In this article, the tunnelling current was treated in a more rigorous manner by considering the position-dependent electric field in the space charge region, rather than treating the electric field as a constant as that in the conventional approach.
Abstract: In this paper we treat the tunnelling current in a more rigorous manner by considering the position-dependent electric field in the space-charge region, rather than treating the electric field as a constant as that in the conventional approach [eqn (1)]

Journal ArticleDOI
TL;DR: In this paper, a generalized application to the determination of material properties for device models is proposed, leading to the principle of inverse modelling, and a step profile is presented to show the reduced noise sensitivity of the inverse modelling method as compared to that of the traditional CV method; also more accurate results are obtained because the abrupt depletion approximation is not required.
Abstract: Semiconductor device simulations require valid physical input parameters for their results to be adequate. The technique of parameter extraction by error minimization has up till now almost exclusively been applied to analytical models for circuit simulations. A generalized application to the determination of material properties for device models is proposed, leading to the principle of inverse modelling. As an example application, the nondestructive determination of doping profiles from electrical measurements is discussed. A step profile is presented to show the reduced noise sensitivity of the inverse modelling method as compared to that of the traditional CV method; also, more accurate results are obtained because the abrupt depletion approximation is not required. As a second example, the complete profile in a Junction Charge-Coupled Device has been determined to illustrate the possibility of two-dimensional doping profiling. The application range of inverse device modelling is not limited to doping profiling; further application to MOSFET channel mobility determination is proposed. The advantages and disadvantages of inverse modelling as compared to tradiational methods are investigated.

Journal ArticleDOI
TL;DR: In this paper, an analytical model is developed for the I-V characteristics of a normally off bipolar-mode FET structure, which is based on the physical picture obtained by a detailed two-dimensional numerical simulation.
Abstract: On the basis of the physical picture obtained by a detailed two-dimensional numerical simulation, an analytical model is developed for the I-V characteristics of a normally-off bipolar-mode FET structure. The numerical results show that the device has basically two modes of operation. When the minority-carrier injection from the gate is negligible, the device operation is governed by the modulation of the potential barrier in the channel due to the gate and drain voltages. This gives rise to an exponential shape of the I-V characteristics in the subthreshold regime, while for larger drain currents a transition to a triodelike shape takes place. The second mode of operation is due to the injection of minority carriers from the gate. This bipolar mode of operation is modeled according to a regional approximation method. The limits of the proposed quasi one-dimensional analysis are discussed by comparisons with the two-dimensional numerical results. The comprehensive analytical model obtained gives results in very good agreement with the numerical simulations and can be used to assess the influence of the various geometrical and physical parameters on the performances of the device.

Journal ArticleDOI
TL;DR: In this paper, the authors used dielectric spectroscopy of semiconductors (DSS) to characterize the energy depth of localised levels, the nature of the various transition rates and the interactions between the localised carriers and the lattice.
Abstract: The measurement of delayed electronic transitions in semiconductors by the technique of Dielectric Spectroscopy of Semiconductors (DSS) constitutes an effective means of characterising materials. The advantage of DSS in comparison with other static techniques consists in the availability of a large range of times or frequencies—typically several decades—which characterise the rate processes prevailing in the materials under study and thus reveal features which may not be accessible by more commonly used static techniques. The results give information about the energy depth of localised levels, about the nature of the various transition rates and also about the interactions between the localised carriers and the lattice, which are not easily measured by other techniques. They are relevant to the assessment of p−n junctions and also of the interfacial layers in Schottky barriers.

Journal ArticleDOI
TL;DR: In this paper, analytical solutions for the breakdown voltage of cylindrical junctions terminated with a single, optimally placed, floating field ring are presented in a normalized form which allows calculation of breakdown voltage over a broad range of junction depths and background dopings.
Abstract: Analytical solutions for the breakdown voltage of cylindrical junctions terminated with a single, optimally placed, floating field ring are presented. These solutions are provided in a normalized form which allows calculation of the breakdown voltage over a broad range of junction depths and background dopings. In addition, an equation for the optimal spacing of the field ring has been derived. This allows determination of the optimal spacing for the first time without resorting to numerical analysis for each specific case.

Journal ArticleDOI
TL;DR: In this paper, the authors present an approche permettant une interpretation du spectre dielectrique de tous les materiaux semiconducteurs, which correspond a dependance temporelle exponentielle.
Abstract: Etude dynamique des transitions de piegeage par les niveaux profonds dans les regions de charge d'espace des jonctions p-n et des diodes de Schottky. Les resultats mettent en evidence un ecart par rapport a la forme ideale de Debye qui correspond a une dependance temporelle exponentielle. Proposition d'une nouvelle approche permettant une interpretation du spectre dielectrique de tous les materiaux semiconducteurs

Journal ArticleDOI
TL;DR: In this paper, a new set of hydrodynamic conservation equations, expressing balance of momentum and energy in a particular conduction band valley of GaAs, is derived, and it is demonstrated that the equations represent a generalization of Blotekjaer's popular balance equations, in that nonparabolicity and non-placed-Maxwellian distributions are fully accounted for.
Abstract: A new set of hydrodynamic conservation equations, expressing balance of momentum and energy in a particular conduction band valley of GaAs, is derived It is demonstrated that the equations represent a generalization of Blotekjaer's popular balance equations, in that nonparabolicity and nondisplaced-Maxwellian distributions are fully accounted for Results of Monte Carlo simulations, in which electrons are subjected to approximately 100 kV/cm, sharply peaked one-dimensional electric fields, are presented Inclusion of nonparabolicity in the Γ valley of GaAs is shown to change the magnitude of the momentum equation's diffusion terms by up to 50% Rapid transfer of electrons out of the Γ valley via Γ - L transitions is shown to result in an effective diffusion “force” that equals or exceeds the drift force, even under very high field conditions