Showing papers in "Solid-state Electronics in 1996"

Status of silicon carbide (SiC) as a wide-bandgap semiconductor for high-temperature applications: A review

Abstract: Silicon carbide (SiC), a material long known with potential for high-temperature, high-power, high-frequency, and radiation hardened applications, has emerged as the most mature of the wide-bandgap (2.0 eV ≲ Eg ≲ 7.0 eV) semiconductors since the release of commercial 6HSiC bulk substrates in 1991 and 4HSiC substrates in 1994. Following a brief introduction to SiC material properties, the status of SiC in terms of bulk crystal growth, unit device fabrication processes, device performance, circuits and sensors is discussed. Emphasis is placed upon demonstrated high-temperature applications, such as power transistors and rectifiers, turbine engine combustion monitoring, temperature sensors, analog and digital circuitry, flame detectors, and accelerometers. While individual device performances have been impressive (e.g. 4HSiC MESFETs with fmax of 42 GHz and over 2.8 W mm−1 power density; 4HSiC static induction transistors with 225 W power output at 600 MHz, 47% power added efficiency (PAE), and 200 V forward blocking voltage), material defects in SiC, in particular micropipe defects, remain the primary impediment to wide-spread application in commercial markets. Micropipe defect densities have been reduced from near the 1000 cm−2 order of magnitude in 1992 to 3.5 cm−2 at the research level in 1995.

Ordered arrays of quantum dots: Formation, electronic spectra, relaxation phenomena, lasing

Abstract: Elastic relaxation on facet edges, renormalization of the surface energy of the facets, and interaction between i&no3 via the strained substrate are the driving forces for self-organization of ordered arrays of uniform coherent three-dimensional is/a& on crystal surfaces. For a (100) surface of a cubic crystal, two-dimensional square lattice of pyramid-like islands (quantum dots) with the periodicity along the directions of the lowest stiffness (OlO) and (OOI) has the minimum energy among different one-dimen- sional and two-dimensional arrays. For the InAs/GaAs(lOO) system, an equilibrium array of dots of the lateral size _ 120-140 A exists in a fixed range of growth parameters. T'he main luminescence peak at 1.1 eV, as well as peaks of excited states coincide in energy with the peaks revealed in the calorimetric absorption spectra regardless of the amount of InAs deposited (2-5 ML). Raman spectra indicate significant strain in InAs dots. The "phonon bottleneck" effect is bypassed via multi-phonon exciton and carrier relaxation. Ultranarrow lines (< 0.15 meV) are observed in cathodoluminescence spectra up to high temperatures. Low threshold current density operation via zero-dimensional states and ultrahigh temperature stability of the threshold current (T, = 450 K) are realized for a quantum dot injection laser. Increase in the gain and significant reduction in the radiative lifetime are possible via the self-organization of vertically-coupled quantum dots (VECODs) arranged in a well ordered artificial three-dimensional tefragonal lattice.

BARRIER CHARACTERISTICS OF PtSi/p-Si SCHOTTKY DIODES AS DETERMINED FROM I-V-T MEASUREMENTS

Abstract: The current-voltage-temperature characteristics of PtSi/p-Si Schottky barrier diodes were measured in the temperature range 60–115 K. Deviation of the ideality factor from unity below 80 K may be modelled using the so-called T0 parameter with T0 = 18 K. It is also shown that the curvature in the Richardson plots may be remedied by using the flatband rather than the zero-bias saturation current density. Physically, the departure from ideality is interpreted in terms of an inhomogeneous Schottky contact. Here we determine a mean barrier height at T = 0 K, ƒ b 0 = 223 mV , with an (assumed) Gaussian distribution of standard deviation σ ƒ = 12.5 mV . These data are correlated with the zero-bias barrier height, ƒ j 0 = 192 mV (at T = 90 K), the photoresponse barrier height, ƒ ph = 205 mV , and the flatband barrier height, ƒ fb = 214 mV . Finally, the temperature coefficient of the flatband barrier was found to be −0.121 mVK−1, which is approximately equal to 1 2 (dE g i /dT) , thus suggesting that the Fermi level at the interface is pinned to the middle of the band gap.

Mosfet carrier mobility model based on gate oxide thickness, threshold and gate voltages

Abstract: The widely accepted universal dependence of N- and P-MOSFETs carrier mobility on effective vertical field E eff = (ηQ inv + Q b ) ϵ Si has been re-examined. New empirical mobility models for both electrons and holes expressed in terms of Tox, Vt and Vg explicitly are formulated. New empirical mobility models are confirmed with experimental data taken from devices of different technologies. It is also shown that the hole mobility of both the surface and buried channel P-MOSFETs can be unified for the first time by a single universal mobility equation, rather than two separate equations as previously thought necessary.

A model for specific contact resistance applicable for titanium silicide-silicon contacts

Abstract: An analytical model is presented for the specific contact resistance and shown to be applicable for metal-semiconductor contacts consisting of titanium silicide (TiSi2) on n and p-type silicon. The model includes the influence of field emission and thermionic-field emission in a unified manner, requiring only one simple relation for determination of specific contact resistance when either of these conduction mechanisms dominates. Previously, depending on field emission or thermionic-field emission dominating, separate analytical models, consisting of different relations for the specific contact resistance, have been derived. Moreover, these derivations generally have resulted in rather complex expressions, with complicated terms that are not readily amenable for easy analysis and physical understanding. The present model, while simpler in form, captures the main elements affecting specific contact resistance as influenced by thermionic-field emission and field emission and compares well with experimental results for TiSi2Si contacts. The model is also applicable for other metal-semiconductor contacts, and has been used to generate theoretical curves for specific contact resistance doping concentration, for a range of barrier heights, for metal-silicon contacts. Moreover, due to its simpler form, this model may be conveniently used for extracting model parameters from experimental data, if necessary and it can be easily implemented and used in process and/or device simulation programs.

Effect of series resistance on the forward current-voltage characteristics of Schottky diodes in the presence of interfacial layer

Abstract: In order to make an accurate determination of Schottky diode parameters such as the ideality factor, the barrier height and the series resistance [using forward current-voltage ( I - V ) characteristics in the presence of an interfacial layer], a novel calculation method has been developed by taking into account the applied voltage drop across the interfacial layer ( V i ). The parameters obtained by accounting for the voltage drop V i have been compared with those obtained without considering the above voltage drop. To examine the consistency of this approach, the comparison has been made by means of Schottky diodes fabricated on a n -type semiconductor substrate with different bulk thickness. It is shown that the voltage drop across the interfacial layer will increase the ideality factor and the voltage dependence of the I - V characteristics. In addition, it is shown that the series resistance value increases as the semiconductor bulk thickness has been increased.

Physical models of ohmic contact for Monte Carlo device simulation

Abstract: This paper investigates the problem of modelling ohmic contacts for Monte Carlo simulation of semiconductor devices. Several models are proposed with different velocity distributions for the injected carriers. The influence of each model on the device physics near the contact is discussed. As a prototype for this analysis we investigate the role of the ohmic contact on the electrical characteristics of a GaAs Schottky-barrier diode under forward-bias condition. To get accurate results from the simulations of this device, correct modelling of the ohmic contact is crucial. We have found that the best simulation of the carrier dynamics near the contact is achieved by using a velocity-weighted Maxwellian distribution for injecting the carriers, which provides flat profiles of the different magnitudes near the boundary and a zero voltage drop at the contact. In addition, an appropriate time and space algorithm for carrier injection must be applied.

Silicon carbide MOSFET technology

Abstract: The research and development activities carried out to demonstrate the status of MOS planar technology for the manufacture of high temperature SiC ICs will be described. These activities resulted in the design, fabrication and demonstration of the world's first SiC analog IC—a monolithic MOSFET operational amplifier. Research tasks required for the development of a planar SiC MOSFET IC technology included: characterization of the SiCSiO2 interface using thermally grown oxides; high temperature (350°C) reliability studies of thermally grown oxides; ion implantation studies of donor (N) and acceptor (B) dopants to form junction diodes; epitaxial layer characterization; device isolation methods; and finally integrated circuit design, fabrication and testing of the world's first monolithic SiC operational amplifier IC. High temperature circuit drift instabilities at 350°C were characterized. These studies defined an SiC depletion model MOSFET IC technology and outlined tasks required to improve all types of SiC devices.

A new analytical method of solving 2D Poisson's equation in MOS devices applied to threshold voltage and subthreshold modeling

Abstract: In this paper we present a new theoretical approach in MOS modeling to derive analytical, physics-based model equations for the geometry and voltage dependence of threshold voltage and for the subthreshold behavior of short-channel MOSFETs. Our approach uses conformal mapping techniques to analytically solve the two-dimensional Poisson equation, whereby inhomogeneous substrate doping is taken into account. The presented model consists of analytical equations in closed form and uses only physically meaningful parameters. Therefore, the results are not only useful in circuit simulators but also in calculations of scaling behavior, where planned processes can be investigated. Comparison with numerical device simulation results and measurements confirm the high accuracy of the presented model.

A silicon-on-insulator quantum wire

Abstract: Thin, narrow silicon-on-insulator n-channel MOSFETs have been fabricated. The drain current characteristics, when measured as a function of gate voltage at low temperature, exhibit a series of oscillations, which is characteristic of current transport in one-dimensional systems (quantum wires). Theoretical calculation of the current oscillations in the device show reasonable agreement with the experimental characteristics.

Modelling and application of fully depleted SOI MOSFETs for low voltage, low power analogue CMOS circuits

Abstract: Transistor models which reproduce the superior device characteristics of fully depleted silicon-on-insulator (SOI) MOSFETs and which are efficient for the design of analogue CMOS circuits are discussed and validated. These analogue models are then used to investigate the significant performance improvement that several basic analogue cells can achieve when optimized in fully depleted SOI CMOS, rather than in bulk CMOS technology. Experimental verifications support this original demonstration of the great potential of fully depleted SOI CMOS for low voltage, low power analogue applications.

High barrier metallic polymer/p-type silicon schottky diodes

Abstract: A metallic polypyrrole film has been formed on a p-type Si substrate by means of an anodization process An investigation of the formed polymer/pSi Schottky diodes has been made The polypyrrole polymer provides a good rectifying contact to the p-Si semiconductor The current-voltage (barrier height Φb0 = 084 eV) and capacitance-voltage (Φb0 = 094 eV) characteristics of the devices are significantly improved with increasing Φb0 and decreasing the ideality factor (n = 120) after a polymer melt processing step These values of Φb0 are significantly larger than those of conventional Schottky diodes Furthermore this study shows that owing to its room temperature processing the high barrier-metallic polypyrrole/pSi structures can be useful for deep level characterisation of p-Si

Hot-carrier-induced degradation in ultra-thin-film fully-depleted soi MOSFETs

Abstract: The charge-pumping measurement technique was successfully applied to submicron ( L eff = 035 μm) n-MOSFETs on ultra-thin (50 nm) SOI film The hot-carrier-induced degradation is studied by examining the damages to both gate-oxide and buried-oxide (BOX) interfaces We found that when stressed at maximum substrate current, interface-trap generation is still the primary cause for hot-carrier-induced degradation Even for ultra-thin-film SOI devices, the hot-carrier-induced damage is locally confined to the gate-oxide interface and only minor damage is observed at the buried-oxide interface The buried-oxide interface charging contributes less than 5% of the overall drain current degradation

The low-frequency noise behaviour of silicon-on-insulator technologies

Abstract: In this overview, the low-frequency noise behaviour of devices fabricated in silicon-on-insulator technologies is described. The different potential noise sources are analysed and illustrated by experimental results, mainly obtained on MOSFETs. Some SOI-specific noise behaviour is highlighted, as for instance the kink-related excess low-frequency noise overshoot. It is shown furthermore that SOI MOSFETs suffer from so-called random telegraph signals, which can originate from the front- or the back-gate dielectric, or from defects located in the thin Si active layer. The impact of the substrate type (SIMOX, bonded, ZMR,…) is discussed. At the same time, it is shown that the used technology and device structure can have a pronounced effect on the LF noise performance. Finally, the response of SOI MOSFETs on ionizing radiation (γs, X-rays,…) is studied through the LF noise degradation, in view of radiation-hardened applications.

Thermally stable low ohmic contacts to p-type 6HSiC using cobalt silicides

Abstract: Cobalt silicide (CoSi2) ohmic contacts possessing low specific contact resistivity (pc Co SiC contact structure subjected to an identical annealing process revealed higher pc and a modified sheet resistance requiring a different method of contact parameter extraction.

Analytical study of the contribution of fast and slow oxide traps to the charge pumping current in MOS structures

Abstract: An analytical expression of the charge pumping (CP) current in a MOS device is derived for fast and slow interface traps, after assuming short gate bias transition times and neglecting the emission of carriers In the case of fast interface traps, this simple CP formulation enables a good description of the charge pumping characteristics for general purpose CP configurations It is used to demonstrate the influence of the doping concentration on the CP characteristics It is also shown that the slow oxide traps induce a recombination current which can be of the same order of magnitude compared to that due to the fast interface traps The characteristics of this current are discussed in terms of the trap parameters In the case of a continuum of volume oxide traps, the apparent interface trap density, which is measured in the conventional CP technique, is also investigated and discussed for state-of-the-art MOS structures

An instrumental solution to the phenomenon of negative capacitances in semiconductors

Abstract: A number of authors make reference to “negative capacitances” observed during impedance measurements of metal-semiconductor and other semiconductor device structures at sufficiently low frequencies for parasitic inductances to be assumed negligible. Often, these negative capacitances are attributed to physical phenomena associated with the devices being measured. It is demonstrated in this paper that many such interpretations incorrectly neglect the importance of parasitic series inductances at low frequencies when device conductance is large, as in a forward biased Schottky barrier, or when large device leakage currents are present. Simulations of experimental data for a Schottky diode show that typical values of probe lead and other instrumental inductance may be sufficient to provide an instrumental explanation for the apparent effect.

Visible light emitting SiSiO2 superlattices

Abstract: Six-period superlattices of Si SiO 2 have been grown at room temperature using molecular beam epitaxy. With this mature technology, the ultra-thin (1–3 nm) Si layers were grown to atomic layer precision. These layers were separated by ∼1 nm thick SiO2 layers whose thickness was also well controlled by using a rate-limited oxidation process. The chemical and physical structures of the multilayers were characterized by cross-sectional TEM, X-ray diffraction, Raman spectroscopy, Auger sputter-profile, and X-ray photoelectron spectroscopy. The analysis showed that the Si layer is free of impurities and is amorphous, and that the SiO 2 Si interface is sharp (∼0.5 nm). Photoluminescence (PL) measurements were made at room temperature using 457.9 nm excitation. The PL peak occurred at wavelengths across the visible range for these multilayers. The peak energy position E was found to be related to the Si layer thickness d by E (eV) = 1.60+0.72d−2 in accordance with a quantum confinement mechanism and the bulk amorphous-Si band gap.

A comparison of the kink effect in polysilicon thin film transistors and silicon on insulator transistors

Abstract: Polysilicon thin film transistors (TFTs) differ from conventional silicon on insulator (SOI) transistors in that the TFT exhibits a fundamental gate length dependence of the voltage at which a kink occurs in the output characteristics. This difference is shown to be caused by the peak lateral electric field being strongly dependent on the doping density in an SOI transistor, but relatively insensitive to trap distribution in a TFT. Source barrier lowering which occurs in SOI transistors is absent in a TFT, where the increase in current is the result of a field redistribution along the channel. For very short gate lengths, the TFT exhibits a small pseudo-bipolar gain. Estimates of this bipolar gain can be made by simulation of TFT characteristics with and without impact ionisation. The magnitude of the gain is shown to be approximately inversely proportional to gate length.

Capacitance technique for the determination of interface state density of metal-semiconductor contact

Abstract: A capacitance technique to determine the interface state density of metal—semiconductor contact is developed which takes care of interfacial oxide layer and series resistance of the device. The technique is applied to Pt- and Co-nSi contacts, and the energy distributions of interface state density are determined. For both devices, the distribution is found to be initially flat, then increasing sharply with energy.

High frequency characteristics and modelling of p-type 6H-silicon carbide MOS structures

Abstract: This paper presents the high frequency electrical characteristics and modelling of Al/SiO 2 / p -type 6HSiC structures. The oxide was thermally grown under dry conditions. Capacitance and conductance vs bias and frequency measurements have been performed in daylight and exposing the capacitors to u.v. light. The experimental C m - V g and G m - V g characteristics show hysteresis effects, which are more important when the samples are exposed to 254 nm u.v. light. This behaviour can be explained in terms of interface traps. The MOS structure modelling is based on an interface trap model in which the interface trap levels are considered to be continuously distributed in the SiC bandgap and only charge exchange between interface trap levels and the SiC bands is allowed. From this formulation and from the G m - f characteristics, the interface state density and the interface trap time constant have been determined.

Formation of Si quantum dots in nanocrystalline silicon

Abstract: Amorphous Si (a-Si) thin films deposited on Si(110) substrates were crystallized by using rapid thermal annealing. From structural investigations using X-ray diffraction (XRD) and cross-sectional transmission electron microscopy (TEM) we find that this crystallization is a two step process. In a first step single crystalline needles having a thickness of 1–2 nm grow in 〈111〉 direction towards the thin film surface starting from the a-Si Si interface. In a second process these needles induce growth of rectangular shaped Si crystallites (Si quantum dots) with 2–3 nm length and 3–5 nm width in the space between the needles. This process is driven by the difference in density between the a-Si regions and the Si- needles (ϱ(a-Si) > ϱ(Si)) and consequently leads to stretching of the a-Si regions. Strain relief is carried out consecutively by transition of these amorphous regions into the nanocrystalline phase. Room-temperature photoluminescence (PL) using the 337 nm line of an N2 laser for excitation shows intense blue light emission from the nanocrystalline thin films. The luminescence band between 2.6 and 3.2 eV consists of distinct peaks. Time resolved PL yields decay time constants τ1 = 170–250 ps and τ2 = 500–800 ps depending on the spatial positions of PL excitation across the sample surface. The blue light emission from the nanocrystalline thin films is explained by quantum size effects in the Si nanocrystallites which actually are Si quantum dots.

Self-organized growth of quantum-dot structures

Abstract: We found a new self-organizing growth mode in the metalorganic vapor-phase epitaxy (MOVPE) on high-index GaAs (311)B substrates to form well-ordered arrays of quantum-dots. The spontaneous interaction of strained InGaAs layers with AlGaAs buffer layers results in high-density rows of disk-shaped InGaAs quantum dots buried within AlGaAs microcrystals due to lateral mass transport. The size and distance of the disks are controlled independently in the mesoscopic size range by the In composition and the InGaAs layer thickness, respectively, without affecting the uniformity and the shape. The photoluminescence spectra exhibit narrow linewidth and high efficiency at room temperature. Buried quantum disk structures are formed also on other GaAs (n11)B substrates and on InP (311)B substrates, indicating this growth mode to be universal in the strained layer growth on high-index semiconductor surfaces.

Noise in mixed tunneling avalanche transit time (MITATT) diodes

Abstract: A generalized method of analysis for avalanche noise in mixed tunneling and avalanche transit time (MITATT) diode is reported. This method can be applied to MITATT diodes with arbitrary doping distribution and arbitrary material combinations. The method is capable of estimating the mean-square value of the noise voltage as well as the noise distribution due to individual space steps caused by the individual noise sources. The method has been applied to a variety of Si double-drift diode structures with different levels of tunneling currents. The results indicate some new and interesting features of noise for mixed-mode operation.

Comparison of different analytical descriptions of the temperature dependence of the indirect energy gap in silicon

Abstract: Novel analytical descriptions of the temperature dependence of the indirect energy gap in silicon are compared with conventional models due to Varshni [ Physica 34 , 149 (1967)] and Vina et al. [ Phys. Rev. B 30 , 1979 (1984)]. A high-precision fit is shown to be given by an empirical expression of the type E g (T) = E g (0) − ( α·Θ 2 )·( 1 + ( 2T Θ ) − 1 ) where α is the limiting gap shrinkage coefficient and Θ ≡ hω k represents the effective phonon temperature. For silicon, the empirical model parameter p is found to be significantly higher than 2, which is in analogy to many other semiconductor materials. The principal physical causes and analytical aspects of this common feature are briefly discussed on the background of forthcoming analytical results.

Analytical approach to breakdown voltages in thin-film SOI power MOSFETs

Abstract: The breakdown voltage behavior of thin-film SOI power MOSFETs is described using an analytical approach. Simple expressions for the vertical and horizontal characteristics of the device are developed one-dimensionally to analytically predict the critical impurity concentration of the drift region and the breakdown voltages. Using this modeling, the effect of device parameters is also examined. The validity of the analytical expressions is demonstrated by comparison with the extensive results of numerical simulations.

C-V and G-V characterization of in-situ fabricated Ga2O3GaAs interfaces for inversion/accumulation device and surface passivation applications

Abstract: Interface properties of Ga 2 O 3 GaAs structures fabricated using in-situ multiple-chamber molecular beam epitaxy have been investigated. The oxide films were deposited on clean, atomically ordered (100) GaAs surfaces at ≅600°C by electron-beam evaporation using a Gd 3 Ga 5 O 12 single-crystal source. Metal-oxide-semiconductor (MOS) capacitors were characterized by quasi-static capacitance voltage ( C - V ) as well as by C - V and conductance voltage ( G - V ) measurements at frequencies ranging from 100 Hz to 1 MHz. A midgap interface state density D it in the low 10 10 cm −2 eV −1 range has been inferred from C - V measurements using the quasi-static/high frequency technique. Although interface trap loss is almost entirely masked by oxide loss, a wide bottom of the D it - E characteristic extending from E v + 0.27 eV to E c − 0.19 eV has been concluded from G - V measurements. The formation of inversion layers in both n - and p -type GaAs has been clearly established.

The conduction properties of the silicon/off-stoichiometry-SiO2 diode

Abstract: The study of the silicon/silicon rich oxide diode is presented. The behaviour of the C - V and the I - V characteristics when the structure is positively and negatively bias stressed for N and P substrates is reported. It is found that the C min in the C - V curves is affected by the charge status of the SRO. A way to estimate the density of traps in the SRO from the C - V curves is proposed. In the case of the I - V curves a comparison between the results obtained for samples deposited on N or P type wafers is performed. The electric characteristics of this device are explained assuming that silicon islands introduce univalent traps in the SRO.

Substrate crosstalk in BiCMOS mixed mode integrated circuits

Abstract: A comparison of several crosstalk reduction schemes using two-dimensional device simulation and measurements on silicon has shown that while SOI based processes provide high isolation from crosstalk, fully junction isolated wells can provide equal or better crosstalk immunity at a lesser expense. Simple guard ring substrate contacts appear to be the technique best suited for preventing cross-talk at high operating frequencies. A lumped parameter equivalent circuit has also been developed to simulate fully junction isolated wells in SPICE.