Showing papers in "Solid-state Electronics in 2002"

GaN-based modulation doped FETs and UV detectors

Abstract: GaN based modulation doped field effect transistors (MODFETs) and ultraviolet detectors are critically reviewed. AlGaN/GaN MODFETs with CW power levels of about 6 W (in devices with 1 mm gate periphery) and a minimum noise figure of 0.85 dB with an associated gain of 11 dB have been obtained at 10 GHz. As a precursor to solar-blind detectors that will be operative around 280 nm, where the solar radiation is absorbed by the ozone layer surrounding the earth, detector arrays with pixel sizes of 32×32 operative near the solar-blind region have been achieved. One does not have to rely on imagination to predict that devices with much improved performance will continue to be developed.

An accurate charge control model for spontaneous and piezoelectric polarization dependent two-dimensional electron gas sheet charge density of lattice-mismatched AlGaN/GaN HEMTs

Abstract: The present paper proposes an improved charge control model of lattice-mismatched AlGaN/GaN HEMTs, valid over the entire operating region. The model for estimation of two-dimensional electron gas (2-DEG) sheet carrier concentration accounts for the strongly dominant spontaneous and piezoelectric polarization at the AlGaN/GaN heterointerface. The dependence of 2-DEG sheet carrier concentration on the aluminum composition and AlGaN layer thickness has been investigated in detail. Current–voltage characteristics developed from the 2-DEG model include the effect of field dependent mobility, velocity saturation and parasitic source/drain resistances. Close proximity with experimental data confirms the validity of the proposed model.

Fringing fields in sub-0.1 μm fully depleted SOI MOSFETs: optimization of the device architecture

Abstract: Lateral field penetration in the buried oxide (BOX) and underlying substrate of fully depleted SOI MOSFETs is responsible for a dramatic increase of short-channel effects. An original compact model of the latter phenomena is proposed and used to explore optimized architectures of sub-100 nm transistors. Various architectures including the ground-plane MOSFET, are compared using a quasi-2D analysis in order to evaluate the contribution of the BOX to short-channel effects.

A comparative study of surface passivation on AlGaN/GaN HEMTs

Abstract: Using a Si 3 N 4 layer as passivation layer, effects of surface passivation on device performances have been investigated. After passivation, devices exhibited better pinch-off characteristics and lower gate leakage current. For a device with a gate-length of 0.25 μm, the I dss increased from 791 to 812.2 mA/mm and the peak extrinsic transconductance increased from 207.2 to 220.9 mS/mm. The f T and f MAX values decreased from 53 and 102.5 to 45.9 and 90.5 GHz, respectively, due to the increase of parasitic capacitances. Microwave noise measurements showed that devices exhibited 0.2–0.25 dB increase in minimum noise figure (NF min ) after passivation.

AlGaN/GaN HFETs fabricated on 100-mm GaN on silicon ( 1 1 1 ) substrates

Abstract: The group III-nitride material system has been demonstrated by many groups to produce high performance, heterostructure field effect transistors (HFETs). AlGaN/GaN heterostructures yield high two-dimensional electron gas densities with high carrier mobilities and simultaneous high breakdown field. Devices based on this structure perform well at high power and at high frequency operating conditions. Most AlGaN/GaN HFETs to date have been produced on sapphire or silicon carbide substrates due to the limited availability of bulk GaN substrates. There are limitations in using these substrate materials in either thermal conductivity, cost or wafer diameter. The use of silicon substrates can overcome the issues of sapphire and SiC that limit manufacturability. In this work, results from HFETs fabricated on 100-mm silicon substrates using a proprietary MOCVD reactor design will be presented. The quality and uniformity of the GaN epitaxy, the microwave characterization of these devices at 2 GHz, and the thermal performance of large periphery devices on this material will be detailed. The electrical performance of these devices is found to be comparable to that of early devices on sapphire and SiC. The results will illustrate the viability of silicon as a low cost, manufacturable platform for AlGaN based devices from the standpoint of epitaxy, device performance, and thermal power handling.

Interplay of voltage and temperature acceleration of oxide breakdown for ultra-thin gate oxides

Abstract: In this work, we resolved several seemingly conflicting experimental observations regarding temperature dependence of oxide breakdown in the context of change of voltage acceleration factors with reducing voltages. It is found that voltage acceleration factor is temperature dependent at a fixed voltage while voltage acceleration factors are temperature independent at a fixed TBD. We unequivocally demonstrated that strong temperature dependence of time(charge)-to-breakdown, TBD(QBD), observed on ultra-thin gate oxides (<5 nm) is not a thickness effect as previously suggested. It is a consequence of two experimental facts: (1) voltage-dependent voltage acceleration and (2) temperature-independent voltage acceleration at a fixed TBD window. For the first time, time-to-breakdown at low temperature of −50 °C is reported. It is found that Weibull slopes are insensitive to temperature variations using accurate area-scaling method. The stress-induced leakage current (SILC) was used as a measure of defect-generation rate and critical defect density to investigate its correlation with the directly measured breakdown data, QBD(TBD). The comprehensive and statistical measurements of SILC at breakdown as a function of temperature are presented in detail for the first time. Based on these results, we conclude that SILC-based measurements cannot adequately explain the temperature dependence of oxide breakdown. Finally, we provide a global picture for time-to-breakdown in voltage and temperature domains constructed from two important empirical relations based on comprehensive experimental database.

Observation of resonant tunneling action in ZnO/Zn0.8Mg0.2O devices

Abstract: Resonant tunneling action in a ZnO/Zn 08 Mg 02 O double barrier device is reported The device structures consist of a single ZnO quantum well, with thickness of 6, 8, or 50 nm, placed between two Zn 08 Mg 02 O barriers, with a thickness of 7 nm The structures were grown by pulsed laser deposition on (0 0 0 1) c-cut sapphire substrates Negative differential resistance peaks were observed at room temperature and at 200 K The optical transitions in the quantum wells were evaluated from pulsed photoluminescence spectroscopy measurements, and found to be at 3588 eV for the 6 nm and 356 eV for the 8 nm quantum well The FWHM of the photoluminescence peaks were found to be 53 and 56 meV at 77 K, for the 6 and 8 nm wells respectively, indicating high quality heterointerfaces

Electrical characteristics of thin film cubic boron nitride

Abstract: Cubic boron nitride (c-BN), if properly developed, can be a very promising material for electronic applications, such as ultraviolet (UV) detectors and UV light emitting diodes operable at wavelengths in the deep UV regime Its energy bandgap is favorable also for field-effect transistors for high-power microwave applications Yet, electrical characteristics of c-BN have hardly been reviewed during the past years putting together its important features The present article attempts to describe the latest developments in electrical properties of c-BN taking into account metal–semiconductor contacts, interface states, lattice relaxation and impurity states, NEA, and other related topics In conclusion, current status and the future prospects for c-BN films have been discussed

A numerical study of ballistic transport in a nanoscale MOSFET

Abstract: We examine the physics of ballistic transport in a nanoscale MOSFET as reflected in the shape of the distribution function. We calculate the electron distribution function in the ballistic limit by solving the 1D steady-state Boltzmann transport equation self-consistently with the 2D Poisson equation in an n-channel ultra-thin-body nanoscale doublegate SOI MOSFET. In equilibrium, symmetry of the distribution function is achieved through balanced carrier injections from the source and drain contacts. Under bias, the distribution function displays distinctive features of ballistic transport–– a discontinuous asymmetric shape and the development of a discontinuous ballistic peak. We discuss the implications of ballistic transport to modeling of nanoscale MOSFETs based on moment-based macroscopic transport models. 2002 Elsevier Science Ltd. All rights reserved.

A critical review of thermal models for electro-thermal simulation

Abstract: This paper discusses some limitations in the approaches commonly adopted for device and circuit electro-thermal simulation Thermal models for circuit simulation assume a simple geometry for the region where power dissipation occurs Available models are compared The impact of model parameters and bias condition on simulation accuracy is discussed A new approach for calculating the temperature distribution under both steady-state and transient conditions is also proposed The accuracy of two-dimensional (2D) electro-thermal device simulations is then investigated It is shown that 2D simulations can lead to markedly inaccurate results Possible approaches to overcome these limitations are discussed

A compact large signal model of LDMOS

Abstract: Lateral double-diffused MOSFETs (LDMOS) are becoming more popular in RF power amplifiers for wireless communication applications. The understanding of non-linearity in LDMOS is critical in order to design ultra-linear power amplifiers to meet the stringent needs of current wireless systems. We have developed a compact large signal model that can predict accurately the transconductance of the device and its higher order derivatives. Such large signal model is needed in the accurate simulation of non-linear circuits. Our device measurements show that the higher order derivatives of the transconductance are very sensitive to the gate bias. The model has been applied to simulate the gain and third order intermodulation distortion in a RF LDMOS amplifier, and the simulated results agree well with the experimental measurements.

Spacer FinFET: nanoscale double-gate CMOS technology for the terabit era

Abstract: A spacer lithography technology using a sacrificial layer and a chemical vapor deposition (CVD) spacer layer has been developed, and is demonstrated to achieve sub-40 nm structures with conventional dry etching. The minimumsized features are finished not by photolithography but by the CVD film thickness. Therefore the spacer lithography technology yields critical dimension variations of minimum-sized features which are much smaller than achieved by optical or e-beam lithography. It also provides a doubling of device density for a given lithography pitch. This spacer lithography technology is used to pattern silicon-fin structures for double-gate MOSFETs and CMOS FinFET results are reported. 2002 Elsevier Science Ltd. All rights reserved.

Finding the optimum Al–Ti alloy composition for use as an ohmic contact to p-type SiC

Abstract: Alloys of aluminum and titanium have been successfully used to form low resistance ohmic contacts to p-type SiC. While the 90 wt.% Al alloy has been studied extensively, the literature does not reveal any work which indicates whether the 90/10 or any other alloy composition is the best alloy for use as an ohmic contact material to p-SiC. This work systematically looks at four different Al–Ti alloy compositions in an attempt to decide which alloy if any is superior as an ohmic contact material. The alloy compositions that were studied were chosen by examining the binary Al–Ti phase diagram and choosing specific phases prior to reaction with the SiC. It will be shown that only alloys which have some amount of a liquid phase present at the anneal temperature will form an ohmic contact to p-type SiC.

Reduction of the Schottky barrier height on silicon carbide using Au nano-particles

Abstract: By the incorporation of size-selected Au nano-particles in Ti Schottky contacts on silicon carbide, we could observe considerably lower the barrier height of the contacts. This result could be obtained for both n- and p-type Schottky contacts using current-voltage and capacitance voltage measurements. For n-type Schottky contacts, we observed reductions of 0.19-0.25 eV on 4H-SiC and 0.15-0.17 eV on 6H-SiC as compared with particle-free Ti Schottky contacts. For p-type SiC, the reduction was a little lower with 0.02-0.05 eV on 4H- and 0.10-0.13 eV on 6H-SiC. The reduction of the Schottky barrier height is explained using a model with enhanced electric field at the interface due to the small size of the circular patch and the large difference of the barrier height between Ti and Au.

Oxygen annealing modification of conduction mechanism in thin rf sputtered Ta2O5 on Si

Abstract: The effect of oxygen annealing at high temperature (873, 1123 K; 30 min) on the insulating properties and conduction mechanism of rf sputtered Ta2O5 (25–80 nm) on Si has been investigated. It is found that the oxygen heating significantly reduces the oxide charge (Qf The conduction mechanism of the as-deposited films is found to be of Poole–Frenkel (PF) type for a wide range of applied fields. A change of the conduction mechanism for the annealed films at medium fields (0.8–1.3 MV/cm) is established. This transition from PF process to the Schottky emission limited current is explained with an annealing of bulk traps (oxygen vacancies and nonperfect bonds). It is concluded that the dominant conduction mechanism in the intermediate fields can be effectively controlled by appropriate technological steps.

Low Schottky barrier source/drain for advanced MOS architecture: device design and material considerations

Abstract: An alternative MOSFET architecture based on the use of low barrier Schottky source/drain (S/D) contacts coupled to a thin silicon-on-insulator (SOI) film is described. Two-dimensional device simulations are used to demonstrate the advantage of low Schottky barrier S/D over conventional implanted technologies in terms of current drive capabilities. It is shown that the silicide penetration in the silicon does not increase the contact resistance for this structure while a severe degradation of the current drive is observed for conventional MOS architectures. Experiments conducted on Pt/Ge metallic stacks on p-type silicon show that very low Schottky barriers to hole can be obtained (∼50 meV).

A simple efficient model of parasitic capacitances of deep-submicron LDD MOSFETs

Abstract: Estimation of parasitic capacitances in a MOSFET device is very important, notably in mixed circuit simulation. For deep-submicron LDD MOSFETs, the extrinsic capacitance (overlap plus fringing capacitances) is a growing fraction of the total gate capacitance. A correct estimation of the extrinsic capacitance requires an accurate modeling of each of its constituents. However the major existing models do not correctly predict the overlap capacitance and the inner fringing capacitance (which is often ignored). In this paper a new approach to model the overlap Cov and fringing Cif+Cof capacitances in the zero-current regime is presented. The bias dependence of the extrinsic capacitance is investigated and a detailed study of the influence of the LDD doping dose is also undertaken. Then, an efficient, simple and continuous model describing the evolution of overlap and fringing capacitances in all operating regimes of a n-channel LDD MOSFET is developed. Finally this model is incorporated in an existing compact-model for circuit simulation. It is shown that this new model leads to excellent results in comparison with full 2D numerical device simulation.

Scaling of pseudomorphic high electron mobility transistors to decanano dimensions

Abstract: The performance enhancement associated with the scaling of pseudomorphic high electron mobility transistors (PHEMTs) to deep decanano dimensions is studied using Monte Carlo (MC) simulations. The full scaling of a standard 120 nm PHEMT to gate lengths of 90, 70, 50 and 30 nm in both lateral and vertical dimensions is compared with an approach where only the lateral dimensions are scaled. The study is based on an extended transport module integrated in the finite element MC simulator H2F and accurate up to an electric field of 200 kV/cm, and on the careful calibration of MC device simulations against I–V characteristics from the real 120-nm gate length PHEMT. The fully scaled devices exhibit a continuous improvement in transconductance as channel lengths reduce while performance deteriorates in devices scaled only laterally. The contact resistances become a limiting factor to the performance of the fully scaled devices at shorter channel lengths. The microwave performance of the scaled devices is studied using the transient MC analysis.

The vertical replacement-gate (VRG) MOSFET

Abstract: We have fabricated and demonstrated a new device called the vertical replacement-gate (VRG) MOSFET. This is the first MOSFET ever built in which: (1) all critical transistor dimensions are controlled preciselywithout lithographyand dryetch, (2) the gate length is defined bya deposited film thickness, independentlyof lithographyand etch, and (3) a high-qualitygate oxide is grown on a single-cry stal Si channel. In addition to this unique combination, the VRG-MOSFET includes self-aligned source/drain extensions (SDEs) formed bysolid source diffusion (SSD), small parasitic overlap, junction, and source/drain capacitances, and a replacement-gate approach to enable alternative gate stacks. We have demonstrated nMOSFETs with an initial VRG process, and pMOSFETs with a more mature process. Since both sides of the device pillar drive in parallel, the drive current per lm of coded width can far exceed that of advanced planar MOSFETs. Our 100 nm VRG-pMOSFETs with tOX ¼ 25 A drive 615 lA/lm at 1.5 V with IOFF ¼ 8 nA/lm—80% more drive than specified in the 1999 ITRS Roadmap at the same IOFF. Our 50 nm VRGpMOSFETs with tOX ¼ 25 A approach the 1.0 V roadmap target of ION ¼ 350 lA/l ma tIOFF ¼ 20 nA/lm without the need for a hyperthin (<20 A gate oxide. We have described a process for integrating n-channel and p-channel VRGMOSFETs to form side-by-side CMOS that retains the key VRG advantages while providing packing density and process complexitythat is competitive with traditional planar CMOS. All of this is achieved using current manufacturing methods, materials, and tools, and high-performance devices with 50 nm physical gate lengths (LG) have been demonstrated with precise gate length control without advanced lithography. 2002 Published byElsevier Science Ltd.

New method for determination of harmonic distortion in SOI FD transistors

Abstract: We present a new method for calculating the total harmonic distortion (THID) and the third harmonic distortion (HD3) of the output current-voltage characteristics of a semiconductor device. The method is based on the calculation of two functions which we call D and D3 and are based on a specific integration of the DC current-voltage characteristic of the device. In this paper we demonstrate that function D can be correlated with the THD and function D3 with the HD3, so that they can be determined in a much simpler way, with no need to use derivatives, Fourier coefficients or fast Fourier transforms. The new method is applied to calculate the harmonic distortion of a silicon-on-insulator (Sol) fully depleted (FD) MOS transistor in the triode regime to be used as an active resistor at the input of an operational amplifier in a MOSFET-C filter configuration. It is also demonstrated that the transistor I-DS-V-DS characteristics used in these calculations can be obtained from either measurements, analytical models or numerical simulations. (C) 2002 Elsevier Science Ltd. All rights reserved.

Organic light-emitting diode on indium zinc oxide film prepared by ion assisted deposition dc sputtering system

Abstract: In this letter, high-quality indium zinc oxide (IZO) films (60–220 nm) were first grown on hardness poly-carbonate substrate by ion-assisted deposition (IAD) dc magnetron sputtering without a post deposition annealing treatment. The electrical, optical, and structural properties of these films were investigated as a function of film thickness. IAD dc magnetron sputtering provides very uniform IZO films with high transparency (⩾85% in 550 nm spectrum) and low electrical resistivity ( 3×10 −4 Ω cm). The Hall mobility and carrier density for a 120-nm-thick film at 100 W are 12 cm 2 /V s and 2.5×10 21 cm −3 , respectively. The IZO films grown at low temperature by IAD dc magnetron sputtering were used for the organic light-emitting devices (OLEDs) as transparent anode. Under a current density of 100 mA/cm 2 , the developed OLEDs show an excellent efficiency (12 V turn-on voltage) and a luminance of 1200 cd/m 2 in average, which is better than that measured with commercial ITO anodes and suitable for the electro-optical application.

Device and circuit performance of SiGe/Si MOSFETs

Abstract: It is shown that a 4-fold improvement in static and dynamic CMOS circuit performance can be achieved by the introduction of strained silicon MOSFETs. A 2-fold improvement is obtained using pseudomorphic SiGe pMOSFETs in static CMOS. The industry standard compact model BSIM3v3 is able to capture the features of buried channel and surface channel SiGe based MOSFETs for SPICE simulations. TCAD shows that surface channel strained silicon MOSFETs offer better n-channel performance than buried channel devices, while p-channel devices buried up to 4 nm may outperform surface channel pMOSFETs. The impact of achievable mobility on device design and performance is presented.

Transient effects in PD SOI MOSFETs and potential DRAM applications

Abstract: The transients in partially depleted (PD) silicon on insulator (SOI) MOSFETs produced with 0.25 and 0.13 μm technologies are studied. The exponential dependence of the switch-on transient time on the reciprocal drain voltage for both P- and N-channel devices is explained by the predominance of the impact ionisation mechanism. A pulse method to measure output I – V curves using short gate pulses has been applied to study self-heating and transient effects in 0.13 μm SOI N-MOSFETs. It is shown that under normal operating conditions the difference between DC and pulsed I – V curves of PD SOI MOSFET is attributed mainly to the floating body effect and not to self-heating. We demonstrate also that it is possible to use the body charging of PD SOI devices to store information. Based on this effect, an original 1T-DRAM cell concept is proposed (DRAM: dynamic random access memory). This cell is at least two times smaller in area than the conventional 1T/1C DRAM cell and does not require the integration of a storage capacitor. This concept allows the manufacture of low cost DRAMs and embedded DRAMs for 100 and sub-100 nm generations.

Analysis of body bias effect with PD-SOI for analog and RF applications

Abstract: The interaction of the body bias effect, device size, and analog characteristics such as DC gain, the matching effect, and speed ( f T and f max ) of the sub-0.2 μm PD-SOI technology is reported. From the study, the optimized device size and the body bias for the analog and radio-frequency applications can be determined according to the specific utilization of the chip.

Design considerations for CMOS near the limits of scaling

Abstract: As MOSFETs reach the limits of scaling, a variety of physical and application-related constraints must be considered. This paper provides an overview of these constraints for conventional bulk-like MOSFET design, including two-dimensional effects due to short-channel length, tunneling currents through thin insulators and junctions, limitations on supply and threshold voltage reduction, dopant fluctuation effects, and overall system power dissipation requirements. We show that the end of scaling is different for different applications, depending especially on the leakage dissipation constraints.

Extraction of Schottky diode parameters including parallel conductance using a vertical optimization method

Abstract: An improved method based on a computer-aided curve fitting technique that uses vertical optimization for the simultaneous determination of various Schottky diode parameters ( I s , n , R s and G p ) from the I – V characteristics has been re-examined. In particular, it is shown that the inclusion of the effect of a shunt conductance in the analysis of transport properties allows the determination of more realistic values for the parameters of various quality diodes. The present method appears to be accurate even in the presence of noise and/or random errors during measurements.

Morphological study of the Al–Ti ohmic contact to p-type SiC

Abstract: The composition 70 wt.% Al was recently reported to provide low resistance Al–Ti ohmic contacts with excellent electrical uniformity on p-type SiC. Using scanning electron microscopy and atomic force microscopy, an investigation of the surface morphology and edge definition of the annealed contacts was conducted, and the morphology of the buried metal/semiconductor interface was examined by etching away the contact metallization and imaging the freshly exposed SiC surface. This information provides guidance on the suitability of the contact for devices with small feature sizes and shallow p-type epilayers. Patterned contacts exhibited good edge definition, a root-mean-square surface roughness of 11 nm, and a root-mean-square interfacial roughness of 12 nm. The deepest observed penetration of the metallization into the SiC was 65 nm, and the lateral length scale of the morphological features at the buried metal/semiconductor interface was sufficiently small compared to the active area of the contact to allow good contact-to-contact reproducibility. The interfacial reactions and ohmic contact formation mechanism are considered from the point of view of the materials characterization study presented here and the binary Al–Ti and quaternary Al–C–Si–Ti phase diagrams.

Properties of self-assembled ZnO nanostructures

Abstract: The formation of self-assembled ZnO nanoclusters using diblock copolymers, is reported. The diblock copolymers, consisting of a majority polymer (norbornene) and a minority polymer (norbornene-dicarboxcylic acid), were synthesized with a block repeat unit ratio of 400/50, to obtain spherical microphase separation and hence a spherical morphology for the metal oxide nanoclusters. The self-assembly of the inorganic nanoparticles was achieved at room temperature in the liquid phase, using ZnCl2 precursor dopant and wet chemical processing compatible with semiconductor manufacturing to convert to ZnO. FTIR and XPS spectroscopy, confirmed the association of the ZnCl2 precursor with the minority block and the formation of ZnO, while TEM showed the spherical morphology of ZnO nanoparticles as targeted, and a relatively narrow size distribution ranging between 7 and 15 nm.

NROM (TM) - a new technology for non-volatile memory products

Abstract: NROM TM ––is a new technology for non-volatile memories (NVMs); it offers three major improvements relative to the Floating Gate technology: one technology for all NVM products (Flash, EEPROM, ROM and Embedded), higher density (2.5 F 2 /bit in Flash, where F is the feature size of the process), and simpler process with reduced number of masks without any “exotic” materials. The NROM TM cell is based on localized charge trapping above the junction edge, storing two physically separated bits per cell. Performance of new NVM NROM TM based products show endurance up to 100 K with retention of 10 years at 150 °C.

Surface passivation of AlGaN/GaN HEMTs using MBE-grown MgO or Sc2O3

Abstract: Thin (100 A) layers of MgO or Sc2O3 grown by molecular beam epitaxy were investigated for surface passivation of AlGaN/GaN high electron mobility transistors. A variety of pre-treatments such as UV/O3 or in situ heating were employed prior to the dielectric deposition. Under optimized conditions, the MgO produced an increase in drain–source current, threshold voltage and extrinsic transconductance, which is consistent with passivation of surface states in the AlGaN. The absence of hydrogen in the dielectrics makes them attractive candidates for long-term stable passivation of the HEMTs.