Showing papers in "Solid-state Electronics in 2005"

Antimonide-based compound semiconductors for electronic devices: A review

Abstract: Several research groups have been actively pursuing antimonide-based electronic devices in recent years. The advantage of narrow-bandgap Sb-based devices over conventional GaAs- or InP-based devices is the attainment of high-frequency operation with much lower power consumption. This paper will review the progress on three antimonide-based electronic devices: high electron mobility transistors (HEMTs), resonant tunneling diodes (RTDs), and heterojunction bipolar transistors (HBTs). Progress on the HEMT includes the demonstration of Ka- and W-band low-noise amplifier circuits that operate at less than one-third the power of similar InP-based circuits. The RTDs exhibit excellent figures of merit but, like their InP- and GaAs-based counterparts, are waiting for a viable commercial application. Several approaches are being investigated for HBTs, with circuits reported using InAs and InGaAs bases.

Interfaces and defects of high-K oxides on silicon

Abstract: The properties of oxides with high-dielectric constant are being extensively studied for use as gate oxides. The criteria for choosing such oxides is discussed. The bonding at Si–oxide interfaces is considered in order to obtain an insulating interface. The stabilities of various atomic configurations of interface are compared, and their band offsets are calculated. The energy levels of point defects are calculated and the origin of fixed charge present is discussed.

A Design Oriented Charge-based Current Model for Symmetric DG MOSFET and its Correlation with the EKV Formalism

Abstract: We propose a design oriented charge-based model for undoped DG MOSFETs under symmetrical operation that aims at giving a comprehensive understanding of the device from the design strategy. In particular, we introduce useful normalizations for current and charges that in turn lead to very simple relationships among the physical quantities. Finally, we emphasize on the link that exists between this approach and the EKV formalism derived for bulk MOSFETs, which in turn leads to the unique gms/ID design methodology for DG architectures. © 2004 Elsevier Ltd. All rights reserved.

Accurate modeling and parameter extraction method for organic TFTs

Abstract: In this paper we demonstrate the applicability of the unified model and parameter extraction method (UMEM), previously developed by us, to organic thin film transistors, OTFTs. The UMEM, which has been previously used with a-Si:H, polysilicon and nanocrystalline TFTs, provides a much rigorous and accurate determination of main electrical parameters of organic TFTs than previous methods. Device parameters are extracted in a simple and direct way from the experimental measurements, with no need of assigning predetermined values to any other model parameter or using optimization methods. The method can be applied to both experimental and simulated characteristics of organic TFTs, having different geometries and mobility. It provides a very good agreement between transfer, transconductance and output characteristics calculated using parameter values obtained with our extraction procedure and experimental curves. Differences in mobility behavior, as well as other device features that can be analyzed using UMEM are discussed.

Measuring the specific contact resistance of contacts to semiconductor nanowires

Abstract: Ohmic contacts to semiconductor nanowires are essential components of many new nanoscale electronic devices. Equations for extracting specific contact resistance (or contact resistivity) from several different test structures have been developed by modeling the metal/semiconductor contact as a transmission line, leading to the development of equations analogous to those used for planar contacts. The advantages and disadvantages of various test structures are discussed. To fabricate test structures using a convenient four-point approach, silicon nanowires have been aligned using field-assisted assembly and contacts fabricated. Finally, specific contact resistances near 5 × 10−4 Ω cm2 have been measured for Ti/Au contacts to p-type Si nanowires with diameters of 78 and 104 nm.

An electron mobility model for wurtzite GaN

Abstract: A comprehensive model for the electron mobility in wurtzite (hexagonal) GaN is developed. A large number of experimental mobility data and the results of Monte Carlo transport simulations reported in the literature have been evaluated and serve as the basis for the model development. The proposed model describes the dependence of the mobility on carrier concentration, temperature, and electric field. Good agreement between the modeled low-field mobility and measured data at both room and elevated temperatures has been obtained. The Monte Carlo results of the high-field transport are correctly reproduced by the model. The model can be easily incorporated into numerical device simulators.

An analytical retention model for SONOS nonvolatile memory devices in the excess electron state

Abstract: We present an analytical retention model for scaled SONOS devices in the excess electron state. In this model, trap-to-band tunneling and thermal excitation discharge mechanisms are considered to be responsible for the temperature-dependent electron decay behaviors in SONOS devices. We assume an arbitrary trap distribution in energy within the charge-storage silicon nitride. Simulated retention characteristics are compared with experiment results measured on SONOS devices with a gate dielectric stack consisting of a 1.8 nm tunnel oxide, a 10 nm oxynitride and a 4.5 nm blocking oxide. We obtain good agreement between simulations and measurements for temperatures from 22 to 225 °C. We also extract the trap distribution in the nitride with this model. Finally, we discuss the influence of the gate dielectric properties (thickness, trap energy, etc.) and temperature on data retention of SONOS devices.

Beyond the conventional transistor

Abstract: Recent progress in continuing CMOS scaling is accomplished by introducing new device structures and new materials. This paper reviews recent progress in new technology features for silicon CMOS. With the imminent perceived “end” of CMOS device scaling, there is renewed interest in other non-silicon-FET based device and system architectures. We will discuss the merits of various proposed devices and fabrication techniques and suggest areas for further study.

Rigorous analytic solution for the drain current of undoped symmetric dual-gate MOSFETs

Abstract: We describe a new drain current model for nanoscale undoped-body symmetric dual-gate MOSFETs based on a fully consistent physical description. The model consists on a single analytic equation that includes both drift and diffusion contributions. It is built on the basis of the potentials at the surface and at the center of the silicon film evaluated at the source and drain ends. The derivation is completely rigorous and is based on a procedure previously enunciated for long-channel bulk SOI MOSFETs. The expression is a continuous description valid for all bias conditions, from subthreshold to strong inversion and from linear to saturation operation. The validity of the model has been ascertained by extensive comparison to exact numerical simulations. The results attest to the excellent accuracy of this formulation.

Effective resistivity of fully-processed SOI substrates

Abstract: We introduce in this work a new quality factor called effective resistivity (rho(eff)), which is used to characterize and fairly compare the substrate resistivity of fully processed SOI wafers. The impacts on rho(eff) (and thus on microwave losses) of the bias (V-a), fixed oxide charges (Q(ox)) traps at the SiO2/Si interface (D-it), oxide thickness (t(ox)) and line geometry are quantified and discussed for the first time. Different design and technological conclusions are drawn. (C) 2004 Elsevier Ltd. All rights reserved.

Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells

Abstract: An ‘atomistic’ circuit simulation methodology is developed to investigate intrinsic parameter fluctuations introduced by discreteness of charge and matter in decananometer scale MOSFET circuits. Based on the ‘real’ doping profile, the impact of random device doping on 6-T SRAM static noise margins are discussed in detail for 35 nm physical gate length devices. We conclude that SRAM may not gain all the benefits of future bulk CMOS scaling, and new device architectures are needed to scale SRAM down to future technology node.

FinFET analogue characterization from DC to 110 GHz

Abstract: In this work the analogue performance of 50 nm gate length FinFETs is investigated under static and dynamic conditions up to 110 GHz. The fin width is shown to have a large impact on some analogue figures of merit such as the Early voltage because it determines the existence of volume inversion, full or partial depletion inside the fins. The RF measurements show that a non-uniform silicidation of the three-dimensional polysilicon gate can have a strong impact on the device maximum frequency of oscillation (f(max)). However, it is also shown on the basis of experimental and modelled data that process optimization on the gate side as well as source/drain engineering should lead to f(max) values higher than 250 GHz, making FinFETs very promising devices for future use in RF applications. (c) 2005 Elsevier Ltd. All rights reserved.

Evolution of materials technology for stacked-capacitors in 65 nm embedded-DRAM

Abstract: The architecture, materials choice and process technology for stacked-capacitors in embedded-DRAM applications are a crucial concern for each new technology node. An overview of the evolution of capacitor technology is presented from the early days of planar PIS (poly/insulator/silicon) capacitors to the MIM (metal/insulator/metal) capacitors used for todays 65 nm technology node. In comparing Ta2O5, HfO2 and Al2O3 as high-k dielectric for use in 65 nm eDRAM technology, Al2O3 is found to give a good compromise between capacitor performance and manufacturability. The use of atomic layer deposition (ALD) is identified to be an enabling technology for both high-k dielectrics and capacitor electrodes. � 2005 Elsevier Ltd. All rights reserved.

Interface trap properties of thermally oxidized n-type 4H–SiC and 6H–SiC

Abstract: This work presents detailed investigations of interface traps at the Si-face 4H– and 6H–SiC/SiO 2 interfaces using thermally stimulated current (TSC) and capacitance–voltage ( C – V ) techniques. Using n-type material we focus on the interface traps near the SiC conduction band edge which, in the case of 4H–SiC, severely suppress the effective mobility in n-channel metal-oxide-silicon carbide transistors. Our TSC measurements demonstrate that electron traps at the 4H–SiC/SiO 2 interface consist of two groups of trap levels displayed as two distinguishable TSC signatures and differing by their trapping/detrapping behavior. One of them, chargeable at low temperatures, is displayed as a well-defined TSC peak assigned to a trapping level with an activation energy of 0.11 eV. Another is displayed as a wide TSC hump, and its charging mechanism strongly depends on temperature, indicating that these traps are not conventional “fast” interface states but border traps. A near-continuous distribution of activation energies ranging from 0.1 to 0.7 eV is obtained for these traps. The above two groups are observed in differently prepared thermal oxides on Si-face 4H–SiC. We hypothesize that both groups are due to the same interfacial defects but differing by their spatial closeness to the interface: the first is located in immediate proximity to the interface, while the second is composed of defects distributed within the oxycarbide transition layer, which explains their range of ionization energies and the thermally activated capture mechanism. No distinct interface traps are observed on 6H–SiC samples. In general, the electrical characteristics of the 6H–SiC/SiO 2 interface can be satisfactorily explained in terms of conventional “fast” interface states.

Diamond semiconductor technology for RF device applications

Abstract: This paper presents a comprehensive review of diamond electronics from the RF perspective. Our aim was to find and present the potential, limitations and current status of diamond semiconductor devices as well as to investigate its suitability for RF device applications. While doing this, we briefly analysed the physics and chemistry of CVD diamond process for a better understanding of the reasons for the technological challenges of diamond material. This leads to Figure of Merit definitions which forms the basis for a technology choice in an RF device/system (such as transceiver or receiver) structure. Based on our literature survey, we concluded that, despite the technological challenges and few mentioned examples, diamond can seriously be considered as a base material for RF electronics, especially RF power circuits, where the important parameters are high speed, high power density, efficient thermal management and low signal loss in high power/frequencies. Simulation and experimental results are highly regarded for the surface acoustic wave (SAW) and field emission (FE) devices which already occupies space in the RF market and are likely to replace their conventional counterparts. Field effect transistors (FETs) are the most promising active devices and extremely high power densities are extracted (up to 30 W/mm). By the surface channel FET approach 81 GHz operation is developed. Bipolar devices are also promising if the deep doping problem can be solved for operation at room temperature. Pressure, thermal, chemical and acceleration sensors have already been demonstrated using micromachining/MEMS approach, but need more experimental results to better exploit thermal, physical/chemical and electronic properties of diamond.

AlGaN/GaN Schottky diode hydrogen sensor performance at high temperatures with different catalytic metals

Abstract: Schottky diodes on AlGaN/GaN heterostructures with Pt, IrPt, and PdAg catalytic metals are fabricated and characterized from 200 °C to 800 °C for H 2 sensing. Over this large range of temperature, the forward current of all the diodes increases with exposure to H 2 gas, which is attributed to Schottky barrier height reduction caused by the atomic hydrogen absorption on the metal–oxide interface. The results indicate that AlGaN/GaN heterostructure Schottky diodes are capable of high-temperature H 2 sensor operation up to 800 °C. As temperature increases, the hydrogen detection sensitivity of Pt and IrPt diodes improves due to the more effective H 2 dissociation. However, the sensitivity of PdAg diodes degrades with the increase of temperature due to thermal instability of PdAg. At a range of temperature from 200 °C to 300 °C, PdAg diodes exhibit significant higher sensitivity compared with Pt and IrPt diodes. IrPt and Pt diodes show higher sensitivity at temperatures above 400 °C.

Sub-band structure engineering for advanced CMOS channels

Abstract: This paper reviews our recent studies of novel CMOS channels based on the concept of sub-band structure engineering. This device design concept can be realized as strained-Si channel MOSFETs, ultra-thin SOI MOSFETs and Ge-on-Insulator (GOI) MOSFETs. An important factor for the electron mobility enhancement is the introduction of larger sub-band energy splitting between the 2- and 4-fold valleys on a (1 0 0) surface, which can be obtained in strained-Si and ultra-thin body channels. The electrical properties of strained-Si MOSFETs are summarized with an emphasis on strained-SOI structures. Also, the importance of the precise control of ultra-thin SOI thickness is pointed out from the experimental results of the SOI thickness dependence of mobility. Furthermore, it is shown that the increase in the sub-band energy splitting can also be effective in obtaining higher current drive of n-channel MOSFETs under ballistic transport regime. This suggests that the current drive enhancement based on MOS channel engineering utilizing strain and ultra-thin body structures can be extended to ultra-short channel MOSFETs dominated by ballistic transport.

Scaling down the interpoly dielectric for next generation Flash memory: Challenges and opportunities

Abstract: We review the main issues in scaling down the interpoly dielectric (IPD) for future floating gate Flash memory technology generations. The equivalent oxide thickness (EOT) of the IPD must reach the sub-10 nm range to enable lowering of the operating voltages and further scale device feature sizes. Additionally, the loss of control gate wrap around the floating gate for high density memories as device dimensions scale down will require a drastic reduction (up to 60%) in IPD EOT to maintain the same capacitive coupling. As the scalability of the conventional oxide-nitride-oxide (ONO) IPD’s is limited, we propose new solutions that exploit the opportunities offered by the high- κ dielectrics. Their effectiveness increases when midgap and p-type metals are considered, instead of the conventional polysilicon control gate. The optimal approach depends on the most critical requirement that the IPD has to fulfill, which in turn is application or device-structure dependent. The nonideal nature of the dielectric materials, however, may severely reduce the design window, calling for a sustained effort to improve their electrical properties by process optimization.

The barrier height inhomogeneity in identically prepared Au/n-GaAs Schottky barrier diodes

Abstract: We have prepared small Au/n-GaAs Schottky barrier diodes (SBDs) using e-beam lithography (EBL), and obtained their effective barrier heights (BHs) and ideality factors from current–voltage ( I / V ) characteristics, which were measured using a conducting probe atomic force microscope (CP-AFM). Although the diodes were all identically prepared, there was a diode-to-diode variation: the effective BHs ranged from 0.795 eV to 0.836 eV, and the ideality factor from 1.025 to 1.101. Lateral homogeneous BHs were computed from the observed linear correlation between BH and ideality factor using the method of Schmitsdorf et al. [Schmitsdorf RF, Kampen TU, Monch W. J Vac Sci Technol B 1997;15(4):1221]. These homogeneous BHs were also obtained from the fit to the experimental I / V characteristics of the current through a “patchy” diode. From our model, the barrier height in the patches and their diameter could be determined. It are however the homogeneous BHs which should be used to make theories of the physical mechanisms responsible for the Schottky barrier height of the metal–semiconductor combination considered.

An improved semi-classical Monte-Carlo approach for nano-scale MOSFET simulation

Abstract: A conventional Monte-Carlo simulator has been extended to include electrostatic and transport effects that are most relevant for the analysis of nano-scale MOSFETs with either bulk or single and double gate silicon-on-insulator (SOI) architectures and silicon film thickness down to approximately 10 nm. Corrections to the self-consistent electrostatic potential and a new model for the surface roughness scattering have been included. The effectiveness of the approach has been tested simulating carrier transport in a 25 nm double gate SOI MOSFET. The simulation results point out the strong influence of the scattering on the ON current even in these ultra-scaled devices.

Carrier transport mechanisms and photovoltaic properties of Au/p-ZnPc/p-Si solar cell

Abstract: The dark current density–voltage characteristics of Au/p-ZnPc/p-Si device at different temperatures ranging from 302 to 364 K have been investigated. Results showed a rectification behavior. At low forward bias, the current density was found to limited by the thermionic emission of holes from p-Si over the organic/inorganic barrier in the ZnPc thin film, while at high voltages, space charge limited current mechanism dominated by a single trapping level. Junction parameters such as, built-in potential, V bi , carrier concentration, N , the width of the depletion layer, W , were obtained from the C – V measurements. The current density–voltage characteristics under light illumination provided by tungsten lamp (200 W/m 2 ) gives values of 0.44 V, 31.25 A/m 2 , 0.335% and 2.3% for the open circuit voltage, V oc , the short circuit current density, J sc , the fill factor, FF, and conversion efficiency, η , respectively.

Charge trapping memory structures with Al2O3 trapping dielectric for high-temperature applications

Abstract: Charge trapping memory structures with Al 2 O 3 dielectrics as a trapping dielectric are investigated in a metal–Al 2 O 3 –oxide–silicon configuration with a metal gate of high work function. The devices show very good write/erase characteristics, endurance, retention and disturb behaviour. At elevated temperature, devices with an Al 2 O 3 trapping layer are found to have better retention properties than devices with a silicon nitride trapping layer.

Extraction of non-ideal junction model parameters from the explicit analytic solutions of its I–V characteristics

Abstract: In modeling semiconductor junctions the extraction of the models parameters is often hindered by the presence of parasitic series resistance and shunt conductance. We propose a method to extract the intrinsic and extrinsic model parameters using the exact explicit analytic solutions for current and voltage of the junctions I–V characteristics, which are expressed in terms of Lambert W functions. However, direct numerical fitting of these solutions to extract the models parameters would be an unwieldy and computationally inefficient task. To circumvent this difficulty, the proposed method is based on first calculating the Integral Difference Function, D, from the explicit analytic solutions for I and V. This produces a purely algebraic equation in I and V whose coefficients contain the models parameters. The coefficients of this auxiliary equation can be quickly determined by direct numerical fitting. From them, all the intrinsic and extrinsic model parameters are then readily obtained at once. The method is tested on representative synthetic I–V characteristics to illustrate the computation process. 2004 Elsevier Ltd. All rights reserved.

Organic thin film transistors: a DC/dynamic analytical model

Abstract: In this paper a new DC/dynamic analytical model for organic thin-film transistors (OTFTs) is presented. The model is based on the variable range hopping theory, i.e. thermally activated tunneling of carriers between localized states. It accurately accounts for below-threshold, linear, and saturation operating conditions via a single formulation. Furthermore, the model does not require the explicit definition of the threshold and saturation voltages as input parameters, which are rather ambiguously defined, and it is suitable for CAD applications.

Characteristics of 4H–SiC MOS interface annealed in N2O

Abstract: 4H–SiC(0 0 0 1) MOSFET annealed in N2O at below 1150 °C is systematically investigated. Inversion-type planar MOSFETs show higher channel mobility and lower threshold voltage by increasing anneal temperature. Through C–V measurement of n-type MOS capacitors, the interface state density is revealed to decrease at higher anneal temperature. The field effect mobility of 30 cm2/Vs is achieved by 1150 °C anneal for 3 h, which is about 10 times higher than that of not annealed MOSFET. Epitaxial n-channel MOSFET annealed in N2O has been also fabricated. A positive threshold voltage of 0.46 V and the field effect mobility of 45 cm2/Vs are attained. The effective mobility at 2.5 MV/cm is 34 cm2/Vs, which is five times higher than that for not annealed sample, suggesting that the N2O anneal improves the MOS interface quality.

Integration of buried insulators with high thermal conductivity in SOI MOSFETs: Thermal properties and short channel effects

Abstract: SOI circuits exhibit excellent performance and scalability but suffer from self-heating. Systematical 2D simulations demonstrate that the thermal dissipation in SOI MOSFETs can be improved dramatically by replacing the buried oxide with high thermal conductance insulators. The self-heating can be reduced by as much as 50–100 °C. Yet, these materials feature high-K dielectric constant, which also affects the electrical properties: more severe short-channel effects, parasitic capacitances and drain-to-body fringing fields. The conciliation between the thermal and electrical properties of advanced SOI MOSFETs (50 nm long, 10 nm thick) is examined by comparing different SOI materials (air, SiO2, diamond, AlN, Al2O3, SiC) and MOS architectures. We demonstrate the advantage of a ground plane (GP) located under the buried insulator (BOX). Diamond is excellent candidate for relatively thick BOX whereas Al2O3 and SiC are suitable for ultra-thin BOX. These novel structures can be fabricated by wafer bonding technology.

Improved DC and RF performance of AlGaN/GaN HEMTs grown by MOCVD on sapphire substrates

Abstract: High-quality AlGaN/GaN high electron mobility transistor (HEMT) structures were grown by metalorganic chemical vapor deposition (MOCVD) on 2-in. sapphire substrates. Two-dimensional electron gas (2DEG) mobility of 1410 cm(2)/Vs and concentration of 1.0X10(13) CM-2 are obtained at 295 K from the HEMT structures, whose average sheet resistance and sheet resistance uniformity are measured to be about 395 Omega/sq and 96.65% on 2-in. wafers, respectively. AlGaN/GaN HEMTs with 0.8 mu m gate length and 0.2 mm gate width were fabricated and characterized using the grown HEMT structures. Maximum current density of 0.9 A/ mm, peak extrinsic transconductance of 290 mS/mm, unity cutoff frequency (f(T)) of 20 GHz and maximum oscillation frequency (f(max) of 46 GHz are achieved. These results represent significant improvements over the previously fabricated devices with the same gate length, which are attributed to the improved performances of the MOCVD-grown HEMT structures. (c) 2005 Elsevier Ltd. All rights reserved.

Preparation and gas-sensing properties of NiFe2O4 semiconductor materials

Abstract: The gas-sensing materials, NiFe2O4, were prepared by inverse titrating chemical co-precipitation. After calcinations at 350–700 °C for 1 h, respectively, p-type semiconductor gas-sensing materials with inverse spinel structure were obtained. Effects of the calcining temperature on the phase constituents and microstructure were studied and characterized by simultaneous differential scanning calorimetry and thermogravimetry analysis (DSC–TGA), X-ray diffraction (XRD) and transmission electron microscopy (TEM). NiFe2O4 used as sensitive materials of indirect heating structure sensors were fabricated on an alumna tube with Au electrodes and platinum wires. The gas-sensing properties were determined for using reducing gases. The results demonstrated that the sensors based on NiFe2O4 had good sensitivity and good selectivity to toluene. The difference in response for various tested gases might be attributed to absorption of reducing gases and reaction between these gases and the absorbed oxygen.

Direct demonstration of the ‘virtual gate’ mechanism for current collapse in AlGaN/GaN HFETs

Abstract: Potential probes to the channel of a long channel AlGaN/GaN HFET are used to directly measure the increase in resistance of the ungated regions at the source and drain that are responsible for current collapse under pulsed conditions. Silicon nitride passivation is shown to be an effective means of preventing the formation of the ‘virtual gate’ on the ungated surface.

Design and optimization of junction termination extension (JTE) for 4H–SiC high voltage Schottky diodes

Abstract: This paper analyzes single- and double-zone junction termination extension (JTE) structures for 4H–SiC Schottky diodes using numerical simulations. In the single-zone case, we study the effects of JTE dose, depth, length, metal/JTE overlap length, and surface or interface charge. In the double-zone case, we systematically vary the inner and outer doses over about 80 possible combinations for each of three sets of inner and outer zone widths. The total JTE width is constrained to be that necessary for optimum breakdown voltage in the single-zone case. The results are presented as contour plots of breakdown voltage and maximum surface field as a function of the two doses, with the locations of peak bulk and surface fields also indicated at each point. The resulting tolerance to variations in activated dose can then be visualized directly. The physics underlying the shapes of the contours is explained in some detail. We show that JTE behavior is significantly different for Schottky diodes compared to the better-known case of p ( i ) n junction diodes. The peak surface field is increased for Schottky diodes when the single-zone dose is reduced below its optimum value, which is opposite to the behavior of pn junctions. Moreover, double-zone JTE is not effective in reducing peak surface field for the Schottky case, unlike pn junctions, although tolerance to dose variations can be improved with two zones. The usual rule of thumb for double-zone JTE design for pn junctions is not appropriate for Schottky diodes, because of the field crowding near the sharp metal edge. We recommend an inner dose of 95–105% of the ideal single-zone and an outer dose of 70–80% of the single-zone value, with a width ratio of ∼1:1 for the inner and outer zones and a total width similar to the optimal value in a single-zone design.