Showing papers in "Solid-state Electronics in 2007"
IBM1
TL;DR: In this article, the influence of dimensionality on the performance of tunneling field effect transistors is investigated with simulations and it is shown that in contrast to the 3D case, one-dimensional systems offer the possibility to combine a high on-state performance with steep inverse sub-threshold slopes.
Abstract: The influence of the dimensionality on the performance of tunneling field-effect transistors is investigated with simulations. It is shown that in a three-dimensional tunneling FET it is possible to achieve inverse subthreshold slopes smaller than 60 mV/dec. However, there is a trade-off between high on-currents and small values for the subthreshold swing. Using a carbon nanotube tunneling FET as an example it is shown that in contrast to the 3D case, one-dimensional systems offer the possibility to combine a high on-state performance with steep inverse subthreshold slopes.
277 citations
TL;DR: In this article, the length scaling of the double gate tunnel field effect transistor (DG Tunnel FET) is studied. And the authors show that the scaling limits are reached sooner by tunnel FETs with an SiO2 gate dielectric, while those with a high-K dielectoric can be scaled further before threshold voltage, and average and point subthreshold swing are affected.
Abstract: In this paper, the length scaling of the silicon Double Gate Tunnel Field Effect Transistor (DG Tunnel FET) is studied. It is found that scaling limits are reached sooner by Tunnel FETs with an SiO2 gate dielectric, while those with a high-K dielectric can be scaled further before threshold voltage, and average and point subthreshold swing are affected. It is demonstrated that the scaling of the high-K Tunnel FET is completely different than that of conventional MOS transistors. An outstanding feature of the Tunnel FET switch is that length scaling has a much weaker impact on device characteristics than does gate control (e.g. the use of a high-K dielectric), which primarily dictates the tunneling barrier width and consequently, device conduction. This paper demonstrates that while some improvements are observed, the length scaling does not dramatically affect switch figures of merit such as subthreshold slope, Ion and Ioff down to about 20 nm, and an optimized device design can be extended over a much larger window of sub-micron dimensions, compared to the MOSFET. A discussion of the length dependence of the transconductance, gm, and output conductance, gds of the Tunnel FET is presented for the first time.
185 citations
TL;DR: In this paper, a metal-semiconductor-metal (MSM) photoconductive detector was fabricated on c-axis preferred oriented ZnO film prepared on quartz by radio frequency magnetron sputtering.
Abstract: In this study, metal–semiconductor–metal (MSM) photoconductive detector was fabricated on c -axis preferred oriented ZnO film prepared on quartz by radio frequency magnetron sputtering. With the applied bias below 3 V, the dark current was below 250 nA. The typical responsivity peaked at around 360 nm, and had values of 30 A/W. In addition, the UV (360 nm) to visible (450 nm) rejection ratio of around five orders could be extracted from the spectra response. Furthermore, the transient response measurement revealed fast photoresponse with a rise time of 20 ns.
165 citations
TL;DR: In this paper, a review of the recent mobility enhancement technologies including application of strain and new channel materials such as SiGe, Ge and III-V materials are reviewed. And the results on MOSFETs using these three types of the technologies with an emphasis on the global strained Si/Si/SiGe/Ge substrates and the combination with the local techniques are presented.
Abstract: Mobility enhancement technologies have currently been recognized as mandatory for future scaled MOSFETs. In this paper, the recent mobility enhancement technologies including application of strain and new channel materials such as SiGe, Ge and III–V materials are reviewed. These carrier transport enhancement technologies can be classified into three categories; global enhancement techniques, local enhancement techniques and global/local-merged techniques. We present our recent results on MOSFETs using these three types of the technologies with an emphasis on the global strained-Si/SiGe/Ge substrates and the combination with the local techniques. Finally, issues on device structures merged with III–V materials are briefly described.
137 citations
TL;DR: In this paper, the design, fabrication and testing of novel one and two port piezoelectric higher-order contour-mode MEMS resonators that can be employed in RF wireless communications as frequency reference elements or arranged in arrays to form banks of multi-frequency filters are presented.
Abstract: This paper reports on the design, fabrication and testing of novel one and two port piezoelectric higher order contour-mode MEMS resonators that can be employed in RF wireless communications as frequency reference elements or arranged in arrays to form banks of multi-frequency filters. The paper offers a comparison of one and two port resonant devices exhibiting frequencies approximately ranging from 200 to 800 MHz, quality factor of few thousands (1000–2500) and motional resistances ranging from 25 to 1000 Ω. Fundamental advantages and limitations of each solution are discussed. The reported experimental results focus on the response of a higher order one port resonator under different environmental conditions and a new class of two port contour resonators for narrow band filtering applications. Furthermore, an overview of novel frequency synthesis schemes that can be enabled by these contour-mode resonators is briefly presented.
135 citations
TL;DR: Pretet et al. as discussed by the authors investigated the super-coupling effect in fully depleted SOI devices and revealed new challenges in the characterization of ultra-thin devices, such as gate oxide tunneling, thin buried oxide, and ultra thin films.
Abstract: A standard characterization method in fully depleted SOI devices consists in biasing the back interface in the accumulation regime, and measuring the front-channel properties. In ultra thin body device however, it is sometimes no longer possible to achieve such an accumulation regime at the back interface. This unusual effect is investigated by detailed simulations and analytical modelling of the potential and electron/hole concentrations. The enhancement of the interface coupling effect in ultra thin body devices, called super-coupling, can explain previously published experimental data [Pretet J, Ohata A, Dieudonne F, Allibert F, Bresson N, Matsumoto T, et al. Scaling issues for advanced SOI devices: gate oxide tunneling, thin buried oxide, and ultra-thin films. In: 7th International symposium silicon nitride and silicon dioxide thin insulating films, Paris, France, 2003. Electrochemical Society Proceedings, vol. 2003-02, Pennington (USA); 2003. p. 476–87], and reveals new challenges in the characterization of advanced SOI devices.
128 citations
TL;DR: In this article, empirical relations for k-values and energy band offset values for gate dielectric materials are presented, which can be used in the search for gate-dielectric material fulfilling the needs of future CMOS generations.
Abstract: From experimental literature data on metal oxides combined with theoretical estimates, we present empirical relations for k -values and energy band offset values, that can be used in the search for gate dielectric materials fulfilling the needs of future CMOS generations. Only a few materials investigated so far have properties meeting the demands for k and energy band offset values in the development of CMOS down to 22 nm.
125 citations
TL;DR: In this paper, the photovoltaic properties of organic solar cells based on pentacene and C 60 thin films with a focus on their spectral responses and the effect of thermal annealing were analyzed.
Abstract: We report on the photovoltaic properties of organic solar cells based on pentacene and C 60 thin films with a focus on their spectral responses and the effect of thermal annealing. Spectra of external quantum efficiency (EQE) are measured and analyzed with a one-dimensional exciton diffusion model dependent upon the complex optical functions of pentacene films, which are measured by spectroscopic ellipsometry. An improvement in EQE is observed when the thickness of the bathocuproine (BCP) layer is decreased from 12 nm to 6 nm. Detailed analysis of the EQE spectra indicates that large exciton diffusion lengths in the pentacene films are responsible for the overall high EQE values near wavelengths of 668 nm. Analysis also shows that improvement in the EQE of devices with the thinner BCP layer can be attributed to a net gain in optical field distribution and improvement in carrier collection efficiency. An improvement in open-circuit voltage ( V OC ) is also achieved through a thermal annealing process, leading to a net increase in power conversion efficiency. Integration of the EQE spectrum with an AM1.5 G spectrum yields a predicted power conversion efficiency of 1.8 ± 0.2%. The increase in V OC is attributed to a significant reduction in the diode reverse saturation current upon annealing.
122 citations
TL;DR: It is shown that Si-based RF transistors are very fast and compete successfully with GaAs pHEMTs and GaAs HBTs, and reasons for the competitive performance of Si- based RF transistor are provided.
Abstract: This paper provides an overview on the status, development and performance of current and future RF transistors. The targets specified in the 2005 issue and the 2006 update of the International Technology Roadmap for Semiconductors (ITRS) are addressed and used as a blueprint, and potential challenges and problems to achieve these targets are discussed. Main emphasis is given to Si-based RF transistors, i.e., Si RF MOSFETs and SiGe HBTs, but relevant information on III–V RF transistors is also included. It is shown that Si-based RF transistors are very fast and compete successfully with GaAs pHEMTs and GaAs HBTs. As the result of a qualitative discussion, reasons for the competitive performance of Si-based RF transistors are provided.
120 citations
TL;DR: In this paper, the short-channel properties of multi-gate SOI MOSFETs were analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness, and the radius of curvature of the corners.
Abstract: The short-channel properties of multi-gate SOI MOSFETs (MuGFETs) are studied by numerical simulation. The evolution of characteristics such as DIBL, subthreshold slope, and threshold voltage roll-off is analyzed as a function of channel length, silicon film or fin thickness, gate dielectric thickness and dielectric constant, and as a function of the radius of curvature of the corners. The notion of an equivalent gate number is introduced. This number ranges from 2 for a double-gate device to 4 in a gate-all-around transistor. The equivalent gate number can be used in general equations to predict the absence or presence of short-channel effects. As a general rule, increasing the equivalent gate number improves the short-channel behavior of the devices. Similarly, increasing the radius of curvature of the corners improves the control of the channel region by the gate.
114 citations
TL;DR: In this article, the effect of temperature on the performance of Schottky diodes has been investigated as a function of temperature by using forward bias currentvoltage (I-V) measurements, and it has been concluded that the temperature dependence of the forward bias I-V characteristics of the Au/SnO2/n-Si (MIS)-Schottky diode can be successfully explained on the basis of a thermionic emission (TE) mechanism with a Gaussian distribution of barrier heights.
Abstract: The variation in electrical characteristics of Au/SnO2/n-Si (MIS) Schottky diodes have been systematically investigated as a function of temperature by using forward bias current–voltage (I–V) measurements The main diode parameters, ideality factor n and zero-bias barrier height ΦB0, were found strongly temperature dependent and while the zero-bias barrier height ΦB0(I–V) increases, the n decreases with increasing temperature This behavior has been interpreted by the assumption of a Gaussian distribution of barrier heights due to barrier inhomogenities that prevail at the metal–semiconductor interface The zero-bias barrier height ΦB0 vs q/(2kT) plot has been drawn to obtain evidence of a Gaussian distribution of the barrier heights, and values of Φ ¯ B 0 = 1101 eV and σ0 = 0158 V for the mean barrier height and zero-bias standard deviation have been obtained from this plot, respectively Thus a modified ln(I0/T2) − ( q 2 σ 0 2 ) /2k2T2 vs q/(kT) plot has given mean barrier height Φ ¯ B 0 and Richardson constant (A*) as 1116 eV and 12786 A cm−2 K−2, respectively The A* value 12786 A cm−2 K−2 obtained from this plot is in very close agreement with the theoretical value of 120 A cm−2 K−2for n-type Si Hence, it has been concluded that the temperature dependence of the forward bias I–V characteristics of the Au/SnO2/n-Si (MIS) Schottky diode can be successfully explained on the basis of a thermionic emission (TE) mechanism with a Gaussian distribution of the Schottky barrier heights (SBHs) In addition, we have reported a modification by the inclusion of both n and αχ05δ in the expression of I0 to explain the positive temperature dependence of ΦB0 against that of energy band-gap of Si Thus, the values of temperature coefficient of the effective barrier height ΦBef(−364 × 10−4 eV/K) is very close agreement with the temperature coefficient of Si band-gap (−473 × 10−4 eV/K)
TL;DR: In this paper, a mixture of crystalline phase ZrO2 and amorphous phase Al2O3 was used for DRAM capacitor dielectrics of 60nm and below technologies.
Abstract: New ZrO2/Al2O3/ZrO2 (ZAZ) dielectric film was successfully developed for DRAM capacitor dielectrics of 60 nm and below technologies. ZAZ dielectric film grown by ALD has a mixture structure of crystalline phase ZrO2 and amorphous phase Al2O3 in order to optimize dielectric properties. ZAZ TIT capacitor showed small Tox.eq of 8.5 A and a low leakage current density of 0.35 fA/cell, which meet leakage current criteria of 0.5 fA/cell for mass production. ZAZ TIT capacitor showed a smaller cap leak fail bit than HAH capacitor and stable leakage current up to 550 °C anneal. TDDB (time dependent dielectric breakdown) behavior reliably satisfied the 10-year lifetime criteria within operation voltage range.
Abstract: This paper examines the impact of an important geometrical parameter of FinFET devices, namely the fin width. From static and low-frequency measurements on n-FinFETs ( I – V , C – V and 1/ f noise), transistor Figures of Merit in the near-threshold region (like threshold voltage, subthreshold slope, and drain induced barrier lowering); linear region (mobility, series resistance, 1/ f noise) and saturation region (normalized transconductance, early voltage) are analyzed as a function of fin width. In the near-threshold region, fin width is seen to strongly impact the coupling between the back and front gates, while in the above threshold region, the most important impact of fin width is on the parasitic source/drain resistance, which affects different strong inversion parameters to different extents. With the help of analytical expressions, the impact of series resistance on these device parameters is studied, and the contribution from series resistance is de-embedded, enabling extraction of intrinsic device parameters. Significant differences are observed between the intrinsic and extrinsic parameters, especially for short and narrow devices, which also underlines the need for accounting for series resistance effects at every stage of FinFET characterization.
IBM1
TL;DR: In this article, the authors reviewed the progress in scaling of MOS transistors and integrated circuits over the years and today's status and challenges are described and updated for the present leakage-constrained environment to project results of continued scaling at a constant power-supply voltage.
Abstract: Progress in scaling of MOS transistors and integrated circuits over the years is reviewed and today’s status and challenges are described. Generalized scaling is updated for the present leakage-constrained environment to project results of continued scaling at a constant power-supply voltage. Alternatives to achieve energy-efficient operation at lower voltages are discussed. Particular attention is given to threshold variability issues and to the design challenges in reducing and controlling variability using back-gate devices. The importance of the depth of the inversion layer below the silicon surface as a limit to the effectiveness of gate-insulator scaling is illustrated by a design study. Low-temperature operation is considered as a possible future direction for continuing scaling.
TL;DR: In this paper, a new SOI high voltage device structure with variable-k (permittivity) dielectric buried layer (VK SOI) is proposed, in which the buried layer is made of two dielectrics.
Abstract: A new SOI high voltage device structure with variable- k (permittivity) dielectric buried layer (VK SOI) is proposed in this paper. In this structure, the buried layer is made of two dielectrics, one of which is the low- k dielectric. The breakdown voltage is enhanced due to the modulation effect of the variable- k buried layer on the electric fields in the buried layer and drift region. An analytical model for the electric field and breakdown voltage in VK SOI is presented taking the modulation effect into account, from which the RESURF condition is derived. The dependences of the electric field distribution and breakdown voltage on the device parameters for VK SOI are investigated. Compared with the conventional SOI, the electric field of the buried layer and breakdown voltage of VK SOI with relative permittivity k I2 = 2 of the low- k dielectric are enhanced by 81% and 56%, respectively. The analytical results are in good agreement with those of 2D simulations. Finally, the proposed model and RESURF condition can be well applied to the conventional SOI and also extended to VT SOI (variable thickness buried layer SOI) devices.
TL;DR: NXP's family of SOI-based advanced bipolar CMOS DMOS (A-BCD) technologies is presented in this paper, which is very successful in automotive, audio and power applications.
Abstract: NXP’s family of SOI-based advanced bipolar CMOS DMOS (A-BCD) technologies is presented. The technology is very successful in automotive, audio and power applications. This paper introduces the technology, the device concepts and the applications. The advantage of BCD technology on SOI is in the ability to have all devices fully dielectrically isolated. This enables various device-biasing conditions (like high side or below substrate voltage), which are not easy to realise on bulk. This creates competitive advantage in the mentioned applications. As an example this enables extreme robust EMC (electro magnetic compatibility) and EMI (electro magnetic immunity) circuitry for CAN (controlled area network), or LIN (local interconnect network) transceivers in automotive. The leakage currents of the devices are much lower compared to bulk. The same holds for parasitic capacitances towards the substrate. LIGBT’s can be built without suffering from minority carriers being injected into the substrate. The area of power devices is in general very small due to the usage of the double Resurf principle and trench isolation. This small area pays off for high voltage analogue circuits. Special topics on self-heating and ESD are being treated, where it is demonstrated that performance is comparable to bulk. Three applications where SOI based BCD generates a functionality advantage, are being explained. The SOI based technology is an excellent starting point for development of future products were monolithic solutions can be built with embedded power or even embedded MEMs technology.
TL;DR: In this paper, the electrical transport properties of PVK (poly N-vinyl carbazole), a polymer exhibiting an intrinsic electroluminescence (EL) in blue region, have been investigated.
Abstract: Electrical transport properties of PVK (poly N-vinyl carbazole), a polymer exhibiting an intrinsic electroluminescence (EL) in blue region, have been investigated. In particular, resistivity and charge carrier mobility have been assessed by means of I–V measurements and by Field Effect (FET) doping, respectively. Dielectric constant has been also evaluated by means of C–V measurements performed on an ITO/PVK/Al single layer electroluminescent (EL) device. All electrical characterizations, carried out in different environmental conditions to deeply investigate PVK intrinsic conduction mechanisms, allowed to assess the good quality of spin coated PVK thin films. Electroluminescent measurements performed on ITO/PVK/Al and on ITO/PVK/Alq3/Al have been also performed. Finally, charge injection mechanisms from the electrodes to PVK have been investigated also as a function of the temperature. Experimental results have been compared with some well known theoretical models.
TL;DR: In this paper, the capacitance and voltage characteristics of lattice mismatched AlGaN/GaN modulation doped field effect transistor are obtained using charge controlled analysis for its microwave performance.
Abstract: Polarization dependent analysis for AlGaN/GaN HEMT has been done The capacitance–voltage characteristics of lattice mismatched AlGaN/GaN modulation doped field effect transistor are obtained using charge controlled analysis for its microwave performance The model includes the spontaneous and piezoelectric polarization effects and device transconductance and cutoff frequency are calculated The results show excellent agreement when compared with experimental data thereby proving the validity of the model
TL;DR: In this article, a high-quality Ga-doped ZnO film was epitaxially grown on a Rplane sapphire substrate by plasma-assisted molecular-beam epitaxy.
Abstract: A high-quality Ga-doped ZnO film was epitaxially grown on a R-plane sapphire substrate by plasma-assisted molecular-beam epitaxy. Photoconductor devices with Al/Ti Ohmic contacts were fabricated. Photoluminescence and photocurrent measurements were carried out to study the emission and absorption properties of the Ga-doped ZnO film. Both spectra are consistent with each other showing good response in the ultraviolet region and weak response in the green–yellow band. Peak responsivity of 1.68 A/W at 20 V bias for 374 nm light was obtained in the ultraviolet region. Transient response of the device is slow due to the presence of the deep levels.
TL;DR: In this article, a red light sensor with pentacene phototransistors (PTs) with a thin film transistor (TFT) configuration was investigated as a red-light sensor.
Abstract: Pentacene phototransistors (PTs) prepared with a thin film transistor (TFT) configuration were investigated as a red light sensor. The pentacene TFTs showed an efficient photo-current response under various intensities of both modulated or continuous red light. The pentacene PTs showed a reliable high responsivity of 1 A/W and the ratio of photocurrent to dark current (IPh/IDark) was 9000 under visible light at a wavelength of 650 nm due to the relatively small band gap of pentacene. � 2007 Elsevier Ltd. All rights reserved.
TL;DR: In this article, coupled quantum and statistical mechanical calculations are used to design materials with precisely controlled charge perturbation and charge transport (under the influence of applied electric fields) critical to the realization of desired photonic and electronic properties.
Abstract: Electronic and photonic properties of organic materials are well-known to depend on the intra- and intermolecular interaction of π-electron orbitals. We describe the systematic use of coupled quantum and statistical mechanical calculations to design materials with precisely controlled charge perturbation and charge transport (under the influence of applied electric fields) critical to the realization of desired photonic and electronic properties. Control of electro-optic activity is taken as an example because this phenomenon requires that acentric (dipolar or charge-transfer) molecules be organized in a lattice arrangement exhibiting finite noncentrosymmetric symmetry. Noncentrosymmetric organization of dipolar π-electron chromophores is also an arrangement of potential relevance to optimization of the performance of electronic, photovoltaic, and photorefractive materials. In our theoretical calculations, the roles of inter- and intramolecular electrostatic interactions and the effects of applied electrical and optical fields are explicitly taken into account. A variety of experimental tests of theoretical predictions are executed and a new class of materials is introduced and evaluated. Theoretically-inspired molecular and nanoscopic material design is shown to yield electro-optic coefficients ( r 33 ) at telecommunication wavelengths on the order of 500 pm/V (15 times greater than lithium niobate). The optimization of auxiliary properties including optical loss, thermal stability and conductivity is also discussed.
TL;DR: In this article, a monolithic 4 × 4 tin oxide gas sensor array together with on-chip multiplexing and differential read-out circuitry is presented, which uses a surface micro-machined micro-hotplate based structure.
Abstract: This paper presents a monolithic 4 × 4 tin oxide gas sensor array together with on-chip multiplexing and differential read-out circuitry. A robust fabrication process focusing on the integration of the CMOS circuitry and the microelectromechanical systems (MEMS) structure is first described. The gas sensor uses a surface micro-machined micro-hotplate based structure. Platinum is selected as the material of choice for both the micro heater and the sensor’s electrodes, for its good thermal stability and compatibility with the sensing film. Different post-treatments are used to modify the characteristics of the tin oxide gas sensors hence improving the sensor’s selectivity of the overall sensor array. Furthermore, in contrast to the conventional voltage divider read-out technique, a novel differential read-out circuit (DRC) for tin oxide gas sensors is proposed. The DRC applies a constant current to drive the sensor and uses a unit-gain single stage amplifier (inverter) to generate a fully differential output, directly from the voltage drop across the sensor. The output of the DRC is simply proportional to the difference between the voltage on the two electrodes of the sensor but not to the transistor parameters such as mobility and threshold voltage, neither to the supply voltage. The monolithic sensor array and its pre-processing circuitry have been implemented in our in-house 5 μm process. Experimental results showed good linearity at the output of the DRC for a wide range of sensor resistance variation (over 20 MΩ). The fabricated micro-hotplate sensor array was tested for four target gases. Results show good sensitivity and interesting thermal characteristic leading to only 15.5 mW power consumption for 300 °C operating temperature.
TL;DR: In this paper, an analytical and continuous model for a highly-doped double-gate Sol MOSFET, in which the channel current is expressed as an explicit function of the applied voltages, is presented targeting the electrical simulation of baseband analog circuits.
Abstract: An analytical and continuous model for a highly-doped double-gate Sol MOSFET, in which the channel current is expressed as an explicit function of the applied voltages, is presented targeting the electrical simulation of baseband analog circuits. A unified charge control model is for the first time derived for doped double-gate transistors. It is valid from below to well above threshold, showing a smooth transition between the regimes. Small-signal parameters can be obtained from the model. The calculated current and capacitance characteristics show a good agreement with 2D numerical device simulations, in all regimes, and also a very good match to FinFET experimental data, in the case of the drain current. (c) 2007 Elsevier Ltd. All rights reserved.
TL;DR: In this paper, a strain-relief underlying layer was employed to reduce the strain in the InGaN well layers arising from the large lattice mismatch between InN and GaN.
Abstract: InGaN/GaN multiple quantum well (MQW) structures were grown by MOCVD. A strain-relief underlying layer was employed to reduce the strain in the InGaN well layers arising from the large lattice mismatch between InN and GaN. Samples were investigated by photoluminescence (PL), electroluminescence (EL) and atom force microscopy (AFM) to characterize their optical and morphological properties. By inserting an underlying layer, the PL intensity was increased more than three times. Under small injection current (1–15 mA), the blue-shift of EL peak wavelength was decreased from 8 to1.8 nm, the surface morphology was improved and the density of V-pits was reduced from 14–16 × 10 8 to 2–4 × 10 8 /cm 2 . Further, the 20-mA output power was increased by more than 50%.
TL;DR: In this paper, the performance of semiconductor mid-IR lasers with double heterostructure, quantum well, quantum cascade, quantum wire, quantum dash and quantum dot active regions have been reviewed.
Abstract: Semiconductor lasers emitting in mid-infrared (IR) range, 2–5 μm, have many important applications in semiconductor industries, military, environmental protection, telecommunications, molecular spectroscopy, biomedical surgery and researches. Different designs of the reactive regions in mid-IR laser structures have been investigated for achieving high performance devices. In this article, semiconductor mid-IR lasers with double heterostructure, quantum well, quantum cascade, quantum wire, quantum dash and quantum dot active regions have been reviewed. The performance of the lasers with these different active regions and the development of the newly emerging III–V–N materials for mid-IR applications have been discussed in details.
TL;DR: In this paper, an artificial neural network (ANN) was applied to the study of the nanoscale CMOS circuits, based on the 2-D numerical non-equilibrium Green's function (NEGF) simulation of the current-voltage characteristics of an undoped symmetric DG MOSFET.
Abstract: As critical transistor dimensions scale below the 100 nm (nanoscale) regime, quantum mechanical (QM) effects begin to manifest themselves and affect important device performance metrics. Therefore, simulation tools which can be applied to design nanoscale transistors in the future, require new theory and modeling techniques that capture the physics of quantum transport accurately and efficiently. In this paper, we apply an artificial neural network (ANN) to the study of the nanoscale CMOS circuits. The latter is based on the 2-D numerical non-equilibrium Green’s function (NEGF) simulation of the current–voltage characteristics of an undoped symmetric DG MOSFET. The encouraging comparisons between numerical results and ANN PSPICE simulations have indicated that the developed ANN subcircuit representation particularly suitable to be incorporated in SPICE-like tools for nanoscale CMOS circuits simulation.
TL;DR: In this paper, the authors present the fabrication and characterization of ultra thin and relatively thick SiGe-On-Insulator wafers with different Ge contents prepared by Ge condensation technique.
Abstract: We present the fabrication and characterization of ultra thin and relatively thick SiGe-On-Insulator wafers with different Ge contents prepared by Ge condensation technique. The fabrication procedures as well as the structural analysis are detailed. The electrical properties of advanced strained SiGe-On-Insulator (SGOI) and relaxed Germanium-On-Insulator (GeOI) wafers were investigated using the Pseudo-MOSFET method and then compared with Silicon-On-Insulator (SOI) and strained Silicon-On-Insulator (sSOI) structures. GeOI wafers with 10-nm and 100-nm film thickness show exceptionally high hole mobility as compared to both SOI and sSOI structures. The hole mobility can reach 400 cm 2 /V s. It is found that the mobilities for holes and electrons vary in opposite directions as the Ge fraction is increased. The Ge content also impacts the threshold and flat-band voltages.
TL;DR: In this article, an overview of low-frequency (LF) noise of silicon-on-insulator (SOI) devices and technologies is given, and the impact of SOI substrate, gate stack processing, isolation module, etc., on the LF noise is described.
Abstract: An overview is given on the low-frequency (LF) noise of silicon-on-insulator (SOI) devices and technologies. In the first two parts, noise mechanisms specific for SOI are discussed, namely, the front–back-gate coupling in fully-depleted MOSFETs and the Lorentzian noise overshoot in floating-body operating transistors. In the next part, the impact of the technology (SOI substrate, gate stack processing, isolation module, …) on the LF noise is described. From this, it is derived that scaling below the 0.25 μm CMOS node did not result in the anticipated reduction of the 1/f noise with tfox or t fox 2 . This is related to the increasing amount of nitrogen incorporated in the thin SiON front gate oxides with thickness tfox. In the case of high-κ dielectrics it is frequently observed that these have a higher trap density compared to SiO2. On the other hand, today’s multigate SOI transistors seem to give rise to similar gate oxide trap densities and hence, 1/f noise, than their single-gate counterparts. In the last part, operational and circuit aspects will be discussed, which might have a beneficial impact on the LF noise performance.
TL;DR: Wet-etching-induced surface patterning of p-type indium tin oxide (ITO) electrodes has been investigated to improve the light output of GaN-based light-emitting diodes (LEDs).
Abstract: Wet-etching-induced surface patterning of p-type indium tin oxide (ITO) electrodes has been investigated to improve the light output of GaN-based light-emitting diodes (LEDs). Etching of as-deposited ITO layers in a buffered-oxide-etch solution results in the formation of a high density of randomly distributed sphere-shaped protrusions (250–1100 nm in size). LEDs fabricated with the 7 s-etched ITO electrodes yield higher light output (by 31.7% at 20 mA) compared with LEDs made with unpatterned ITO electrodes. The improvement is attributed to the increased light escape probability via the randomly distributed sphere-shaped protrusions formed on the electrode surfaces.
TL;DR: Cerium-dicyclohexano-18-crown-6 complex was used to fabricate organic light-emitting diode (OLEDs) with structure of ITO (indium tin oxide)/CuPc (copper-phthalocyanine)/Ce-DC-18·C·6: CBP (4,4′-bis(9-carbazolyl)biphenyl)/Bu-PBD (2-(4-biphenylyl)-5-( 4- tert -butylphenyl)-
Abstract: Cerium-dicyclohexano-18-crown-6 complex, Ce-DC-18·C·6, was prepared and used to fabricate organic light-emitting diode (OLEDs) with structure of ITO (indium tin oxide)/CuPc (copper-phthalocyanine)/Ce-DC-18·C·6: CBP (4,4′-bis(9-carbazolyl)biphenyl)/Bu-PBD (2-(4-biphenylyl)-5-(4- tert -butylphenyl)-1,3,4-oxadiazole)/LiF/Al. In the device the emitter layer consists of Ce(III)-complex as a dopant and CBP as a host. Adopting this doping Ce(III)-complex film, the device exhibits ultraviolet (UV) emission at 376 nm and maximum UV radiance power 13 μW/cm 2 at 3 wt% Ce(III)-complex doped device is obtained, which has been improved by about two times in comparison with no Ce(III)-complex layer UV device. In terms of photoluminescence (PL) of Ce(III) ion and CBP film, we demonstrated that the two UV emissions should be assigned to be from electron transitions of 5d → 4f of the Ce(III) ion and of S 1 → S 0 of CBP molecule, respectively. Increasing in UV radiation at shorter UV wavelength is more valuable and interesting for solid lighting application because the shorter UV emission would much match with excitation bands of more organic or inorganic phosphors. The mechanism on the electroluminescence (EL) processes of Ce(III) ion was also discussed.