Showing papers in "Solid-state Electronics in 2009"

Micropower energy harvesting

Abstract: More than a decade of research in the field of thermal, motion, vibration and electromagnetic radiation energy harvesting has yielded increasing power output and smaller embodiments. Power management circuits for rectification and DC–DC conversion are becoming able to efficiently convert the power from these energy harvesters. This paper summarizes recent energy harvesting results and their power management circuits.

High density 3D memory architecture based on the resistive switching effect

Abstract: We demonstrate the fabrication of a 3D memory architecture based on the resistive switching effect. Resistive memory (RRAM) is under wide investigation since it is non-volatile, promises fast operation and can be integrated into high density architectures like crossbar arrays. Here, silver-doped methyl-silsesquioxane (MSQ) is integrated in crossbar array structures for the following reasons. First, the material at the same time provides good planarization properties so that emerging lithography techniques like nanoimprint lithography (NIL) are applicable. Second, we could prove that silver-doped MSQ can be used as resistive switching material on the nano scale. Using this technique, crossbar arrays with a minimum feature size of only 100 nm are stacked on each other and the functionality is proved by electrical characterization. This comprises the doubling of the memory density and furthermore even higher integration is in principle not limited by this technique, while the CMOS overhead increases only slightly.

Electrical properties of poly-Ge on glass substrate grown by two-step solid-phase crystallization

Abstract: The carrier concentration and mobility of intrinsic holes in poly-Ge films grown by solid-phase crystallization (SPC) were investigated. The two-step SPC method, consisting of low-temperature annealing (425 °C) to obtain large grains and subsequent high-temperature annealing (500 °C) to decrease defects, is proposed. The hole concentration remarkably decreased from 1 × 10 18 to 5 × 10 17 cm −3 with keeping a high-mobility (140 cm 2 /Vs) after post-annealing.

Plastic circuits and tags for 13.56 MHz radio-frequency communication

Abstract: We discuss the design and implementation of 64-bit and 128-bit plastic transponder chips for radio-frequency identification tags. The 64-bit chips, comprising 414 organic thin-film transistors, are integrated into fully functional plastic radio-frequency identification tags with 13.56 MHz communication. The required supply voltage on the tag is generated from the AC input signal detected by the antenna, using a plastic double half-wave rectifier circuit. The tag is fully functional at a magnetic field strength of 1.26 A/m, which is below the minimum required radio-frequency magnetic field stated in the standards. We discuss the reading distance that can be achieved with our plastic rectifiers, and show that this reading distance is not limited by the performance of the plastic rectifier or transponder chip. The 128-bit transponder chip includes further features such as Manchester data encoding and a basic ALOHA anti-collision protocol. It employs 1286 organic thin-film transistors and generates the 128 bit sequence at 24 V supply voltage at a data rate of 1.5 kb/s. Data rates up to 2 kb/s could be achieved on chips with an 8-bit transponder chip. © 2009 Elsevier Ltd. All rights reserved.

FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

Abstract: In this paper we compare Fully-Depleted SOI (FDSOI) devices with different BOX (Buried Oxide) thicknesses with or without ground plane (GP). With a simple high-k/metal gate structure, the 32 nm devices exhibits Ion/Ioff performances well suited for low power (LP) applications. The different BOX thicknesses and ground plane conditions are compared with bulk 45 nm technology in terms of variability and noise. A 0.499 μm2 SRAM cell has been characterized with less than 50 pA of standby current/cell and a SNM of 210 mV @ Vdd 1 V.

Impact of electrostatics and doping concentration on the performance of silicon tunnel field-effect transistors

Abstract: We present experimental studies on the performance of ultra-thin body SOI tunnel FETs depending on channel length, gate oxide thickness and source/drain doping concentrations. Electrical measurements show no dependance on channel length, however, a strong dependance on gate oxide thickness and doping concentration is found. Our experimental results match calculations based on a simple Landauer model employing the Wenzel–Kramer–Brillouin approximation for the tunneling process. Bandgap narrowing and the electrostatics of the tunneling junction are found to be the main factors impacting the on-state performance of the tunnel FET.

A low-noise single-photon detector implemented in a 130 nm CMOS imaging process

Abstract: We report on a new single-photon avalanche diode (SPAD) fabricated in a 130 nm CMOS imaging process. A novel circular structure combining shallow trench isolation (STI) and a passivation implant creates an effective guard ring against premature edge breakdown. Thanks to this guard ring, unprecedented levels of miniaturization may be achieved at no cost of added noise, decreased sensitivity, or timing resolution. The detector, integrated along with quenching and readout electronics, was fully characterized. A second batch of detectors with decreased n-well doping was fabricated, thus reducing the dark count rate (DCR) by several orders of magnitude. To the best of our knowledge, the DCR per unit area achieved in these devices is the lowest ever reported in deep sub-micron CMOS SPADs. Optical measurements show the effectiveness of the guard ring and the high degree of electric field planarity across the sensitive region of the detector. With a photon detection probability (PDP) of up to 36% and a timing jitter of 125 ps at full-width-half-maximum, this SPAD is well-suited for applications such as 3D imaging, fluorescence lifetime imaging, and biophotonics.

Determination of electron effective mass and electron affinity in HfO2 using MOS and MOSFET structures

Abstract: We present a combined electrical and modeling study to determine the tunneling electron effective mass and electron affinity for HfO 2 . Experimental capacitance–voltage ( C – V ) and current–voltage ( J – V ) characteristics are presented for HfO 2 films deposited on Si(1 0 0) substrates by atomic layer deposition (ALD) and by electron beam evaporation (e-beam), with equivalent oxide thicknesses in the range 10–12.5 A. We extend on previous studies by applying a self-consistent 1D-Schrodinger–Poisson solver to the entire gate stack, including the inter-layer SiO x region – and to the adjacent substrate for non-local barrier tunnelling – self-consistently linked to the quantum-drift-diffusion transport model. Reverse modeling is applied to the correlated gate and drain currents in long-channel MOSFET structures. Values of (0.11 ± 0.03) m 0 and (2.0 ± 0.25) eV are determined for the HfO 2 electron effective mass and the HfO 2 electron affinity, respectively. We apply our extracted electron effective mass and electron affinity to predict leakage current densities in future 32 nm and 22 nm technology node MOSFETs with SiO x thicknesses of 7–8 A and HfO 2 thicknesses of 23–24 A.

Growth of ZnO:Al films by RF sputtering at room temperature for solar cell applications

Abstract: Aluminum-doped ZnO (ZnO:Al) films were prepared at room temperature in pure argon ambient on glass substrates by RF magnetron sputtering. The influence of sputtering power, deposition pressure and film thickness on the film properties was investigated. The deposited ZnO:Al films were characterized to examine the electrical, optical, and structural properties for the application of thin copper indium gallium selenide (CIGS) solar cells. The deposition parameters of ZnO:Al films were optimized. The optimized ZnO:Al films showed a strong and sharp (0 0 2) X-ray diffraction peak. The 600–800 nm thick ZnO–Al films showed a high transparency above 85% in the visible range and a sheet resistance low to 10 Ω/□. CIGS solar cells with 1.2 μm thick absorbers were fabricated using bi-layer ZnO films (low resistive and thick ZnO:Al/high resistive and transparent thin i-ZnO) as front contacts. The thin absorber layers were prepared by the low cost technique involving co-sputtering of Cu–Ga alloy and In targets and selenization with Se powders. Efficiencies of the order of 6–7% were achieved for the manufactured thin CIGS solar cells without antireflective films. The results demonstrated that RF sputtered ZnO:Al films are suitable for application in low cost and thin CIGS solar cells as transparent conductive electrode layers.

Negative capacitance in light-emitting devices

Abstract: The negative capacitance behavior in light-emitting diodes and laser diodes has been observed and characterized by using ac admittance–voltage method. Experimental results proved that the strong negative capacitance behavior is always accompanied by remarkable light emission. We confirmed that the negative capacitance is an effect of the junction instead of other behavior or measurement error. We presented a numerical calculation by solving one dimension continuity equation based on a simple diode model. The results show that the negative capacitance behavior in light-emitting diodes has great relation to injected carriers recombination in the active region of luminescence.

Temperature dependent analytical model for current-voltage characteristics of AlGaN/GaN power HEMT

Abstract: A temperature dependent analytical model has been presented for AlGaN/GaN power high electron mobility transistor (HEMT) to predict the DC performance at elevated temperatures. In this model the effects of temperature on band gap energy, sheet carrier density, threshold voltage, carrier mobility, and saturation velocity are taken into consideration. Channel length modulation in the saturation region of operation and spontaneous and piezoelectric polarization induced charges at the AlGaN/GaN heterointerface are also included in this model. Temperature- and bias-dependent on-wafer current–voltage measurements from 300 K to 500 K were carried out to verify the developed model. DC measurements and model predictions are presented for an AlGaN/GaN power HEMT fabricated on SiC substrate. The developed model shows good agreement with the measured data for a wide range of temperatures.

Overview and future challenges of floating body RAM (FBRAM) technology for 32 nm technology node and beyond

Abstract: Floating body cell (FBC) is a one-transistor memory cell on SOI substrate aimed at high-density embedded memory on SOC. In order to verify this memory cell technology, a 128 Mb floating body RAM (FBRAM) with FBC has been designed and successfully developed. The memory cell design and the experimental results, including single-cell operation, are reviewed. Based on the experimental results, the scalability of FBC down to 32 nm technology node is also discussed.

Efficient electron transfers in ZnO nanorod arrays with N719 dye for hybrid solar cells

Abstract: Hybrid organic–inorganic solar cells have been focused on producing materials in the combination of metal oxide with high electron mobility and organic semiconductors of conjugated polymers. In this article, we demonstrated the charge injection efficiency of hybrid solar cell consisting of poly(3-hexylthiophene) (P3HT) and (6,6)-phenyl C 61 butyric acid methyl ester (PCBM)/ZnO with and without N719 dye molecule. After the modification of ZnO nanorod arrays with N719, short-circuit current density ( J sc ) of 8.89 mA/cm 2 was obtained, and it was 1.5 times higher than that of without the N719. The power conversion efficiency was enhanced from 1.16% to 2.0% through the additional surface modification of the ZnO nanorod array with N719 dye.

Zinc tin oxide based driver for highly transparent active matrix OLED displays

Abstract: Zinc tin oxide (ZTO) is a promising active material for transparent electronics. We have realized the first transparent active matrix OLED pixel drivers with ZTO channels. The devices are highly transparent (>80%) in the visible part of the spectrum and suitable for see-through AM OLED displays with brightness levels of 2000 cd/m 2 at 100 Hz refresh rate and full-HD resolution.

Fully-depleted Ge interband tunnel transistor: Modeling and junction formation

Abstract: Complementary fully-depleted Ge interband-tunneling field-effect transistors (TFETs) and static inverters are modeled to quantify TFET performance relative to Si MOSFETs. SYNOPSYS TCAD is used to compute the two-dimensional electrostatics and determine the tunnel junction electric field. This electric field is used in an analytic expression to compute the tunnel current. The speed and power performance of TFETs are compared with the nMOSFET at the same supply voltage, 0.5 V. For a gate length of 20 nm, Ge tunnel transistors can provide similar speed in comparison to 45-nm-node nMOSFETs (18 nm gate length), but saves more than 2× in power and lowers energy by over 7×. Toward demonstrating these transistors, a process for forming submicron p + n + Ge tunnel junctions has been utilized in which Al-doped p + Ge is regrown on n + Ge, following melt-back of a patterned Al deposition. Transmission electron microscopy (TEM) reveals the regrown film and a contact microstructure consistent with the Al–Ge phase diagram. The low peak-to-valley current ratio (PVR) of devices produced by this growth method is likely a result of point defects or junction doping non-uniformity as TEM suggest no dislocations at the regrown junction. The PVR of these junctions does not improve as the device area is reduced from 100 to 0.1 μm 2 , a size smaller than the formation scale for grains in the Al–Ge system.

The charge transport mechanism in silicon nitride: Multi-phonon trap ionization

Abstract: The charge transport mechanism in amorphous silicon nitride, Si3N4, was experimentally examined to compare measured data with theoretical calculations made within the Frenkel model and the multi-phonon model of trap ionization. A good agreement between the experimental data and theoretical predictions could be achieved assuming the multi-phonon mechanism to be in effect. The widely accepted Frenkel model, although capable of explaining the measured data, fails to yield realistic values of the electron tunnel mass and attempt-to-escape factor.

Mobility extraction in SOI MOSFETs with sub 1 nm body thickness

Abstract: In this work we discuss limitations of the split-CV method when it is used for extracting carrier mobilities in devices with thin silicon channels like FinFETs, ultra thin body silicon-on-insulator (UTB-SOI) transistors and nanowire MOSFETs. We show that the high series resistance may cause frequency dispersion during the split-CV measurements, which leads to underestimating the inversion charge density and hence overestimating mobility. We demonstrate this effect by comparing UTB-SOI transistors with both recessed-gate UTB-SOI devices and thicker conventional SOI MOSFETs. In addition, the intrinsic high series access resistance in UTB-SOI MOSFETs can potentially lead to an overestimation of the effective internal source/drain voltage, which in turn results in a severe underestimation of the carrier mobility. A specific MOSFET test structure that includes additional 4-point probe channel contacts is demonstrated to circumvent this problem. Finally, we accurately extract mobility in UTB-SOI transistors down to 0.9 nm silicon film thickness (four atomic layers) by utilizing the 4-point probe method and carefully choosing adequate frequencies for the split-CV measurements. It is found that in such thin silicon film thicknesses quantum mechanical effects shift the threshold voltage and degrade mobility.

Analytical models of front- and back-gate potential distribution and threshold voltage for recessed source/drain UTB SOI MOSFETs

Abstract: Front-gate and back-gate potential distributions and threshold voltage of recessed source/drain (ReS/D) ultrathin body (UTB) silicon-on-insulator (SOI) MOSFETs are modeled. The analytical expressions of the front-gate and the back-gate potential distributions are derived by assuming a parabolic potential variation perpendicular to channel and by solving 2D Poisson’s equation. Based on strong inversion criterion applied to the surface potential minimum value, threshold voltage model of the short channel ReS/D UTB SOI MOSFETs is derived. The model is verified by comparison with 2D numerical device simulator over a wide range of different material and geometrical parameters and very good agreement is obtained.

The improvement of ohmic contact of Ti/Al/Ni/Au to AlGaN/GaN HEMT by multi-step annealing method

Abstract: A multi-step rapid thermal annealing process of Ti/Al/Ni/Au was investigated for ohmic contact of AlGaN/GaN high electron mobility transistor (HEMT). The samples were studied by Transmission Line Model (TLM), Scanning Electron Microscopy (SEM), Auger electron spectroscopy (AES) and X-ray Photoelectron Spectroscopy (XPS) measurements. By the multi-step annealing process, the specific contact resistance was decreased from 10−5 Ω cm2 level to 4–3 × 10−6 Ω cm2 and the surface morphology was improved. The AES measurements showed that the limitation indiffusion of Au and outdiffusion of Al were account for the surface morphology improvement and the surface Fermi level towards the conduction-band edge resulted in a lower specific contact resistance.

Preparation and characterization of solid n-TiO2/p-NiO hetrojunction electrodes for all-solid-state dye-sensitized solar cells

Abstract: Thin films of p-type nickel oxide (NiO) were prepared by a sol–gel spin deposition on ITO/TiO 2 to fabricate the photoelectrodes and all-solid-state dye-sensitized solar cells. The Ni(OH) 2 sol was formed from nickel (II) acetate tetrahydrate in a mixture of alcohol solution and poly(ethylene glycol), and followed by different heat treatments in air (350–800 °C). The formation and composition of NiO thin film was verified by EDX and X-ray diffraction (XRD) analysis, which shows preferred orientation along the (1 1 1) plane. The thickness of the NiO film calcined at 450 °C for 1 h is 120.6 nm with average grain size of 22 nm, and high UV transparency (∼75%) in the visible region is observed. The electrical properties of the sol–gel NiO films such as hole carrier concentration, sheet resistance and carrier mobility were examined using Hall measurement. Results show that the Hall mobility is dominated by the hole concentration. Furthermore, all-solid-state dye-sensitized solar cells comprising n-TiO 2 /p-NiO composite electrode were fabricated and the performance was evaluated. The current–voltage ( I – V ) characteristics of the composite TiO 2 /NiO electrode in dark demonstrate a good rectifying curve, verifying the p-type behavior of NiO films. Solar cells when sensitized with Ru-dye (N719) demonstrate short-circuit photocurrent ( I SC ) of 0.33 mA/cm 2 and open-circuit photovoltage ( V OC ) of 210 mV; the overall energy conversion efficiency of the device is about 0.025%.

A new compact subthreshold behavior model for dual-material surrounding gate (DMSG) MOSFETs

Abstract: On the basis of exact resultant solution of two-dimensional Poisson equation, a new compact subthreshold behavior model comprising two-dimensional potential, threshold voltage, subthreshold current and subthreshold swing for the dual-material surrounding gate (DMSG) MOSFETs is successfully developed. The model shows its validity by a good agreement with the simulated results from published device simulation software MEDICI. Besides offering the physical insight into device physics, the model provides the basic designing guidance for the DMSG MOSFETs.

A single-poly EEPROM cell for embedded memory applications

Abstract: We present a novel single-poly-silicon EEPROM cell for embedded memory. The cell is integrated in a 0.13 μm RF-CMOS technology without process modifications and is composed of an NMOS transistor and a MOS capacitor on two isolated P-wells sharing a floating poly-silicon layer. A two-polarity voltage of ±6 V is applied for writing and erasing using uniform-channel Fowler–Nordheim tunnelling. Operations faster than 1 ms, endurance over 10+3 cycles and data retention longer than 10 years are demonstrated.

High performance 70 nm gate length germanium-on-insulator pMOSFET with high-k/metal gate

Abstract: We demonstrate for the first time 70 nm gate length TiN/HfO 2 pMOSFETs on 200 mm GeOI wafers, with excellent performance: I ON = 260 μA/μm and I OFF = 500 nA/μm @ V d = −1.0 V (without germanide). These performance are obtained using adapted counterdoping and pocket implants. We report the best CV / I vs. I OFF trade-off for Ge or GeOI devices: CV / I = 4.4 ps, I OFF = 500 nA/μm @ V d = −1 V. Moreover, based on fine electrical characterizations ( μ , D it , R access , etc.) at T = 77–300 K, in-depth analysis of both ON and OFF states were carried out. Besides, calibrated TCAD simulations were performed to predict the performance enhancements which can be theoretically reached after further device optimization. By using germanide and reducing both interface state density and diode leakage we expect I ON = 450 μA/μm, I OFF = 100 nA/μm @ V d = −1 V for L g = 70 nm.

Simulation of self-heating effects in different SOI MOS architectures

Abstract: This paper discusses self-heating effects in different silicon-on-insulator architectures by 3D electro-thermal simulations. First of all, we compare different device architectures such as planar single- and double-gate transistors, as well as FinFETs. In the second part of the article, we focus on nanoscale FinFET devices and we study the dependence of self-heating on device-structure parameters such as buried oxide thickness, source/drain extension length, fin pitch and fin height. The electron transport model has been calibrated against Monte Carlo simulations at various temperatures. The results show that under stationary conditions the rise of temperature is not negligible, and self-heating severely impacts the device performance; however, its dependence on the geometrical parameters is weak.

Continuous model for independent double gate MOSFET

Abstract: This paper describes an explicit compact model of an independent double gate (IDG) MOSFET with an undoped channel. This model includes short channel effects and also mobility reduction, saturation velocity, series resistance and a charge model. It is applicable for symmetrical, asymmetrical and independent gate devices. The validity of this model is demonstrated by comparisons with ATLAS two-dimensional numerical simulations.

Effect of UV/ozone treatment on hysteresis of pentacene thin-film transistor with polymer gate dielectric

Abstract: Pentacene organic thin-film transistors (OTFTs) having acrylic polymer gate dielectric were fabricated with the change of UV/ozone treatment on the surface of gate dielectric. As UV/ozone exposure time increased, threshold voltage was shifted towards positive values from −0.7 V to 6.2 V and saturation mobility was dramatically increased from 0.07 cm 2 /Vs to 2.66 cm 2 /Vs while the amount of hysteresis was enlarged. The increase of hysteresis and the non-saturation behavior of output characteristics were attributed to the generation of hydroxyl groups through polymer dissociation during UV/ozone treatment because the hydroxyl groups making the surface of polymer gate dielectric more polar played as electron traps.

Parameter determination of Schottky-barrier diode model using differential evolution

Abstract: In this article, a new method, based on the differential evolution (DE) of determining the Schottky-barrier height, ideality factor and series resistance of Schottky-barrier diode (SBD) model using forward current–voltage ( I – V ) characteristics, is discussed. For the DE method, initial guesses close to the solutions are not required. It can combat the parameter determination problem of the SBD model based on a very broad range specified for each parameter. The performance of the proposed DE method is compared with other commonly used model parameter determination technologies, including genetic algorithm (GA), simulated annealing algorithm (SA), Nelder–Mead simplex search method (SM) and least squares technique (LS). The comparative result indicates that the DE method can obtain optimum solutions more easily than others.

Silicon nanowire FETs with uniaxial tensile strain

Abstract: We present experimental results on on-current and transconductance gain and mobility enhancement in Si nanowire FETs (NW-FETs) fabricated on silicon-on-insulator (SOI) and biaxially tensile strained SOI (SSOI). The Si NW-FETs show very high I on / I off -ratios of 10 7 and off-currents as low as 10 - 13 A . Inverse sub-threshold slopes of about 80 mV/dec for SOI n- and p-FETs and 65 mV/dec for strained SOI n-FETs were obtained. The on-current and transconductance of Si NW-nFETs fabricated on strained SOI substrates are 2.5 and 2.1 times larger, respectively, compared to identical devices on SOI due to uniaxial tensile strain along the wires. An electron mobility enhancement by a factor of 2.3 in uniaxial tensile strained NW-FETs was found. Moreover, the on-currents of n- and p-NW-FET are more symmetrical compared to planar devices, differing only by a factor of 1.6, for 〈 1 1 0 〉 NW channel direction on a (1 0 0) wafer.

Temperature dependence and thermal stability of planar-integrated enhancement/depletion-mode AlGan/GaN HEMTs and digital circuits

Abstract: We report detailed results on the temperature dependence and thermal stability of the planar-integrated enhancement/depletion-mode (E/D-mode) AlGaN/GaN high-electron mobility transistors (HEMTs). Compared to the standard mesa etching technique, the plasma treatment can achieve the same device isolation results. The E/D-mode HEMTs and the corresponding digital integrated circuits fabricated by the planar process exhibit stable operation from room temperature up to 350 °C. No degradation in device performance was observed after a 140-h thermal stress at 350 °C, implying excellent thermal stability of the planar process. The direct-coupled FET logic inverter, realized by planar-integration of E/D-mode HEMTs, presents larger noise margins (NMS) at high temperatures than the previously reported work, demonstrating promising potential for GaN-based high-temperature digital ICs. The NM improvement can be attributed to the higher threshold voltage and the improved gate turn-on voltage of the E-mode HEMTs that is achieved with larger plasma treatment dose.

Weak rectifying behaviour of p-SnS/n-ITO heterojunctions

Abstract: This work explores the electrical properties of p-SnS/n-ITO heterojunction at different temperatures The p-type SnS film was deposited on n-type ITO substrate using the thermal evaporation technique and its junction properties were studied using two probe method The as-grown p-n junction exhibited weak rectifying behaviour with a low Saturation current of the order of similar to 10(-6) A While increasing temperature, the saturation current of the junction is increased and however, its series resistance decreased At all temperatures the junction exhibited three types of transport mechanisms depending on applied bias-voltage At lower voltages the junction showed nearly ideal diode characteristics The junction behaviour with respect to bias-voltage and temperature is discussed with the help of existing theories and energy band diagram