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Showing papers in "Solid-state Electronics in 2011"


Journal ArticleDOI
TL;DR: In this paper, the successful integration of CBRAM technology into an industry standard logic process is described and functional operation of such a fully CMOS integrated CBRAM memory array is shown.
Abstract: One of the promising technologies under development for next generation non-volatile memory is the Conductive Bridging Random Access Memory (CBRAM) which utilizes the reversible switching of an electro-resistive dielectric between two conductive states as means of storing logical data [1–7] In this paper, we describe the successful integration of CBRAM technology into an industry standard logic process Moreover, we show functional operation of such a fully CMOS integrated CBRAM memory array and highlight its specific fundamental low power characteristics that make it suitable to be used in scaled embedded application as well as discrete devices

122 citations


Journal ArticleDOI
TL;DR: In this paper, the threading dislocation density (TDD) is decreased with increasing Ge thickness and further decayed by cyclic annealing process, which is shown to increase the surface roughness.
Abstract: Threading dislocation density as function of Ge thickness deposited with different annealing processes. AFM images of 4.7 μm thick Ge deposited without annealing process and Ge deposited with cyclic annealing process.► Smooth Ge layer growth on Si (100) surface without graded SiGe buffer is performed using RPCVD. ► Threading dislocation density (TDD) is decreased with increasing Ge thickness. ► TDD is decreased by postannealing and further decease is observed by cyclic annealing. ► TDD of 7×10 5 cm −2 without degrading surface roughness is achieved.

113 citations


Journal ArticleDOI
TL;DR: In this paper, thin-body tunneling field effect transistors (TFETs) built on SOI substrates with both SiO 2 and HfO 2 gate dielectrics are investigated.
Abstract: We report on thin-body tunneling field-effect transistors (TFETs) built on SOI substrates with both SiO 2 and HfO 2 gate dielectrics. The source–drain leakage current is suppressed by the introduction of an intrinsic region adjacent to the drain, reducing the electric field at the tunnel junction in the off state. We also investigate the temperature dependence of the TFET characteristics and demonstrate that the temperature-induced change in the Si bandgap is the main mechanism that determines the tunneling barrier and hence the drain current I D . We present a model of the TFET as a combination of a gated diode and a MOSFET, which can be solved analytically and can predict the experimentally measured I D over a wide range of drain and gate bias. Finally we report on the low frequency noise (LFN) behavior of TFETs, which unlike conventional MOSFETs exhibits 1/ f 2 frequency dependence even for large gate areas. This dependence indicates less trapping due to the much smaller effective gate length over the tunneling junction.

112 citations


Journal ArticleDOI
TL;DR: An optically transparent p-n heterojunction device consisting of p-NiO and n-ZnO thin films was fabricated by rf sputtering method as mentioned in this paper, which has an average transmittance of over 80% in the visible region.
Abstract: An optically transparent p–n heterojunction device consisting of p-NiO and n-ZnO thin films was fabricated by rf sputtering method The structural and optical properties of the p-NiO/n-ZnO heterojunction were characterized by X-ray diffraction (XRD), UV–visible spectroscopy, Hall effect measurement, and J–V photocurrent measurements The XRD shows that ZnO films are highly crystalline in nature with preferred orientation along the (0 0 0 2) direction The p-NiO/n-ZnO heterojunction device has an average transmittance of over 80% in the visible region The current–voltage curve of the heterojunction demonstrates obvious rectifying diode behavior in a dark environment The lowest leakage current is 664 × 10−8 A/cm2 for the p-NiO/n-ZnO heterojunction device

111 citations


Journal ArticleDOI
TL;DR: In this article, the reduction of I reset in NiO-based RRAM by controlling the filament size in 1 transistor-1 resistor (1T1R) cell devices is demonstrated to be scalable and controllable below 10μA.
Abstract: Resistive-switching memory (RRAM) is receiving a growing deal of research interest as a possible solution for high-density, 3D nonvolatile memory technology One of the main obstacle toward size reduction of the memory cell and its scaling is the typically large current I reset needed for the reset operation In fact, a large I reset negatively impacts the scaling possibilities of the select diode in a cross-bar array structure Reducing I reset is therefore mandatory for the development of high-density RRAM arrays This work addresses the reduction of I reset in NiO-based RRAM by control of the filament size in 1 transistor–1 resistor (1T1R) cell devices I reset is demonstrated to be scalable and controllable below 10 μA The significance of these results for the future scaling of diode-selected cross-bar arrays is finally discussed

107 citations


Journal ArticleDOI
TL;DR: In this paper, the formation and behavior of excess copper selenide (Cu 2− x Se) was studied and compared with typical copper-poor with that of copper-rich solar cells.
Abstract: Large-grain, copper-poor CuInGaSe 2 (CIGS) films are favored in the fabrication of highly efficient solar cells. However, the degradation of cell performance caused by residual copper selenide (Cu 2− x Se) remains a problem. This work studies the formation and behavior of excess Cu x Se and further compares the cell performance of typical copper-poor with that of copper-rich solar cells. Since excess Cu 2− x Se cannot be exhausted during the growth, it fully surrounds the polycrystalline CIGS grains. Excess Cu 2− x Se in the CIGS film produces serious shunt paths and causes the pn junction to be of poor quality. A short circuit in copper-rich CIGS solar cells is attributable to the conductive Cu 2− x Se. The best way to ensure high-efficiency of the cells is to exhaust Cu 2− x Se during growth. Otherwise, a dense, chemically treated CIGS film is required to prevent the negative effects of excess Cu 2− x Se.

95 citations


Journal ArticleDOI
TL;DR: In this article, a two-dimensional analytical model of single-gate silicon-on-insulator (SOI) tunneling field effect transistors (TFETs) is presented.
Abstract: This paper presents a two-dimensional analytical model of single-gate silicon-on-insulator (SOI) tunneling field-effect transistors (TFETs). Potential and electric field intensity calculated by Poisson’s equation are used to extract tunneling current values. The validity of the proposed model has been confirmed by comparing the analytical results with finite-element method (FEM) results.

91 citations


Journal ArticleDOI
Feng Xie1, Hai Lu1, Xiangqian Xiu1, Dunjun Chen1, Ping Han1, Rong Zhang1, Youdou Zheng1 
TL;DR: In this article, metal-semiconductor-metal ultraviolet photodetectors are fabricated on low-defect-density homoepitaxial GaN layer on bulk GaN substrate.
Abstract: Metal-semiconductor–metal ultraviolet photodetectors are fabricated on low-defect-density homoepitaxial GaN layer on bulk GaN substrate The dislocation density of the homoepitaxial layer characterized by cathodoluminescence mapping technique is ∼5 × 10 6 cm −2 The photodetector with a high UV-to-visible rejection ratio of up to 1 × 10 5 exhibits a low dark current of

89 citations


Journal ArticleDOI
TL;DR: In this paper, the authors investigated carbon-doped GeTe (GeTeC) as a novel material for phase-change memories (PCM) and reported very good data retention properties and reduction of RESET current.
Abstract: This paper investigates Carbon-doped GeTe (GeTeC) as novel material for Phase-Change Memories (PCM). In the first part of the manuscript, a study of GeTeC blanket layers is presented. Focus is on GeTeC amorphous phase stability, which has been studied by means of optical reflectivity and electrical resistivity measurements, and on GeTeC structure and composition, analyzed by XRD and Raman spectroscopy. Then, electrical characterization of GeTeC-based PCM devices is reported: resistance drift, data retention performances, RESET current and power, and SET time have been investigated. Very good data retention properties and reduction of RESET current make GeTeC suitable for both embedded and stand-alone PCM applications, thus suggesting GeTeC as promising candidate to address some of the major issues of today’s PCM technology.

74 citations


Journal ArticleDOI
TL;DR: In this paper, the HfO 2 high-k thin films have been deposited on p-type silicon wafer using RF magnetron sputtering technique and the XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively.
Abstract: The HfO 2 high-k thin films have been deposited on p-type (1 0 0) silicon wafer using RF magnetron sputtering technique. The XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively. The monoclinic structured, smooth surface HfO 2 thin films with 9.45 nm thickness have been used for Al/HfO 2 /p-Si metal–oxide–semiconductor (MOS) structures fabrication. The fabricated Al/HfO2/Si structure have been used for extracting electrical properties viz dielectric constant, EOT, barrier height, doping concentration and interface trap density through capacitance voltage and current–voltage measurements. The dielectric constant, EOT, barrier height, effective charge carriers, interface trap density and leakage current density are determined are 22.47, 1.64 nm, 1.28 eV, 0.93 × 10 10 , 9.25 × 10 11 cm −2 eV −1 and 9.12 × 10 −6 A/cm 2 respectively for annealed HfO 2 thin films.

73 citations


Journal ArticleDOI
TL;DR: Hartmann et al. as discussed by the authors presented an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness.
Abstract: After a long period of developing integrated circuit technology through simple scaling of silicon devices, the semiconductor industry is now embracing technology boosters such as strain for higher mobility channel material. Germanium is the logical supplement to enhance existing technologies, as its material behaviour is very close to silicon, and to create new functional devices that cannot be fabricated from silicon alone (Hartmann et al. (2004) [1]). Germanium wafers are, however, both expensive and less durable than their silicon counterparts. Hence it is highly desirable to create a relaxed high quality Ge layer on a Si substrate, with the provision that this does not unduly compromise the planarity of the system. The two temperature method, proposed by Colace et al. (1997) [2], can give smooth (RMS surface roughness below 1 nm) and low threading dislocation density (TDD <10(8) cm(-2)) Ge layers directly on a Si(0 0 1) wafer (Halbwax et al. (2005) [3]), but these are currently of the order of 1-2 mu m thick (Hartmann et al. (2009) [4]). We present an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness. We report the effect of changing the thickness, of both the low temperature (LT) and the high temperature (HT) layers, emphasising the variation of TDD, surface morphology and relaxation. Within this study, the LT Ge layer is deposited directly on a Si(0 0 1) substrate at a low temperature of 400 degrees C. This low temperature is known to generate monolayer islands (Park et al. (2006) [5]), but is sufficiently high to maintain crystallinity whilst keeping the epitaxial surface as smooth as possible by suppressing further island growth and proceeding in a Frank-van der Merwe growth mode. This LT growth also generates a vast number of dislocations, of the order of 10(8)-10(9) cm(-2), that enable the next HT step to relax the maximum amount of strain possible. The effect of varying the HT layer thickness is studied by depositing on a LT layer of fixed thickness (100 nm) at a higher growth temperature of 670 degrees C. We find that the HT layer allows Ge-on-Ge adatom transport to minimise the surface energy and smooth the layer. The final step to the technique is annealing at a high temperature that allows the dislocations generated to glide, increasing the degree of relaxation, and annihilate. We find that annealing can reduce the TDD to the order of 10(7) cm(-2), but at a cost of a significantly roughened surface.

Journal ArticleDOI
Bo Yuan1, X. J. Zheng1, Yi Qiang Chen1, Bo Yang1, Tong Zhang2 
TL;DR: In this article, a photoconductive semiconductor switch (PCSS) based on ZnO single nanobelt (NB) was fabricated by controlling the concentration of mixed solution and using the probe technique, and applied into a test circuit to control the circuit state.
Abstract: Photoconductive semiconductor switch (PCSS) based on ZnO single nanobelt (NB) was fabricated by controlling the concentration of mixed solution and using the probe technique, and applied into a test circuit to control the circuit state. The current–voltage characteristics and voltage spectra were investigated by system source meter and oscillograph, and the results show that the PCSS is of high photosensitivity of ∼104, low dark current of ∼10−3 μA, low power consumption of ∼2.45 μW, typical rise time 0.12 s, and decay time 0.15 s. Within the wavelength range of 280–340 nm, the shorter the wavelength is, the higher the voltage response is. The test circuit state conversion between “1” and “0” is obviously corresponding to UV illumination “on” and “off”. The high photosensitivity and low dark current of PCSS can be reasonably explained by using the view point of light absorption and oxygen chemisorption mechanism.

Journal ArticleDOI
TL;DR: In this paper, the impact of process parameters on the electrical performance of complementary multiple-gate tunnel field effect transistors (MuGTFETs), implemented in a Multiple-Gate Field Effect Transistors (muGFETs) technology compatible with standard CMOS processing is investigated.
Abstract: We show the impact of process parameters on the electrical performance of complementary Multiple-Gate Tunnel Field Effect Transistors (MuGTFETs), implemented in a Multiple-Gate Field Effect Transistors (MuGFETs) technology compatible with standard CMOS processing. Firstly, we assess the impact of the gate oxide thickness on the tunneling performance. Secondly, we investigate the effect of the doping concentration and profile by implementing different doping conditions. Thirdly, three different annealing conditions are compared: spike anneal, sub-ms laser anneal and low temperature anneal for Solid Phase Epitaxy Regrowth (SPER). In case of SPER anneal a record drive current of 46 μA/μm at V DD of −1.2 V and I OFF of 5 pA/μm for Si pTFETs is reported. The enhanced current is given by the position of the silicide at the n+ side close to the gate. Silicide engineering opens a new opportunity to optimize tunnel devices.

Journal ArticleDOI
TL;DR: In this article, a thermally oxidized titanium chip was used to evaluate the properties of the TiO 2 -Ti and Ag-TiO 2-Ti structures at different biasing, thermal and atmospheric conditions.
Abstract: Ti–TiO 2 structure has been utilized in the fabrication of many TiO 2 -based devices such as solar cells, electrocatalytic electrodes and noble metal–TiO 2 –Ti chemical sensors. While the ohmic behaviour of Ti–TiO 2 is assumed in the description of many TiO 2 -based devices, direct experimental evaluation has not yet been carried out. We have fabricated Ti–TiO 2 –Ti and Ag–TiO 2 –Ti structures on a thermally oxidized titanium chip and assessed their electronic behaviours at different biasing, thermal and atmospheric conditions. The junction areas at the opposite sides of the Ti–TiO 2 –Ti structure were different and the linearity of the I–V characteristics of the structure, at both biasing directions, approved the ohmicity assumed. This was compared to the behaviour of Ag–TiO 2 junction which varied from a high energy barrier Schottky diode to an ohmic contact, depending on the composition of the surrounding atmosphere. It was established that the ionic current due to the field assisted silver ion migration in the forward biased device causes the behaviour of the Ag–TiO 2 junction to deviate from that of a Schottky diode.

Journal ArticleDOI
TL;DR: In this paper, expanded graphite (EG) was prepared and then used with 5B pencil-lead as counter electrodes for the DSSCs, and the overall conversion efficiency reached to highest value 7.7% (Jsc = 0.441mV, Voc = 6.637mV).
Abstract: A kind of new carbon material – expanded graphite (EG) was prepared and then used with 5B pencil-lead as counter electrodes for the DSSCs. The EG/pencil-lead products were discussed following five different weight ratios of 1:0, 1:1, 1:2, 2:1, and 0:1. And flake graphite was employed for comparison. Commercial P25 TiO2 adsorbing dye N719 was used as photoanode and ionic liquid was adopted as electrolyte to compose the cell. Using green light-emitting diode (525 nm, LED) as the light source, J–V curves were recorded using the Zahner Zennium CIMPS system based on an IM6x electrochemical workstation. When the mass ratio of the mixture was 1:1, the overall conversion efficiency of DSSCs reached to highest value 7.7% (Jsc = 0.441 mA cm−2, Voc = 683 mV, fill factor = 0.637) under green-light intensity.

Journal ArticleDOI
TL;DR: In this article, a straightforward non-invasive method is proposed to accurately evaluate the shunt resistance of an elementary cell of a photovoltaic module connected in an installed string without requiring prior knowledge of the parameters of the intrinsic diodes.
Abstract: A straightforward non-invasive method is proposed to accurately evaluate the shunt resistance of an elementary cell of a photovoltaic module connected in an installed string without requiring prior knowledge of the parameters of the intrinsic diodes. The approach relies on the measurement of the current–voltage characteristic of the whole string after intentionally shading the selected cell. Calibrated PSPICE simulations are employed to illustrate the method and test its reliability. As a case study, the shunt resistances of several cells belonging to a series array of 10 commercial panels are determined.

Journal ArticleDOI
TL;DR: In this article, the power spectral density (PSD) of low-frequency noise (LFN) in pentacene field-effect transistors was analyzed and the authors found that the trap densities in bottom contact (BC) devices were higher than in their top contact (TC) counterparts, in agreement with observations of a poorer crystal structure of BC devices, in particular.
Abstract: Measurements of power spectral density (PSD) of low-frequency noise (LFN) in pentacene field-effect transistors reveal the preponderance of a 1/f-type PSD behavior with the amplitude varying as the squared transistor gain and increasing as the inverse of the gate surface area. Such features impose an interpretation of LFN by carrier number fluctuations model involving capture/release of charges on traps uniformly distributed over the gate surface. The surface slow trap density extracted by the noise analysis is close to the surface states density deduced independently from static I(V) data, which confirms the validity of the proposed LFN interpretation. Further, we found that the trap densities in bottom-contact (BC) devices were higher than in their top-contact (TC) counterparts, in agreement with observations of a poorer crystal structure of BC devices, in the contact regions in particular. At the highest bias the noise originating from the contact resistance is also shown to be a dominant component in the PSD, and it is well explained by the noise originating from a gate-voltage dependent contact resistance. A gate area scaling was also performed, and the good scaling and the dispersion at the highest bias confirm the validity of the applied carrier number fluctuations model and the predominant contact noise at high current intensities.

Journal ArticleDOI
TL;DR: In this article, a sputtered Sm2O3 thin film was applied into a resistive random access memory (RAM) device, which exhibited a stable resistance ratio of about 2.5 orders after 104 cycling bias pulses and no degradation for retention characteristics monitored after an endurance test at 85°C.
Abstract: This study investigates a sputtered Sm2O3 thin film to apply into a resistive random access memory device. The proposed device exhibits a stable resistance ratio of about 2.5 orders after 104 cycling bias pulses and no degradation for retention characteristics monitored after an endurance test at 85 °C. The conduction mechanisms for low and high resistance states are dominated by ohmic behavior and trap-controlled space–charge limited current, respectively. The resistance switching is ascribed to the formation/rupture of conductive filaments.

Journal ArticleDOI
TL;DR: In this paper, a mobility analysis of the surface roughness scattering along the different interfaces of FinFET devices is presented using temperature dependent analysis of effective mobility, quantitative information about the influence of the roughness could be obtained directly on the device.
Abstract: This paper presents a mobility analysis of the surface roughness scattering along the different interfaces of FinFET devices. Using temperature dependent analysis of effective mobility, quantitative information about the influence of the roughness could be obtained directly on the device. The sidewall and top surface drain current components were estimated from the total drain currents of different fin width conditions. Using a conventional mobility model, it was possible to fit the gate voltage and temperature dependence of sidewall and top surface mobilities. This procedure allowed the contribution of the surface roughness scattering to be quantified with nondestructive characterization. Significant differences were observed for sidewalls and top surface. In the specific case under study, surface roughness scattering on sidewalls was about three times stronger than on top surface for n-channel FinFETs, whereas it remained similar for p-channel ones.

Journal ArticleDOI
TL;DR: In this paper, the authors investigated the temperature dependent behavior of a GaN HEMT under both small and large-signal conditions, and showed that thermal phenomena and traps are responsible for a marked self-heating effect, a slight threshold voltage shift, and an evident kink effect.
Abstract: The investigation of the DC and microwave characteristics versus the ambient temperature is a key issue for active solid-state devices, since the operating temperature can strongly affect not only the transistor performance but also its lifetime to failure. In light of the fact that such a study is of crucial importance especially for high-power devices, the present paper is focused on investigating the temperature dependent behavior of a GaN HEMT. This purpose is accomplished by analyzing measurements performed under different ambient temperatures at DC and microwave frequencies. The latter characterization is carried out under both small- and large-signal conditions. The results of this analysis show that thermal phenomena and traps are responsible for a marked self-heating effect, a slight threshold voltage shift, and an evident kink effect. The main benefit of the developed large-signal measurement system consists of allowing one to obtain not only the magnitude but also the phase spectra of all traveling voltage waves under realistic operating condition for different ambient temperatures. Hence, the thermal dependence of the time-domain waveforms can be investigated. The present analysis clearly shows that the thermal phenomena have a marked impact especially on the magnitude of the wave phasors.

Journal ArticleDOI
TL;DR: In this paper, a physical and explicit compact model for lightly doped FinFETs is presented, which is valid for a large range of silicon Fin widths and lengths, using only a very few number of model parameters.
Abstract: A physical and explicit compact model for lightly doped FinFETs is presented. This design-oriented model is valid for a large range of silicon Fin widths and lengths, using only a very few number of model parameters. The quantum mechanical effects (QMEs), which are very significant for thin Fins below 15 nm, are included in the model as a correction to the surface potential. A physics-based approach is also followed to model short-channel effects (roll-off), drain-induced barrier lowering (DIBL), subthreshold slope degradation, drain saturation voltage, velocity saturation, channel length modulation and carrier mobility degradation. The quasi-static model is then developed and accurately accounts for small-geometry effects as well. This compact model is accurate in all regions of operation, from weak to strong inversion and from linear to saturation regions. It has been implemented in the high-level language Verilog-A and exhibits an excellent numerical efficiency. Finally, comparisons of the model with 3D numerical simulations show a very good agreement making this model well-suited for advanced circuit simulations.

Journal ArticleDOI
TL;DR: An analytical compact model for the threshold voltage Vt of double-gate (DG) and tri-Gate (TG) FinFETs is proposed and the Vt model has been validated by developing a Verilog-A code and comparing the results derived by the Spectre simulator and the Verilogs A code with simulation results.
Abstract: In this work, an analytical compact model for the threshold voltage Vt of double-gate (DG) and tri-gate (TG) FinFETs is proposed. The DG FinFET Vt model is extended to TG FinFET Vt model using effective parameters capturing the electrostatic control of the top gate over the short-channel effects. The results of the model are compared with the results of a numerical device simulator for a wide range of the channel length, the fin height and the fin width. The overall results reveal the very good accuracy of the proposed model. The Vt model has been validated by developing a Verilog-A code and comparing the results derived by the Spectre simulator and the Verilog-A code with simulation results.

Journal ArticleDOI
TL;DR: In this paper, the degradation of the dark current of B-layer photodiodes is examined for 10min-long irradiation with 1-25 keV electron energies and stable performance is observed provided that the perimeter isolationoxide is not exposed.
Abstract: Silicon photodiodes for use as low-energy electron detectors have been fabricated using a pure-boron technology to form the p+-anode region. The diode I–V characteristics are ideal and uniform over the wafer with low dark currents in the range of 0.6 pA/mm2. An extremely small thickness of the front-entrance window dead layers was achieved for a 1.8 nm B-layer deposition at 700 °C. All other processing layers on the photosensitive surface were removed using selective wet-etching to the B-layer, a process which is studied here with respect to residues and pitting effects that can result from the etching of Al to the B-layer. For the most optimal photodiode, a high relative electron signal gain is obtained: 60% at 500 eV, and 74% at 1 keV. The degradation of the dark current of B-layer photodiodes is examined for 10-min-long irradiation with 1–25 keV electron energies and stable performance is observed provided that the perimeter isolation-oxide is not exposed.

Journal ArticleDOI
TL;DR: In this paper, a continuous and explicit model valid in all operating regions, for undoped short-channel cylindrical gate-all-around (GAA) MOSFETs, is presented.
Abstract: For the first time, a continuous and explicit model valid in all operating regions, for undoped short-channel cylindrical gate-all-around (GAA) MOSFETs, is presented in this study. From a two-dimensional analysis, the threshold voltage roll-off, the drain-induced barrier lowering (DIBL) and the subthreshold swing are explicitly modeled. Short-channel effects are then implemented into a continuous drain-current model based on an effective surface potential approach using the gradual channel approximation. Improving the model behavior in the saturation operating region by accounting the channel pinch-off displacement, channel length modulation is studied and implemented as well. Analytical results are compared to TCAD-Atlas numerical simulations and validate the short-channel model in all operating modes making it suitable for circuit design simulations.

Journal ArticleDOI
TL;DR: In this article, a normally-off n-channel AlGaN/GaN hybrid metal-oxide-semiconductor heterojunction field effect transistor (MOS-HFET) was fabricated on Si substrate with high field effect mobility.
Abstract: The paper reports a normally-off n-channel AlGaN/GaN hybrid metal–oxide–semiconductor heterojunction field-effect transistor (MOS-HFET) on Si substrate with high field-effect mobility. To decrease the channel resistance and to improve the field-effect mobility, of the MOS-HFET, a selective area growth (SAG) technique is applied at the channel region. The fabricated MOS-HFET exhibits a good normally-off operation with the threshold voltage of 3.7 V, the specific ON-state resistance of 7.6 mΩ cm2, and the breakdown voltage of over 800 V.

Journal ArticleDOI
TL;DR: In this paper, rare earth element La-doped ZnO polycrystalline films are prepared on Pt/Ti/SiO 2 /Si substrate and p -Si substrate by chemical solution deposition (CSD) method.
Abstract: Rare earth element La-doped ZnO polycrystalline films are prepared on Pt/Ti/SiO 2 /Si substrate and p -Si substrate by chemical solution deposition (CSD) method. High R OFF / R ON ratios, low operation voltages within 150 switching cycles of test and long retention measurement are obtained, which indicate that the two different structure devices exhibit reversible, controllable and remarkable reliability unipolar resistive switching (RS) behaviors. The RS mechanism is related to the different substrate of the samples. The filament theory and the interface effect are suggested to be responsible for the RS phenomenon for the Pt/Ti/SiO 2 /Si substrate and p -Si substrate, respectively.

Journal ArticleDOI
TL;DR: In this paper, the minimum switching time for both heating (on) and cooling (off) processes is explored using a simple resistance-capacitance thermal circuit model for two-terminal VO2 devices.
Abstract: Vanadium oxide undergoes a sharp metal-insulator transition in the vicinity of room temperature and there is considerable interest in exploring novel device applications that utilize this phase transition. Using experimentally determined values of the thermal conductivity across the metal-insulator transition in VO2 thin films, we estimate the switching characteristics of two-terminal VO2 devices. The minimum switching time for both heating (“on” state) and cooling (“off” state) processes is explored using a simple resistance-capacitance thermal circuit model. The estimated minimum switching time is on the order of ∼1 ns for 20 nm VO2 films which is comparable to experimentally observed switching times. Optimal operating temperatures to maximize switching times are estimated. Methods to further enhance the switching kinetics by device thickness, carrier doping/strain, interfacial thermal resistance and input thermal energy are discussed. The simulations are compared with a 3-D model for VO2 devices on Si substrates utilizing COMSOL. The results are of potential relevance to the emerging field of correlated oxide electronics with fast phase transitions.

Journal ArticleDOI
TL;DR: In this article, a series of poly(3hexylthiophene) (P3HT)/(6,6)-phenyl C60 butyric acid methyl ester (PCBM) bulk hetero-junction polymer solar cells were fabricated with different iodine (I2) doping concentrations.
Abstract: A series of poly(3-hexylthiophene) (P3HT)/(6,6)-phenyl C60 butyric acid methyl ester (PCBM) bulk hetero-junction polymer solar cells were fabricated with different iodine (I2) doping concentrations. The short circuit current density (Jsc) was increased to 8.7 mA/cm2 from 4 mA/cm2, meanwhile the open circuit voltage (Voc) was decreased to 0.52 V from 0.63 V when the iodine doping concentration is 5%. The optimized power conversion efficiency of polymer solar cells (PSCs) with iodine doping is about 1.51%, which should be attributed to the better charge carrier transport and collection, and the more photon harvesting due to the red shift of absorption peaks and the widened absorption range to the longer wavelength. The morphology and phase separation of polymer thin films were measured by atomic force microscopy (AFM). The phase separation of P3HT and PCBM has been distinctly increased, which is beneficial to the exciton dissociation. The photocurrent density of PSCs with iodine doping was increased compared with the PSCs without iodine doping under the same effective voltage.

Journal ArticleDOI
TL;DR: In this paper, an Ag/ZnO/Ag thin films representing metal/semiconductor/metal ultraviolet (UV) photodetectors were successfully prepared by RF magnetron sputtering.
Abstract: Ag/ZnO/Ag thin films representing metal/semiconductor/metal ultraviolet (UV) photodetectors were successfully prepared by RF magnetron sputtering. A UV light emitting diode was used as an illuminating source at 365 nm. The current–voltage characteristics of the device under UV illumination showed an enhancement in the forward current. Device modeling was carried out using impedance spectroscopy. The resistance of the device decreased as the light was switched from dark to UV. Moreover, the device showed further decrease in resistance at a bias voltage of up to 2 V.

Journal ArticleDOI
TL;DR: In this paper, the capacitance (C) −voltage (V) curve of the Al2O3/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C −V curve of HfO2/GaNs.
Abstract: AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors (MOSHFETs) with Al2O3 gate oxide which was deposited by atomic layer deposition (ALD) were fabricated and their performance was then compared with that of AlGaN/GaN MOSHFETs with HfO2 gate oxide. The capacitance (C)–voltage (V) curve of the Al2O3/GaN MOS diodes showed a lower hysteresis and lower interface state density than the C–V curve of the HfO2/GaN diodes, indicating better quality of the Al2O3/GaN interface. The saturation of drain current in the ID–VGS relation of the Al2O3 AlGaN/GaN MOSHFETs was not as pronounced as that of the HfO2 AlGaN/GaN MOSHFETs. The gate leakage current of the Al2O3 MOSHFET was five to eight orders of magnitude smaller than that of the HfO2 MOSHFETs.