Showing papers in "Solid-state Electronics in 2012"
TL;DR: In this article, the Raman spectroscopy was used to monitor the quality of graphene films transferred onto SiO 2 /Si substrates and the dependence of the sensing response with the operating temperature was studied.
Abstract: Ammonia gas sensing behavior of graphene synthesized by CVD on copper substrate using a methane and hydrogen gas mixture was investigated. The Raman spectroscopy was used to monitor the quality of graphene films transferred onto SiO 2 /Si substrates. The sensitivity and the recovery time of the device were enhanced by the deposition of gold nanoparticles on the surface of graphene films. The dependence of the sensing response with the operating temperature was studied. The adsorption and desorption curves were analyzed using Langmuir kinetic theory and Freundlich isotherm for the adsorption of ammonia gas. The activation energy and the heat of adsorption were estimated to be around 38 and 41 meV, respectively for NH 3 gas concentration of 58 ppm at room temperature.
172 citations
TL;DR: In this article, the influence of the design parameters on the ambipolar current (IAMB) of the tunnel field effect transistors (TFETs) has been investigated using numerical device simulations, showing that the IAMB is reduced progressively by underlapping the gate and the drain, by using low-k spacers and by placing the contacts in the top and bottom configuration.
Abstract: This work presents a study on the influence of the design parameters on the ambipolar current (IAMB) of the Tunnel Field Effect Transistors (TFETs). Using numerical device simulations, IAMB is reduced progressively by underlapping the gate and the drain, by using low-k spacers and by placing the contacts in the top and bottom configuration. It is explained that a structure with top and bottom contacts leads to the field distribution inside the drain spacer, limiting the ambipolar current through the device. A TFET structure with ultra-low ambipolar current, totally independent of the gate voltage, is obtained by combining the layout of top and bottom contacts with low-k spacers. The scaling of the Silicon (Si) TFET is limited by the length of the drain spacer that cannot be scaled beyond a minimal limit without increasing IAMB to undesired high values.
169 citations
TL;DR: In this paper, the femtosecond-fast transport in metal-insulator-metal (MIM) tunnel diodes makes them attractive for applications such as ultra-high frequency rectenna detectors and solar cells, and mixers.
Abstract: The femtosecond-fast transport in metal–insulator–metal (MIM) tunnel diodes makes them attractive for applications such as ultra-high frequency rectenna detectors and solar cells, and mixers. These applications impose severe requirements on the diode current–voltage I ( V ) characteristics. For example, rectennas operating at terahertz or higher frequencies require diodes to have low resistance and adequate nonlinearity. To analyze and design MIM diodes with the desired characteristics, we developed a simulator based on the transfer-matrix method, and verified its accuracy by comparing simulated I ( V ) characteristics with those measured in MIM diodes that we fabricated by sputtering, and also with simulations based on the quantum transmitting boundary method. Single-insulator low-resistance diodes are not sufficiently nonlinear for efficient rectennas. Multi-insulator diodes can be engineered to provide both low resistance and substantial nonlinearity. The improved performance of multi-insulator diodes can result from either resonant tunneling or a step change in tunneling distance with voltage, either of which can be made to dominate by the appropriate choice of insulators and barrier thicknesses. The stability of the interfaces in the MIIM diodes is confirmed through a thermodynamic analysis.
143 citations
TL;DR: In this article, the junctionless tri-gate transistor with a gate length of 20-nm showed excellent electrical characteristics with a high Ion/Ioff ratio (>106), good sub-threshold slope (∼79mV/dec), and low drain-induced barrier lowering.
Abstract: We have fabricated n-channel junctionless nanowire transistors with gate lengths in the range of 20–250 nm, and have compared their electrical performances with conventional inversion-mode nanowire transistors. The junctionless tri-gate transistor with a gate length of 20 nm showed excellent electrical characteristics with a high Ion/Ioff ratio (>106), good subthreshold slope (∼79 mV/dec), and low drain-induced barrier lowering (∼10 mV/V). The simpler fabrication process without junction formation results in improved short-channel characteristics compared to the inversion-mode devices, and also makes the junctionless nanowire transistor a promising candidate for sub 22-nm technology nodes.
138 citations
TL;DR: In this paper, a simple and inexpensive way for the preparation of highly transparent ZnO thin films and their application as active layer in UV ray sensor devices was reported. But this method is not suitable for the case of high temperature.
Abstract: We report a simple and inexpensive way for the preparation of highly transparent ZnO thin films and their application as active layer in UV ray sensor devices. ZnO thin films were deposited on glass substrates by thermal evaporation of pure ZnO powder. The as-deposited films were then annealed at different temperatures (100, 200, 300 and 400 °C) for various time durations (5, 15, 25 and 35 min) to make optically transparent in the visible region. The films annealed at 300 °C for 15 min show very good visible transparency and other material properties. These films were used as the active material for Ag/ZnO/Ag UV sensor devices. The sensor devices are photo conductive type and only sensitive in the UV region of the electromagnetic spectrum. Maximum photo-current gain of the UV sensor device is ∼2. Possible sensing mechanism has been discussed.
114 citations
TL;DR: In this article, a physics-based compact model for drain current I d and intrinsic gate-drain and gate-source capacitances C GS and C GD in AlGaN/GaN high electron mobility transistors is presented.
Abstract: In this paper we present a physics-based compact model for drain current I d and intrinsic gate–drain and gate–source capacitances C GS and C GD in AlGaN/GaN high electron mobility transistors. An analytical expression for the 2-DEG charge density n s , valid in all the regions of device operation is developed and applied to derive current and capacitances. The drain current model includes important physical effects like velocity saturation, channel length modulation, short channel effect, mobility degradation effect, and self-heating. The expression for n s is used to derive a model for C GS and C GD applicable in all the regions of device operation. The parameters introduced in the model have a clear link to the physical effects facilitating easy extraction of parameter values. The model is in excellent agreement with experimental data for both drain current and capacitances over a typical range of applied voltages and device geometries.
100 citations
TL;DR: In this article, a novel tunnel field effect transistor (TFET) concept called the electron-hole bilayer TFET (EHBTFET), which exploits the carrier tunneling through a bias-induced electron hole bilayer in order to achieve improved switching and higher drive currents, was proposed.
Abstract: We propose a novel tunnel field-effect transistor (TFET) concept called the electron–hole bilayer TFET (EHBTFET). This device exploits the carrier tunneling through a bias-induced electron–hole bilayer in order to achieve improved switching and higher drive currents when compared to a lateral p–i–n junction TFET. The device principle and performances are studied by 2D numerical simulations. Output and transfer characteristics, as well as the impact of back gate bias, silicon thickness and gate length on the device behavior are evaluated. Device performances are compared for Si and Ge implementations. Nearly ideal average subthreshold slope (SSavg ∼ 10 mV/dec over 7 decades of current) and Ion/Ioff > 10^8 at Vd = Vg = 0.5 V are obtained, due to the OFF–ON binary transition which leads to the abrupt onset of the band-to-band tunneling inside the semiconductor channel. Remarkably, for Ge EHBTFETs the Ion (∼11 μA/μm at Vdd = 0.5 V) is 10× larger than in Ge tunnel FETs and 380× larger than in Si EHBTFETs.
88 citations
TL;DR: In this paper, the μ-Czochralski process based on a pulsed-laser crystallization was used to form Si TFTs with a diameter of 6μm.
Abstract: Monolithic 3D integration is the ultimate approach in 3D-ICs as it provides high-density and submicron vertical interconnects and hence transistor level integration. Here, high-quality Si layer formation at a low temperature is a key challenge. We review our recent achievements in monolithic 3D-ICs based on single-grain Si TFTs that are fabricated inside a single-grain with a low-temperature process. With the μ-Czochralski process based on a pulsed-laser crystallization, Si grains with a diameter of 6 μm are successfully formed on predetermined positions. Single-grain (SG) Si TFTs are fabricated inside the single-grain with mobility for electron and holes of 600 cm 2 /V s and 200 cm 2 /V s, respectively. Two layers of the SG Si TFT were vertically stacked and successfully implemented into CMOS inverter, 3D 6T-SRAM and single-grain lateral PIN photo-diode with in-pixel amplifier. Those results indicate that the SG TFTs are attractive for use in monolithic 3D-ICs on an arbitrary substrate including a glass and even a plastic for applications such as ultra-high-density memories, logic-to-logic integration, CPU integrated display, and high-definition image sensor for artificial retina.
84 citations
TL;DR: In this paper, the authors report on ultrahigh sensitive, broadband terahertz (THz) detectors based on asymmetric dual-grating-gate (A-DGG) high electron mobility transistors, demonstrating a record responsivity of 2.2 kV/W at 1.2 THz with a superior low noise equivalent power of 15 pW/√Hz using InGaAs/InAlAs/INP material systems.
Abstract: We report on ultrahigh sensitive, broadband terahertz (THz) detectors based on asymmetric dual-grating-gate (A-DGG) high electron mobility transistors, demonstrating a record responsivity of 2.2 kV/W at 1 THz with a superior low noise equivalent power of 15 pW/√Hz using InGaAs/InAlAs/InP material systems. When THz radiation is absorbed strong THz photocurrent is first generated by the nonlinearity of the plasmon modes resonantly excited in undepleted portions of the 2D electron channel under the high-biased sub-grating of the A-DGG (as a quadratic nature of the product of local carrier density and velocity perturbations), then the THz photovoltaic response is read out at high-impedance parts of 2D channel under the other sub-grating biased at the level close to the threshold. Extraordinary enhancement by more than two orders of magnitude of the responsivity is verified with respect to that for a symmetric DGG structure.
74 citations
TL;DR: The Z2-FET as mentioned in this paper is a field effect transistor with a single front gate built on a fully depleted silicon-on-insulator substrate that possesses extremely steep switching slope and gate-controllable hysteresis.
Abstract: We experimentally demonstrate a field-effect transistor with a single front gate built on fully-depleted silicon-on-insulator substrate that possesses extremely steep switching slope (≪1 mV/decade) and gate-controllable hysteresis. The mechanism for the sharp switching, confirmed by simulations, involves the positive feedback between the gate-modulated charge injection barriers and the electron and hole components of the source–drain current. The transistor is named Z2-FET as it features zero impact ionization (unlike thyristors) and zero subthreshold swing.
64 citations
TL;DR: In this article, experimental and theoretical studies have been conducted to determine the effects of phosphorous as a passivating agent for the SiO 2 /4H-SiC interface Annealing in a P 2 O 5 ambient converts the siO 2 layer to PSG (phosphosilicate glass) which is known to be a polar material.
Abstract: We describe experimental and theoretical studies to determine the effects of phosphorous as a passivating agent for the SiO 2 /4H–SiC interface Annealing in a P 2 O 5 ambient converts the SiO 2 layer to PSG (phosphosilicate glass) which is known to be a polar material Higher mobility (approximately twice the value of 30–40 cm 2 /V s obtained using nitrogen introduced with an anneal in nitric oxide) and lower threshold voltage are compatible with a lower interface defect density Trap density, current–voltage and bias-temperature stress (BTS) measurements for MOS capacitors are also discussed The BTS measurements point to the possibility of an unstable MOSFET threshold voltage caused by PSG polarization charge at the O–S interface Theoretical considerations suggest that threefold carbon atoms at the interface can be passivated by phosphorous which leads to a lower interface trap density and a higher effective mobility for electrons in the channel The roles of phosphorous in the passivation of correlated carbon dangling bonds, for SiC counter-doping, for interface band-tail state suppression, for Na-like impurity band formation and for substrate trap passivation are also discussed briefly
TL;DR: In this article, the authors report on the process integration of vertical silicon tunnel FETs and analyze the impact of process and geometrical parameters on the device behavior, especially when the overlap is marginal.
Abstract: We report on the process integration of vertical silicon Tunnel FETs (TFETs) and analyze the impact of process and geometrical parameters on the device behavior. The gate–source overlap is shown to be a critical parameter, especially when the overlap is marginal. The temperature dependence also suggests that trap-assisted tunneling injection mechanism is at the origin of the degraded onset characteristic of the vertical TFET, likely due to a large interface trap density and that improvement in the passivation of the surface of the vertical nanowires should be beneficial.
TL;DR: In this article, a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height is presented with the adoption of Siconi™ Selective Material Removal (SMR) in the fabrication flow.
Abstract: This work presents a process to fabricate Bulk FinFETs with advancements in critical fabrication steps such as the shallow trench oxide recess and the adjustment of the fin height. These steps are accomplished with the adoption of Siconi™ Selective Material Removal (SMR™) in the fabrication flow. FinFETs obtained with this new integration scheme were tested in a co-fabrication process flow proposed to integrate planar CMOS and Bulk FinFETs on the same wafer. Morphological and electrical results indicate perfectly filled trenches, a better fin height control and a Bulk FinFET static performance similar to planar CMOS. The 20 nm wide fins are fabricated using 193 nm illumination lithography followed by a series of trimming steps during the trench etching, the filling and a fin re-oxidation during the steam densification of the trench filling oxide. Trench depth is 300 nm and the electrically active fin height is 40 nm.
TL;DR: In this article, the temperature impact on the off-state current components is analyzed through numerical simulation and experimentally, and the results show that at high temperature, an unexpected offstate current occurred due to the thermal leakage current through the drain/channel junction.
Abstract: In this work, the temperature impact on the off-state current components is analyzed through numerical simulation and experimentally. First of all, the band-to-band tunneling is studied by varying the underlap in the channel/drain junction, leading to an analysis of the different off-state current components. For pTFET devices, the best behavior for off-state current was obtained for higher values of underlap (reduced BTBT) and at low temperatures (reduced SRH and TAT). At high temperature, an unexpected off-state current occurred due to the thermal leakage current through the drain/channel junction. Besides, these devices presented a good performance when considering the drain current as a function of the drain voltage, making them suitable for analog applications.
TL;DR: In this article, an analysis of low-frequency noise in n-channel and p-channel MOSFETs, with high-k gate stack and channel length varying from 1.8μm down to 26.4nm, has been carried out.
Abstract: Extensive investigation of the low-frequency noise in n-channel and p-channel MOSFETs, with high-k gate stack and channel length varying from 1.8 μm down to 26.4 nm, has been carried out. The results demonstrate that the carrier number fluctuation with correlated mobility fluctuations describes accurately and continuously the 1/f noise for all operation regions, i.e. from weak to strong inversion and from linear to saturation. It has been found that the product of the Coulomb scattering coefficient and the effective carrier mobility α sc μ eff is constant over a wide range of the drain current due to the interplay of the Coulomb scattering coefficient αsc and the effective carrier mobility μeff variations. In addition, a non-linear increase in the square root of the input gate voltage noise with the gate voltage overdrive was observed explained by the surface roughness scattering. The overall results lead to an analytical expression for the 1/f noise model, enabling to predict the noise level of a transistor with any channel dimensions using its transfer characteristic. This finding makes the noise model suitable for circuit simulation tools.
TL;DR: Schottky barrier field effect transistors (SB FETs) with Schottky source injection barrier contacts are fabricated using zinc oxide (ZnO) thin films deposited by pulsed laser deposition at room temperature.
Abstract: Schottky barrier field effect transistors (SB FETs) with Schottky source injection barrier contacts are fabricated using zinc oxide (ZnO) thin films deposited by pulsed laser deposition at room temperature. In these devices, we utilize a gold Schottky barrier for the source and an aluminum ohmic metal for the drain contacts. The transistors exhibit field effect mobilities as high as 0.1 cm 2 V −1 s −1 , a current on/off ratio of 10 5 , and a low saturation voltage of 6 V. When using ohmic source and drain contacts, transistor characteristics are not observed. Furthermore, the devices’ transconductance- and capacitance–voltage characteristics show a transition in the dominant carrier injection mechanism at the source barrier from thermionic emission to tunneling at a gate bias of approximately 8 V. These results demonstrate the promise of the Schottky source barrier FET architecture for building ZnO-based transistors.
TL;DR: In this article, as-synthesized nanoparticles and nanosheets are characterized by X-ray powder diffraction (XRD) and scanning electron microscopy (SEM).
Abstract: SnO2 nanosheets were synthesized by a hydrothermal method at 200 °C using stannic chloride hydrate and sodium hydroxide as starting materials. The as-synthesized nanoparticles and nanosheets are characterized by X-ray powder diffraction (XRD) and scanning electron microscopy (SEM). The gas response, selectivity, and response speed were optimized by varying the morphology of the sensing materials and operation temperature. Most importantly, the SnO2 nanosheets sensor exhibits high response, low detection limit and fast response to ethanol. The gas response of the SnO2 nanosheets to 100 ppm ethanol was 39.6 at 300 °C, which was 3.6 and 6.1 times higher than that of the nanospheres-like and the nanoparticles, respectively. Response and recovery times were 1 and 9 s when the sensor was exposed to 20 ppm ethanol at an operating temperature of 300 °C.
TL;DR: This study uses a combination of ab initio calculations and molecular dynamics simulations and analyzes the molecule behavior when specific electric fields are applied to move the electrons inside the molecule in order to force a logic state.
Abstract: Among emerging beyond CMOS technologies Molecular Quantum Dot Cellular Automata (MQCA) are estimated as extremely promising for computational purposes. The elementary nanoelectronic devices are molecular systems in which the binary encoding is provided by the charge localization within a molecule. As a consequence, there is no current flowing among the cells and power dissipation is dramatically reduced. We study a new real molecule that was synthesized ad hoc for this technology. Differently with respect to previous contributions, this study has the aim of assessing the realistic properties of this molecule in a perspective experimental system based on a molecular wire principle. We use a combination of ab initio calculations and molecular dynamics simulations and analyze the molecule behavior when specific electric fields are applied to move the electrons inside the molecule in order to force a logic state. Our results allowed us (i) to asses the molecule behavior and to explore the working points of our experimental system for the write-in, (ii) to introduce in this scenario new metrics for studying and using these new devices from an electronic point of view, (iii) to give a perspective and to define design constraints for possible experimental solutions eligible for issue of molecule state read-out.
TL;DR: UTBB is a promising contender for analog applications, exhibiting high maximum transconductance, drive current, intrinsic gain and achievable cut-off frequencies in the range of 150-220 GHz.
Abstract: In this paper, we analyze, for the first time to our best knowledge, the perspectives of ultra-thin body and ultra-thin BOX (UTBB) SOI CMOS technology for analog applications. We show that UTBB is a promising contender for analog applications, exhibiting high maximum transconductance, drive current, intrinsic gain and achievable cut-off frequencies in the range of 150-220 GHz. Effect of operation regime, substrate bias, channel width and high temperature (up to 250 °C) on analog figures-of-merit (FoM) are analyzed. Benchmarking of UTBB with other technologies (as planar FD SOI, different FinFETs, UTB with thick BOX) is presented.
TL;DR: In this article, the correlation between the crystallinity of reactively sputtered Nb 2 O 5 layers on Pt bottom electrode and their resistive switching behavior was investigated, and it was found that the amorphous phase can be transformed to an orthorhombic phase by annealing in argon at 650°C.
Abstract: In this paper, the correlation between the crystallinity of reactively sputtered Nb 2 O 5 layers on Pt bottom electrode and their resistive switching behavior was investigated. It was found that the amorphous phase can transformed to an orthorhombic phase by annealing in argon at 650 °C. Smooth surfaces of the crystalline samples with RMS roughness of 1 nm were produced. By using the stack Al/Nb 2 O 5 /Pt a Schottky diode was produced and a barrier height of 1.0 eV for the argon annealed sample was found. For the amorphous sample, a Frenkel–Poole emission mechanism was found with the activation energy of 0.21 eV. After an electric forming process a filamentary resistive switching was observed for both types of samples.
TL;DR: In this paper, the impact of lateral charge migration on the retention performance of charge-trap memories whose storage layer is not patterned self-aligned with the channel area of each cell was investigated.
Abstract: This paper investigates the impact of lateral charge migration on the retention performance of charge-trap memories whose storage layer is not patterned self-aligned with the channel area of each cell. Experimental results on planar SONOS devices reveal an important contribution of lateral charge migration at 150 °C and are used to calibrate a new numerical model accounting for both the vertical and the lateral charge loss from the silicon nitride. This new model was used to simulate 3D vertical SONOS devices, where multiple cells are stacked in a cylindrical structure and process constrains the adoption of a self-aligned charge storage layer. A string of three cells and two select transistors has been simulated, evaluating, for different channel length and temperatures, the impact on string operations of the charge migrating in the nitride located between different gates.
TL;DR: In this paper, ternary system hybrid solar cells that are composed of CdSe nanodots, poly (3-hexylthiophene) (P3HT) and phenyl-C61-butyric acid methyl ester (PCBM) with an inverted structure were investigated.
Abstract: Ternary system hybrid solar cells that are composed of CdSe nanodots, poly (3-hexylthiophene) (P3HT) and phenyl-C61-butyric acid methyl ester (PCBM) with an inverted structure were investigated. The incorporation of 10 wt% CdSe nanodots showed increased power conversion efficiency (PCE) of 3.05% compared with that of a binary system with P3HT and PCBM, which is comparable with the best reported efficiency of nanocrystal based solar cells. The photophysical energy level of inverted structure and electrochemical, optical properties and microscopy images of the ternary systems were systematically investigated to elucidate the mechanism. The obtained hybrid solar cell showed enhanced stability through exposure in ambient condition without any encapsulation.
IBM1
TL;DR: In this article, a self-aligned gate-first implant-free access region for indium gallium arsenide (In 0.53 Ga 0.47 As) MOSFETs is investigated.
Abstract: CMOS compatible self-aligned access regions for indium gallium arsenide (In 0.53 Ga 0.47 As) implant-free n-type metal oxide semiconductor eld effect transistors (MOSFETs) are investigated. In situ doped n+source/drain regions are selectively grown by metal-organic vapor phase epitaxy and self-alignedNickel InGaAs alloyed metal contacts are obtained using a self-aligned silicide-like process, where differ-ent process conditions are studied. Soft pre-epitaxy cleaning is followed by X-ray photoelectron spectros-copy, while the Ni InGaAs/III V interface is characterized by back-side SIMS proling. Relevant contactand sheet resistances are measured and integration issues are highlighted. Gate-rst implant-free self-aligned n-MOSFETs are produced to quantify the impact of Ni InGaAs contacts on the deviceperformance. 2012 Elsevier Ltd. All rights reserved. 1. IntroductionDue to their higher injection velocity, III V compound semicon-ductors and in particular indium gallium arsenide (InGaAs) arebeing studied as possible candidates to replace Si as the channelmaterial in metal oxide semiconductor eld-effect-transistors(MOSFETs) for digital logic applications. Several challenges haveto be tackled to benet from the III Vs superior transport proper-ties and achieve a high drain current performance. Achieving lowresistance self-aligned source/drain access regions suitable forhigh-performance logic at 10 nm node and beyond is one of themost critical challenges. These contacts have to be highly compat-ible with standard CMOS ows, scalable to the small-pitch require-ments and thermally stable to stand the back-end process.Several approaches have been tried such as ion implantationwhich has shown its limits due to the too high thermal budget re-quired to achieve a decent S/D dopant activation[1]. Selective epi-taxy of in situ doped InGaAs S/D regions has been done bymolecular beam epitaxy (MBE)[2] and metal-organic vapor phaseepitaxy (MOVPE) [3], achieving a high carrier density in a self-aligned gate-rst scheme. These two approaches require a III Vcleaning recipe which includes a wet etch down to an etch-stoplayer before regrowth. Etching the channel material prior to S/Dformation is not an option in the case of fully-depleted types ofarchitectures like extremely-thin compound semiconductor oninsulator (ETCSOI).Low contact resistance and self-aligned molybdenum (Mo)metal contacts have been demonstrated using a height-selectiveetching process[4]. However, this process might be difcult tomanufacture over large wafer size on scaled devices. A salicide-like(self-aligned silicide) process on III V has been developed using aNickel InGaAs (Ni InGaAs) alloy integrated in a metallic S/D n-MOSFET[5,6] which suffers from a high off-state drain currentdue to the absence of a channel-to-S/D p n junction.In this work we report on a CMOS compatible process ow toachieve self-aligned implant-free access regions for In
TL;DR: In this article, a high temperature selenization and in situ annealing process was developed to improve the optoelectronic quality and increase the band gap at the surface of the CIGS absorber.
Abstract: Cu(In 1− x Ga x )Se 2 (CIGS) thin film have been fabricated by a 2-step process using Cu–In–Ga precursors and H 2 Se gas. A high temperature selenization and in situ annealing process was developed to improve the optoelectronic quality and increase the band gap at the surface of the CIGS absorber. Characterization with SEM and XRD showed the films had large grain size and improved crystallinity. SIMS and PL analysis showed the Ga content at the surface of the absorber was increased and the band gap was higher. Completed solar cells showed V oc increase resulted from more than one order of magnitude decrease in the saturation current compared to cells selenized at lower temperature. A high V oc of 623 mV was achieved and the best cell had conversion efficiency exceeding 15%.
TL;DR: In this article, the authors describe a novel thermal characterization method of GaN-based Light Emitting Diode (LED) package driven under the Alternating Current (AC) mode.
Abstract: In this paper we describe a novel thermal characterization method of GaN-based Light Emitting Diode (LED) package driven under the Alternating Current (AC) mode. The result was compared with the results from the thermal analysis for LED package operated under the Direct Current (DC) condition. Different from the DC condition, the junction temperature rise with the operation time of LED package was exhibited in a band formation. Finite Volume Method (FVM) was utilized to calculate the thermal performance of LED package under the AC condition using the input power extracted from the output current and voltage from the AC power supply. The experimental result was in a good agreement with the simulation data.
TL;DR: In this paper, the frequency variation of the output conductance in ultra-thin body with ultra thin BOX (UTBB) SOI MOSFETs without a ground plane is studied through measurements and two-dimensional simulations.
Abstract: The frequency variation of the output conductance in ultra-thin body with ultra-thin BOX (UTBB) SOI MOSFETs without a ground plane is studied through measurements and two-dimensional simulations. Two effects causing the output conductance variation with frequency, namely self-heating and source-to-drain coupling through the substrate, are discussed and qualitatively compared. Notwithstanding the use of ultra-thin BOX, which allows for improved heat evacuation from the channel to the Si substrate underneath BOX, a self-heating-related transition clearly appears in the output conductance frequency response. Furthermore, the use of an ultra thin BOX results in an increase of the substrate-related output conductance variation in frequency. As a result, the change in output conductance of UTBB MOSFETs caused by the substrate effect appears to be comparable and even stronger than the change due to self-heating.
TL;DR: In this paper, the authors report on the fabrication and characterization of voltage configurable nanowire field effect transistors (NWFET) devices suitable to broaden the flexibility in circuit design, e.g. for reconfigurable logic.
Abstract: In this paper, we report on the fabrication and characterization of voltage configurable nanowire field-effect-transistor (NWFET) devices suitable to broaden the flexibility in circuit design, e.g. for reconfigurable logic. Silicon NW-structures with mid-gap Schottky source and drain (S/D) junctions on silicon-on-insulator (SOI) substrate have been fabricated as unipolar complementary metal–oxide–semiconductor (CMOS) transistors. The desired device type, i.e. NMOS or PMOS, is selected by applying an appropriate back-gate bias. The programming capabilities of the devices fabricated using this approach are demonstrated experimentally using a freely configurable CMOS-NWFET inverter circuit on a MultiSOI-substrate like set-up.
TL;DR: In this paper, an electrical compact model for graphene FET device is proposed, where a trap model is introduced and the equivalent circuit is improved, and the model has been verified by comparison to DC and AC measurements versus bias and frequency on an advanced GFET having a transit frequency of about 10 GHz.
Abstract: An electrical compact model for graphene FET device is proposed. Starting from Meric’s compact model, a trap model is introduced and the equivalent circuit is improved. We show that traps have an effect on the transconductance and influence consequently most figures of merit in circuit design. The model has been verified by comparison to DC and AC measurements versus bias and frequency on an advanced GFET having a transit frequency of about 10 GHz. Then, the compact model has been used to evaluate the transistor in a circuit context. A LNA has been designed and despite the poor voltage gain of the GFET, the LNA shows interesting performances when input and output matching of the circuit is performed. A power gain of |S21| = 4.2 dB is obtained, the reverse isolation is about |S12| = −10.6 dB, the Rollet stability factor K is 1.25 and the noise figure is 3.9 dB at 800 MHz.
TL;DR: In this paper, the authors investigated the resistive switching properties of a memory device in an IrO x /TaO x/WO x, and proposed a model based on oxygen ions migration.
Abstract: Resistive switching properties of a memory device in an IrO x /TaO x /WO x /W structure have been investigated. High-resolution transmission electron microscopy image has shown the formation of a bilayer structure of TaO x /WO x which is further confirmed by energy dispersive X-ray spectroscopy and X-ray photo-electron spectroscopy analyses. The underlying switching mechanism is successfully explained by providing various electrical measurements such as device area dependency on set/reset voltage and low resistance state. A model based on oxygen ions migration is then proposed. Cumulative probability plots of essential memory parameters such as set/reset voltage and LRS/HRS show good distribution. The device has shown excellent read endurance of >10 5 times and data retention of >10 4 s with a resistance ratio of >10 2 at 85 °C.
TL;DR: In this paper, GeO 2 has been used as an interfacial layer for high- κ gate stacks on germanium MOSFETs to minimize GeO volatilisation.
Abstract: Germanium is an attractive channel material for MOSFETs because of its higher mobility than silicon In this paper, GeO 2 has been investigated as an interfacial layer for high- κ gate stacks on germanium Thermally grown GeO 2 layers have been prepared at 550 °C to minimise GeO volatilisation GeO 2 growth has been performed in both pure O 2 ambient and O 2 diluted with N 2 GeO 2 thickness has been scaled down to approximately 3 nm MOS capacitors have been fabricated using different GeO 2 thicknesses with a standard high- κ dielectric on top Electrical properties and thermal stability have been tested up to at least 350 °C The κ value of GeO 2 was experimentally determined to be 45 Interface state densities ( D it ) of less than 10 12 cm −2 eV −1 have been extracted for all devices using the conductance method