Showing papers in "Solid-state Electronics in 2013"

Analytical model for ultra-thin body junctionless symmetric double gate MOSFETs in subthreshold regime

Abstract: In this paper, we propose an approximate solution to solve the two dimensional potential distribution in ultra-thin body junctionless double gate MOSFET (JL DG MOSFET) operating in the subthreshold regime. Basically, we solved the 2D-Poisson equation along the channel, while assuming a parabolic potential across the silicon thickness, which in turn leads to some explicit relationships of the subthreshold current, subthreshold slope (SS) and drain induced barrier lowering (DIBL). This approach has been assessed with Technology Computer Aided Design (TCAD) simulations, confirming that this represents an interesting solution for further implementation in generic JL DG MOSFETs compact models.

Analysis of trap-assisted tunneling in vertical Si homo-junction and SiGe hetero-junction Tunnel-FETs

Abstract: This paper reports on the integration of vertical nTunnel FETs (TFETs) with SiGe hetero-junction and analyzes the presence of trap-assisted tunneling impacting the device behavior Temperature measurements are used to distinguish the band-to-band tunneling (BTBT) from the trap-assisted tunneling (TAT) It is shown that TAT degrades the onset characteristic and the subthreshold swing of the devices TCAD simulations are in good agreement with experimental data for a germanium content up to 44%, when including non-local TAT model and properly tuning the model’s parameters Simulations also suggest that boosting the BTBT component, for example by further bandgap decrease (Ge source), or by other means should be beneficial in lowering the impact of trap-assisted tunneling, provided that the material defectivity does not worsen

Graphene based field effect transistors: Efforts made towards flexible electronics

Abstract: The integration of flexibility in existing electronics has been realized as a key point for practical application of unusual format electronics that can extend the application limit of biomedical equipments and of course daily routine kind of electronic devices. Graphene showed the great potentiality for flexible format owing to its excellent electronic, mechanical and optical properties. Field effect transistor (FET) is a basic unit for digital and analog electronics thus enormous efforts have been attempted to fabricate the flexible FETs in order to get the high performance. This article reviews the recent development of graphene based FETs including the fabrication and active layers material compatibility in flexible format.

Revisited parameter extraction methodology for electrical characterization of junctionless transistors

Abstract: Several electrical parameters characterize device performance, electron transport and doping level in MOS transistors. In this paper, Junctionless Transistors (JLTs) fabricated on (100) silicon on insulator (SOI) wafer with 145 nm thick BOX and 9 nm silicon thickness were considered. Parameter extraction methodologies were revisited in order to account for the unique electrical properties of JLT devices. The deduced parameters, such as threshold voltage, flat-band voltage, drain induced barrier lowering (DIBL), low field mobility and channel doping level, are shown to reveal the specific features of JLT compared to conventional inversion-mode transistors.

Pressure sensors based on suspended graphene membranes

Abstract: A novel pressure sensor based on a suspended graphene membrane is proposed. The sensing mechanism is explained based on tight binding calculations of strain-induced changes in the band structure. A ...

High performance printed N and P-type OTFTs enabling digital and analog complementary circuits on flexible plastic substrate

Abstract: This paper presents a printed organic complementary technology on flexible plastic substrate with high performance N and P-type Organic Thin Film Transistors (OTFTs), based on small-molecule organic semiconductors in solution. Challenges related to the integration of both OTFT types in a common complementary flow are addressed, showing the importance of surface treatments. Stability on single devices and on an elementary complementary digital circuit (ring oscillator) is studied, demonstrating that a robust and reliable flow with high electrical performances can be established for printed organic devices. These devices are used to manufacture several analog and digital building blocks. The design is carried out using a model specifically developed for this technology, and taking into account the parametric variability. High-frequency measurements of printed envelope detectors show improved speed performance, resulting from the high mobility of the OTFTs. In addition, a compact dynamic flip–flop and a low-offset comparator are demonstrated, thanks to availability of both n-type and p-type OTFTs in the technology. Measurement results are in good agreement with the simulations. The circuits presented establish a complete library of building blocks for the realization of a printed RFID tag.

Low-temperature electrical characterization of junctionless transistors

Abstract: The electrical performance of junctionless transistors (JLTs) with planar structures was investigated under low-temperature and compared to that of the traditional inversion-mode (IM) transistors. The low-field mobility ( μ 0 ) of JLT devices was found to be limited by phonon and neutral defects scattering mechanisms for long gate lengths, whereas scattering by charged and neutral defects mostly dominated for short gate lengths, likely due to the defects induced by the source/drain (S/D) implantation added in the process. Moreover, the temperature dependence of flat-band voltage ( V fb ), threshold voltage ( V th ) and subthreshold swing ( S ) of JLT devices was also discussed.

High mobility CMOS technologies using III–V/Ge channels on Si platform

Abstract: MOSFETs using channel materials with high mobility and low effective mass have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. From this viewpoint, attentions have recently been paid to Ge and III–V channels. In this paper, possible solutions for realizing III–V/Ge MOSFETs on the Si platform are presented. The high quality III–V channel formation on Si substrates can be realized through direct wafer bonding. The gate stack formation is constructed on a basis of atomic layer deposition (ALD) Al 2 O 3 gate insulators for both InGaAs and Ge MOSFETs. As the source/drain (S/D) formation, Ni-based metal S/D is implemented for both InGaAs and Ge MOSFETs. By combining these technologies, we demonstrate successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs on a same wafer and their superior device performance.

A comprehensive review on microwave FinFET modeling for progressing beyond the state of art

Abstract: FinFET is a multiple-gate silicon transistor structure that nowadays is attracting an extensive attention to progress further into the nanometer era by going beyond the downscaling limit of the conventional planar CMOS technology. Although the interest for this architecture has been mainly devoted to digital applications, the analysis at high frequency is crucial for targeting a successful mixed integration of analog and digital circuits. In view of that, the purpose of this review paper is to provide a clear and exhaustive understanding of the state of art, challenges, and future trends of the FinFET technology from a microwave modeling perspective. Inspired by the traditional modeling techniques for conventional MOSFETs, different strategies have been proposed over the last years to model the FinFET behavior at high frequencies. With the aim to support the development of this technology, a comparative study of the achieved results is carried out to gain both a useful feedback to investigate the microwave FinFET performance as well as a valuable modeling know-how. To accomplish a comprehensive review, all aspects of microwave modeling going from linear (also noise) to non-linear high-frequency models are addressed.

Implication logic gates using spin-transfer-torque-operated magnetic tunnel junctions for intrinsic logic-in-memory

Abstract: As the feature size of CMOS components scales down, the standby power losses due to high leakage currents have become a top concern for modern circuit design. Introducing non-volatility in logic circuits allows to overcome the standby power issue. Magnetic tunnel junctions (MTJs) offer a great potential, because of their non-volatility, unlimited endurance, CMOS compatibility, and fast switching speed. This work proposes current- and voltage-controlled MTJ-based implication (IMP) logic gtes for future non-volatile logic-in-memory architecture. The MTJ-based implication logic realizes an intrinsic logic-in-memory known as “stateful” logic for which the MTJ devices serve simultaneously as memory elements and logic gates. Spintronic implication logic gates are analyzed by using a SPICE model for spin-transfer torque (STT) MTJs in order to show the reliability of the IMP operation. It has been demonstrated that the proposed current-controlled implication gate offers a higher performance (power and reliability) than the conventional voltage-controlled one. The realization of the spintronic stateful logic operations extends non-volatile electronics from memory to logical computing applications and opens the door for more complex logic functions to be realized with MTJ-based devices. We present a stateful logic circuit based on the common STT-MRAM architecture capable of performing material implication. As an application example, an IMP-based implementation of a full-adder is presented.

A systematic study of the sharp-switching Z2-FET device: From mechanism to modeling and compact memory applications

Abstract: This paper presents a systematic study of a sharp-switching device built in fully-depleted silicon-on-insulator (FD-SOI) that we have called Z 2 -FET, as it features zero subthreshold swing ( 2 -FET is a compact device with a single front gate that experimentally demonstrates a current I ON / I OFF ratio >10 8 at low supply voltage, as well as gate-controlled hysteresis. The operating principle of the sharp switching involves the positive feedback between carrier flow and gate-controlled injection barriers, as confirmed by TCAD simulations. We discuss the impact of bias and device dimensions on the experimental performance and simulate the Z 2 -FET’s ultimate scaling capability to 2 -FET. With good reliability and relative insusceptibility to temperature variation, the envisioned applications of the Z 2 -FET include compact, high-speed one transistor DRAM (1T-DRAM), one-transistor SRAM, fast logic and electrostatic discharge (ESD) protection circuits.

Progress in Z(2)-FET 1T-DRAM: Retention time, writing modes, selective array operation, and dual bit storage

Abstract: In this paper, we extend our studies on the use of zero impact ionization and zero subthreshold swing field-effect-transistor (Z 2 -FET) as a capacitor-less one-transistor dynamic random access memory (1T-DRAM) through both experiment and TCAD simulation. The data retention time is measured as a function of biasing, temperature and device dimensions, leading to a simple predictive model. An alternative writing method using the source MOSFET is presented, which is potentially more compatible with the conventional DRAM array design. The operation of a Z 2 -FET memory array is discussed, in which the write and read signals are adapted from the single cell to achieve selective operation. Finally, we present simulations demonstrating that the Z 2 -FET can be used to store multiple bits thanks to the charges on both the top and bottom gate capacitors.

Direct observation of 0.57 eV trap-related RF output power reduction in AlGaN/GaN high electron mobility transistors

Abstract: This paper reports direct evidence for trap-related RF output power loss in GaN high electron mobility transistors (HEMTs) grown by metal organic chemical vapor deposition (MOCVD) through increased concentration of a specific electron trap at E C −0.57 eV that is located in the drain access region, as a function of accelerated life testing (ALT). The trap is detected by constant drain current deep level transient spectroscopy (CI D -DLTS) and the CI D -DLTS thermal emission time constant precisely matches the measured drain lag. Both drain lag and CI D -DLTS measurements show this state to already exist in pre-stressed devices, which coupled with its strong increase in concentration as a function of stress in the absence of significant increases in concentrations of other detected traps, imply its role in causing degradation, in particular knee walkout. This study reveals E C −0.57 eV trap concentration tracks degradation induced by ALT for MOCVD-grown HEMTs supplied by several commercial and university sources. The results suggest this defect has a common source and may be a key degradation pathway in AlGaN/GaN HEMTs and/or an indicator to predict device lifetime.

A unified analytical continuous current model applicable to accumulation mode (junctionless) and inversion mode MOSFETs with symmetric and asymmetric double-gate structures

Abstract: A unified analytical continuous model, based on an approximate solution of Poisson’s equation, is proposed for the current–voltage (I–V) characteristics of accumulation mode (junctionless FETs) and conventional inversion mode MOSFETs which have symmetric and asymmetric double-gate structures. As a unified model, it is applicable to both junctionless and conventional double-gate (DG) MOSFETs and also represents the I–V characteristics of the MOSFETs with symmetric and asymmetric cases. The model with symmetric and asymmetric gates accounts for body doping, body thickness, and front-gate and back-gate oxide thicknesses. The model is verified by comparing with TCAD simulation results and shows a good agreement.

Characteristics of nanostructured CdO/Si heterojunction photodetector synthesized by CBD

Abstract: In the present work, CdO/Si heterojunction detectors were fabricated by depositing nanostructured CdO film on single crystal silicon wafer by chemical bath deposition (CBD) technique. Films deposition was carried out at different temperatures. To obtain good film stoichiometry heating of films in static air at temperature of 400 °C for 90 min was carried out. The structural properties of CdO films was characterized by X-ray diffraction and atomic force microscope (AFM), these investigations showed that the deposited CdO films have cubic structure. The surface morphology investigation revealed that CdO film is almost homogeneous and consisted of the nanowires with diameter less than 100 nm at temperature of solution 40 °C.The band gap of the films changes from 2.4 to 2.5 eV with increasing preparation temperature. The current–voltage characteristics of photodiodes under dark exhibit good rectification behavior and that ideality factor of heterojunction was found to be in the range of 1.56–3.69 depending on solution temperature. The capacitance–voltage characteristic shows a typical abrupt heterojunction and the built-in-potential was determined. CdO/Si detector has good spectral responsivity in visible and NIR and the maximum responsivity was 0.56 A/W. Rise time of the photodetectors was strongly dependent on solution temperature and the shortest rise time obtained was 45 ns at 2 V.

Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold region

Abstract: This report focuses on the development of an analytical two-dimensional model to calculate the potential within ultra-scaled junctionless double-gate MOSFETs (DG MOSFETs), which is valid in the subthreshold regime. From that we derive an expression for calculating the threshold voltage of such devices, and present our first results. Compared to conventional MOSFETs, the proposed junctionless transistor has no pn-junctions. Its type of doping in the channel region is the same as in the source/drain regions. The device is turned on by creating a conducting channel in the center of the silicon film, and turned off by depleting it. To achieve good I on / I off ratios, and to ensure a safe switching behavior, the investigation of the subthreshold region is therefore important. The analytical model is compared with numerical simulation results from TCAD Sentaurus. Its validity is confirmed for long-channel, as well as for ultra-scaled devices having a channel length about 22 nm. Since the junctionless device is still in its infancy, an analytical model, especially for short-channel devices, can provide help to understand its electrostatic characteristics.

RTS noise characterization of HfOx RRAM in high resistive state

Abstract: In this paper we analyze Random Telegraph Signal (RTS) noise and Power Spectral Density (PSD) in hafnium-based RRAMs. RTS measured in HRS exhibits fast and slow multilevel switching events. RTS characteristics are examined through novel color-coded time-lag plots and Hidden Markov Model (HMM) time-series analyses. Results are validated by comparing simulated and experimental PSD. Noise is examined at different reset conditions to provide an insight into the conduction mechanisms in HRS. Higher reset voltages are found to result in greater RTS complexity due to a larger number of active traps as confirmed by PSD.

UTBB SOI MOSFETs analog figures of merit: Effects of ground plane and asymmetric double-gate regime

Abstract: In this work we investigate the effect of ground plane (GP) on analog figures of merit (FoM) of ultra-thin body and thin buried oxide (UTBB) SOI MOSFETs. Based on experimental devices, both n- and p-type GP configurations are considered and compared with standard no-GP substrates. In a standard single-gate (SG) regime, the effect of GP implementation on analog FoM (related to slightly higher body factor and improved gate-to-channel coupling) is negligible. Moreover, p-GP implementation allows higher intrinsic gain at high frequency compared with no-GP and n-GP substrates. Furthermore, we demonstrate that application of an asymmetric double-gate (ADG) (i.e. front-gate to back-gate/substrate connection) regime allows better control of short-channel effects in terms of drain induced barrier lowering, subthreshold slope and threshold voltage control, due to improved gate(s)-to-channel coupling. Application of an ADG mode is shown to enhance analog FoM such as transconductance, drive current and intrinsic gain of UTBB SOI MOSFETs. Finally, simulations predict that improvements of analog FoM provided by ADG mode can be obtained in the whole dynamic operation range. Moreover, ADG mode provides elimination of the high-frequency substrate coupling effects.

Development of an ethanol sensor based on CBD grown ZnO nanorods

Abstract: In this paper, we report on development of an ethanol sensor based on ZnO hexagonal nanorods grown by a chemical bath deposition technique. Nanorods were deposited on a SiO 2 coated p-Si substrate. Nanocrystalinity, stoichiometry, and surface roughness of the nanorods were determined by X-ray diffraction (XRD), field emission scanning electron microscopy (FESEM), and atomic force microscopy (AFM). The average diameter and average length of the nanorods were found to be ∼70 nm and ∼500 nm, respectively. Four types of sensors structures, to investigate the effect of catalytic metal alloy electrode (Pd–Ag) and Pd nanoparticle sensitization, were fabricated. All the sensors were tested for sensing ethanol vapor in the temperature range of 27–300 °C. The incorporation of catalytic electrode Pd–Ag (70%) and surface modification of nanorods by Pd nanoparticle improved the ethanol sensing performance. For Pd modified nanorods (with catalytic electrode), response magnitude, response time, and recovery time was 94%, 14 s and 70 s (respectively) at 1530 ppm of ethanol (in air) at an optimum operating temperature of 200 °C. The dynamic range of the sensors was also found to be quite appreciable (190–1530 ppm ethanol in air).

Flexible double gate a-IGZO TFT fabricated on free standing polyimide foil

Abstract: In this paper, the concept of double gate transistors is applied to mechanically flexible amorphous indium–gallium–zinc-oxide (a-IGZO) thin film transistors (TFTs) fabricated on free standing plastic foil. Due to the temperature sensitivity of the plastic substrate, a-IGZO is a suitable semiconductor because it provides carrier mobilities around 10 cm 2 /Vs when deposited at room temperature. Double gate TFTs with connected bottom and top gate are compared to bottom gate reference TFTs fabricated on the same substrate. Double gate a-IGZO TFTs exhibit a by 78% increased gate capacitance, a by 700 mV higher threshold voltage, and therefore an up to 92% increased transconductance when characterized at the same gate voltage above threshold (over-bias voltage). The subthreshold swing and the on/off current ratios are improved as well, and reach excellent values of 69 mV/dec and 2 × 10 9 , respectively. The mechanical flexibility of double gate TFTs compared to bottom gate TTFs is investigated, and device operation is shown while the double gate TFT is exposed to tensile strain of 0.55%, induced by bending to a radius of 5 mm.

Drain-conductance optimization in nanowire TFETs by means of a physics-based analytical model

Abstract: In this work we propose a physics-based analytical model of nanowire tunnel FETs, which is meant to provide a fast tool for an optimized device design. The starting point of the model is the Landauer expression of the current for 1D physical systems, augmented with suitable expressions of the tunneling probability across the tunnel junctions and the whole channel. So doing, we account for the ambipolar effect, as well as for the tunnel-related leakage current, which becomes appreciable when small band-gap materials are used. The model is validated by comparison with numerical simulation results provided by the k · p technique. With this model we examine the problem of the non-linear output characteristics of tunnel FETs, and the related small drain conductance at low drain voltage, which prevents rail-to-rail logic switching, and design a nanowire TFET by an appropriate selection of the material, nanowire size and degeneracy levels in the source and drain regions.

A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors

Abstract: This work proposes a physically-based definition for the threshold voltage, V TH , of junctionless nanowire transistors and a methodology to extract it. The V TH is defined as the point of equal magnitude for the drift and diffusion components of the drain current. The methodology for V TH extraction uses the device transconductance over drain current ratio characteristics. An analytical model for the threshold voltage based on the same definition has also been developed. Both V TH extraction method and model have been validated through 3D simulations and have been applied to experimental devices. The proposed method has shown to provide a correct dependence on the temperature, while the double derivative of the drain current method overestimates this variation.

A subthreshold current model for nanoscale short channel junctionless MOSFETs applicable to symmetric and asymmetric double-gate structure

Abstract: We proposed models of subthreshold characteristics for deep nanoscale short channel asymmetric junctionless Double-Gate (DG) MOSFETs. Models were derived by solving 2-D Poisson’s equation using variable separation technique. The subthreshold behavior with structure asymmetry such as different gate oxide thicknesses and different gate biases between the front-gate and back-gate can be exactly described. Design parameters such as body doping, body thickness and channel length were considered. The models were verified by comparing with device simulations’ results.

A resistive-type sensor based on flexible multi-walled carbon nanotubes and polyacrylic acid composite films

Abstract: A humidity sensor film was fabricated by loading high numbers of multi-wall carbon nanotubes (MWCNTs) in a poly(acrylic acid) (PAA) polymer matrix containing poly(4-styrenesulfonic acid) (PSS) to enhance the MWCNT dispersion. Cross-section images demonstrate that the MWCNTs distribute evenly throughout the matrix. The fabrication processes and sensing mechanisms of the film are explained to investigate the flexible properties and humidity-sensing characteristics of the film. The film loaded with 33 wt% MWCNTs is much more flexible than an overhead projector (OHP) film and shows similar electrical resistance to pure CNT Bucky paper. The sensor film composed of 1:2 MWCNTs:PAA is highly sensitive to humidity (0.069/% RH ) and displays good linearity (0.99).

Downscaling ferroelectric field effect transistors by using ferroelectric Si-doped HfO2

Abstract: Throughout the 22 nm technology node HfO 2 is established as a reliable gate dielectric in contemporary complementary metal oxide semiconductor (CMOS) technology. The working principle of ferroelectric field effect transistors FeFET has also been demonstrated for some time for dielectric materials like Pb[Zr x Ti 1− x ]O 3 and SrBi 2 Ta 2 O 9 . However, integrating these into contemporary downscaled CMOS technology nodes is not trivial due to the necessity of an extremely thick gate stack. Recent developments have shown HfO 2 to have ferroelectric properties, given the proper doping. Moreover, these doped HfO 2 thin films only require layer thicknesses similar to the ones already in use in CMOS technology. This work will show how the incorporation of Si induces ferroelectricity in HfO 2 based capacitor structures and finally demonstrate non-volatile storage in nFeFETs down to a gate length of 100 nm. A memory window of 0.41 V can be retained after 20,000 switching cycles. Retention can be extrapolated to 10 years.

Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors

Abstract: A new charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors (SDGJLTM) is proposed and validated with simulations for doping concentrations of 5 × 1018 and 1 × 1019 cm−3, as well as for layer thicknesses of 10, 15 and 20 nm. The model is physically-based, considering both the depletion and accumulation operating conditions. Most model parameters are related to physical magnitudes, and the extraction procedure for each of them is well established. The model provides an accurate description of the transistor behavior in all operating conditions. Among important advantages with respect to previous models are the inclusion of the effect of the series resistance and the fulfilment of the requirement of being symmetrical with respect to Vd = 0 V.

Low-frequency noise behavior of junctionless transistors compared to inversion-mode transistors

Abstract: Low-frequency (LF) noise characteristics of wide planar junctionless transistors (JLTs) are investigated. Interestingly, carrier number fluctuation is the main contributor to the LF noise behavior of JLT devices, even though their bulk conduction features are clearly proved by the extracted flat-band voltage (Vfb). This is explained by the fact that mobile electrons in depletion, originating from the bulk neutral channel or source/drain regions, can interact with slow traps in the gate oxide, giving rise in return to fluctuations of the charge density in the bulk neutral channel. Similar values of trap density (Nt) are extracted in JLT devices and inversion-mode (IM) t0072ansistors, which also supports that the LF noise of JLT is well explained by the carrier number fluctuation model.

Resistive switching in zinc–tin-oxide

Abstract: Bipolar resistive switching is demonstrated in the amorphous oxide semiconductor zinc–tin-oxide (ZTO). A gradual forming process produces improved switching uniformity. Al/ZTO/Pt crossbar devices show switching ratios greater than 10 3 , long retention times, and good endurance. The resistive switching in these devices is consistent with a combined filamentary/interfacial mechanism. Overall, ZTO shows great potential as a low cost material for embedding memristive memory with thin film transistor logic for large area electronics.

Precise analytical model for short channel Cylindrical Gate (CylG) Gate-All-Around (GAA) MOSFET

Abstract: A compact analytical model is presented for device electrostatics of nanoscale Cylindrical Gate (CylG) Gate-All-Around (GAA) MOSFET, using isomorphic polynomial function for potential distribution. The model is based on solutions of 3D Laplace and Poisson’s equations for subthreshold and strong inversion region respectively. In this paper, the short-channel effects are precisely accounted for by introducing z dependent characteristic length and the developed electrostatics is tested against analysis of crossover point for device under test. Further, the modeled subthreshold slope for lightly doped CylG GAA MOSFET has been improved by introducing z dependent characteristic length and the position of minimum center potential in the channel is obtained by virtual cathode position. A new model is proposed for threshold voltage, based on shifting of inversion charge from center line to silicon insulator interface.

Modelling of MWIR HgCdTe complementary barrier HOT detector

Abstract: The paper reports on the photoelectrical performance of medium wavelength infrared (MWIR) HgCdTe complementary barrier infrared detector (CBIRD) with n -type barriers. CBIRD nB 1 nB 2 HgCdTe/B 1,2 - n type detector is modelled with commercially available software APSYS by Crosslight Software Inc. The detailed analysis of the detector’s performance such as dark current, photocurrent, responsivity, detectivity versus applied bias, operating temperature, and structural parameters (cap, barriers and absorber doping; and absorber and barriers compositions) are performed pointing out optimal working conditions. Both conduction and valence bands’ alignment of the HgCdTe CBIRD structure are calculated stressing their importance on detectors performance. It is shown that higher operation temperature (HOT) conditions achieved by commonly used thermoelectric (TE) coolers allows to obtain detectivities D ∗ ≈ 2 × 10 10 cm Hz 1/2 /W at T = 200 K and reverse polarisation V = 400 mV, and differential resistance area product RA = 0.9 Ωcm 2 at T = 230 K for V = 50 mV, respectively. Finally, CBIRD nB 1 nB 2 HgCdTe/B 1,2 - n type state of the art is compared to unipolar barrier HgCdTe nBn/B- n type detector, InAs/GaSb/B-Al 0.2 Ga 0.8 Sb type-II superlattice (T2SL) nBn detectors, InAs/GaSb T2SLs PIN and the HOT HgCdTe bulk photodiodes’ performance operated at near-room temperature ( T = 230 K). It was shown that the RA product of the MWIR CBIRD HgCdTe detector is either comparable or higher (depending on structural parameters) to the state of the art of HgCdTe HOT bulk photodiodes and both A III B V 6.1 A family T2SLs nBn and PIN detectors.