Showing papers in "Solid-state Electronics in 2015"

Universal analytic model for tunnel FET circuit simulation

Abstract: A simple analytic model based on the Kane–Sze formula is used to describe the current–voltage characteristics of tunnel field-effect transistors (TFETs). This model captures the unique features of the TFET including the decrease in subthreshold swing with drain current and the superlinear onset of the output characteristic. The model also captures the ambipolar current characteristic at negative gate–source bias and the negative differential resistance for negative drain–source biases. A simple empirical capacitance model is also included to enable circuit simulation. The model has fairly general validity and is not specific to a particular TFET geometry. Good agreement is shown with published atomistic simulations of an InAs double-gate TFET with gate perpendicular to the tunnel junction and with numerical simulations of a broken-gap AlGaSb/InAs TFET with gate in parallel with the tunnel junction.

Future of nano CMOS technology

Abstract: Although Si MOS devices have dominated the integrated circuit applications over the four decades, it has been anticipated that the development of CMOS would reach its limits after the next decade because of the difficulties in the technologies for further downscaling and also because of some fundamental limits of MOSFETs. However, there have been no promising candidates yet, which can replace Si MOSFETs with better performance with low cost. Thus, for the moment, it seems that we have to stick to the Si MOSFET devices until their end. The downsizing is limited by the increase of off-leakage current between source and drain. In order to suppress the off-leakage current, multi-gate structures (FinFET, Tri-gate, and Si-nanowire MOSFETs) are replacing conventional planar MOSFETs, and continuous innovation of high-k/metal gate technologies has enabled EOT scaling down to 0.9 nm in production. However, it was found that the multi-gate structures have a future big problem of significant conduction reduction with decrease in fin width. Also it is not easy to further decrease EOT because of the mobility and reliability degradation. Furthermore, the development of EUV (Extremely Ultra-Violet) lithography, which is supposed to be essential for sub-10 nm lithography, delays significantly because of insufficient illumination intensity for production. Thus, it is now expected that the reduction rate of the gate length, which has a strong influence on the off-leakage current, will become slower in near future.

Loss mechanisms influence on Cu2ZnSnS4/CdS-based thin film solar cell performance

Abstract: One of the most important issues in kesterite Cu2ZnSnS4 (CZTS)-based thin film solar cells is low open circuit voltage, which is mainly related to loss mechanisms that take place in both CZTS bulk material and CdS/CZTS interface. A device model for CZTS/CdS solar cell which takes into account loss mechanisms influence on solar cell performance is presented. The simulation results showed that our model is able to reproduce experimental observations reported for CZTS/CdS-based solar cells with the highest conversion efficiencies, measured under room temperature and AM1.5 intensity. The comparison of simulation results to experimental observations demonstrated that among the different loss mechanisms, trap-assisted tunneling losses are the major hurdle to boost open circuit voltage. Under this loss mechanism, a solar cell efficiency enhancement up to 10.2% with CdS donor concentration decrease was reached. Finally, the possible path toward a further solar cell efficiency improvement is discussed.

Effect of chiral photosensitive liquid crystalline dopants on the performance of organic solar cells

Abstract: In order to design a new type of an organic solar cell device and to contribute for its performance optimization, i.e. transport and optical properties, a composite organic solar cell have been designed. It has been fabricated in two modifications from poly(3-hexylthiophene) and [6,6]-phenyl C61-butyric acid methyl ester mixtures (P3HT:PCBM) and two chiral photosensitive liquid crystalline (PCLC) materials used as additives. Doping of the P3HT:PCBM solar cell by a specific PCLCs led to a distinct adjustment (increase or decrease) of power conversion efficiency in comparison to that of an undoped cell and it is also strongly depends on the viscosity of the PEDOT:PSS used. In order to control the properties of the resulting composite P3HT:PCBM solar cells doped by PCLCs, the photovoltaic and impedance spectroscopy studies have been done for active layers annealed at different temperatures. Differential scanning calorimetry (DSC) in combination with polarized optical microscopy (POM) has been used to examine the morphology of an active layer. Thermal annealing of the sample within a mesophase temperature range can remove defects, optimize the morphology of the active layer, and hence might be responsible for the increase of photocurrent and cell efficiency.

Full gate voltage range Lambert-function based methodology for FDSOI MOSFET parameter extraction

Abstract: A new full gate voltage range methodology using a Lambert W function based inversion charge model, for extracting the electrical parameters in FDSOI nano-MOSFET devices, has been developed. Split capacitance–voltage measurements carried out on 14 nm technology FDSOI devices show that the inversion charge variation with gate voltage can be well described by a Lambert W function. Based on the drain current equation in the linear region including the inversion charge described by the Lambert function of gate voltage and the standard mobility equation enables five electrical MOSFET parameters to be extracted from experimental Id–Vg measurements (ideality factor, threshold voltage, low field mobility, first and second order mobility attenuation factors). The extracted parameters were compared with those extracted by the well-known Y-function in strong inversion region. The present methodology for extracting the electrical MOSFET parameters was verified over a wide range of channel lengths on nano-scale FDSOI devices, demonstrating its simplicity, accuracy and robustness.

Engineering of chalcogenide materials for embedded applications of Phase Change Memory

Abstract: Phase Change Memory technology can be a real breakthrough for process cost saving and performances for embedded applications. The feasibility at 90 nm technology node has been solidly proven in an industrial environment and the added value of this solution demonstrated. Nevertheless, for specific applications some improvement in High Temperature Data Retention (HTDR) characteristics is needed. In this work we present the engineering of chalcogenide materials in order to increase the stability of RESET state as a function of temperature. This goal has been achieved by exploring Ge-rich compounds in the Ge–Sb–Te ternary diagram. In particular, an optimized Ge x Sb y Te z Phase Change material, able to guarantee code integrity of the memory content after soldering thermal profile and data retention in extended temperature range has been obtained. Extrapolation of data retention at 10 years for temperatures higher than 150 °C cell-level has been demonstrated, thus enabling automotive applications.

Conductive filament structure in HfO2 resistive switching memory devices

Abstract: We study the filament structure in 50 nm × 50 nm Resistive Random Access Memory (ReRAM) cells in the forming/set state with a Hf/HfO2/TiN metal–insulator–metal stack by scanning transmission electron microscopy in cross section view. We reveal the filament morphology and, by the measurement of filament size and electrical resistance, evaluate the average resistivity of the filament material. The combination of the various data indicates the nanostructure of the conductive filament.

Evaluation and optimization of short channel ferroelectric MOSFET for low power circuit application with BSIM4 and Landau theory

Abstract: Based on BSIM4 parameters of 45 nm metal gate/high-k CMOS process and Landau theory, gate and output characteristics of short channel ferroelectric MOSFET (FeFET) are evaluated to explore its optimal structure for low power circuit application. Unlike previously reported simulation results of long channel FeFET, our work reveals that its current–voltage performance is quite susceptible to the parasitic capacitance between the gate and drain. As a consequence, there is a large threshold voltage increase with drain voltage and output characteristics hardly get saturated, indicating that short channel FeFET is not suitable for analog circuit applications. One effective way to address the issues is to minimize the gate-to-drain parasitic overlap and fringing field capacitances. With the tool Purdue Emerging Technology Evaluator, the inverter performance consisting of modified FeFETs is also simulated. Compared with intrinsic inverter, its energy consumption per cycle is much lower at any supply voltage VDD and the propagation delay is also smaller at very low VDD. Our work shows that the optimized FeFET structure, designed by mitigating gate-to-drain parasitic, is suitable for both analog and digital low power circuit designs.

Integration of highly-strained SiGe materials in 14 nm and beyond nodes FinFET technology

Abstract: SiGe has been widely used as stressors in source/drain (S/D) regions of Metal–Oxide-Semiconductor Field Effect Transistor (MOSFET) to enhance the channel mobility. In this study, selectively grown Si 1− x Ge x (0.33 ⩽ x ⩽ 0.35) with boron concentration of 1 × 10 20 cm −3 was used to elevate the S/D regions on bulk FinFETs in 14 nm technology node. The epitaxial quality of SiGe layers, SiGe profile and the strain amount of the SiGe layers were investigated. In order to in-situ clean the Si-fins before SiGe epitaxy, a series of prebaking experiments at temperature ranging from 740 to 825 °C were performed. The results showed that the thermal budget needs to be limited to 780–800 °C in order to avoid any damage to the shape of Si-fins but to remove the native oxide which is essential for high epitaxial quality. In this study, a kinetic gas model was also applied to predict the SiGe growth profile on Si-fins with trapezoidal shape. The input parameters for the model include growth temperature, partial pressures of reactant gases and the chip layout. By knowing the epitaxial profile, the strain to the Si-fins exerted by SiGe layers can be calculated. This is important in understanding the carrier transport in the FinFETs. The other benefit of the modeling is that it provides a cost-effective alternative for epitaxy process development as the SiGe profile can be readily predicted for any chip layout in advance.

An efficient BTX sensor based on ZnO nanoflowers grown by CBD method

Abstract: In this paper, sensing performance of ZnO nanoflower like structures derived by chemical bath deposition method (CBD), towards Benzene Toluene and Xylene (BTX) vapors is reported. Relatively higher bath temperature (110 °C) and high pH value (pH: 11) of solution escort to higher growth rate along [0 0 0 1] plane of ZnO, which eventually resulted in pointed edge nanorod based flower like structures after 3 h. After detailed structural characterizations (field emission scanning electron microscope (FESEM) and X-ray diffraction (XRD)), existence of different defect states (viz. oxygen vacancy (Vo), Zinc vacancy (VZn) and Zinc interstitials (Zni)) were authenticated by Photoluminescence (PL) spectroscopy. BTX sensing performance, employing the nanoflowers as the sensing layer, was carried out in resistive mode with two Pd lateral electrodes. The sensor study was performed at different temperatures (150–350 °C) in the concentration range of 0.5–700 ppm of the respective vapors. The highest normalized resistance response (NRR%) was achieved at 200 °C. At this optimum temperature, normalized resistance responses (39.3/92.6%, 45.8/96.9%, and 47.8/99% respectively) were found to be promising towards 0.5/700 ppm of benzene, toluene and xylene. The response time of the sensor towards the target species were also found to be appreciably fast (15 s, 6 s, and 5 s) towards 700 ppm of benzene, toluene and xylene respectively. Detailed sensing mechanism for BTX with such flower like ZnO structures was explained with the help of interaction of band structures (of ZnO) with the corresponding highest occupied molecular orbital (HOMO) and lowest unoccupied molecular orbital (LUMO) of the target species.

An in-depth study of thermal effects in reset transitions in HfO2 based RRAMs

Abstract: Reset transitions in HfO 2 based RRAMs operated at different temperatures have been studied. Ni/HfO 2 /Si-n + devices were fabricated and measured at temperatures ranging from 233 K to 473 K to characterize their reset features. In addition, a simulator including several coupled conductive filaments, series resistance and quantum effects was employed to analyze the same devices. The experimental results were correctly reproduced. It was found that the reset voltage and current show slight temperature dependence. To explain this fact, the roles of the out-diffusion of metallic species from the conductive filament and its conductance temperature dependence have been studied by simulation. The different conductive filament resistance components are also analyzed in the temperature range employed in our study. Finally, the thermal change in the energy barrier linked to quantum effects in the transport properties in the filament is modeled.

A modified capacitance model of RF MEMS shunt switch incorporating fringing field effects of perforated beam

Abstract: This paper deals with the approach to accurately model the capacitance of non-uniform meander based RF MEMS shunt switch with perforated structure. Here the general analytical model of capacitance is proposed for both up state and down state condition of the switch. The model also accounts for fringing capacitance due to beam thickness and etched holes on the beam. Calculated results are validated with the simulated results of full 3D FEM solver Coventorware in both the conditions of the switch. Variation of Up-state and Down-state capacitances with different dielectric thicknesses and voltages are plotted and error of analytical value is estimated and analyzed. Three benchmark models of parallel plate capacitance are modified for MEMS switch operation and their results are compared with the proposed model. Percentage contribution of fringing capacitance in up-state and down-state is approx. 25% and 2%, respectively, of the total capacitance. The model shows good accuracy with the mean error of −4.45% in up-state and −5.78% in down-state condition for a wide range of parameter variations and −2.13% for ligament efficiency of μ = 0.3.

A modern perspective on the history of semiconductor nitride blue light sources

Abstract: In this paper we shall discuss the development of blue light-emitting (LED) and laser diodes (LD), starting early in the 20th century. Various materials systems were investigated, but in the end, the nitrides of aluminum, gallium and indium proved to be the most effective. Single crystal thin films of GaN first emerged in 1968. Blue light-emitting diodes were first reported in 1971. Devices grown in the 1970s were prepared by the halide transport method, and were never efficient enough for commercial products due to contamination. Devices created by metal–organic vapor-phase epitaxy gave far superior performance. Actual true blue LEDs based on direct band-to-band transitions, free of recombination through deep levels, were finally developed in 1994, leading to a breakthrough in LED performance, as well as nitride based laser diodes in 1996. In 2014, the scientists who achieved these critical results were awarded the Nobel Prize in Physics.

Numerical study of read scheme in one-selector one-resistor crossbar array

Abstract: A comprehensive numerical circuit analysis of read schemes of a one selector–one resistance change memory (1S1R) crossbar array is carried out. Three schemes—the ground, V/2, and V/3 schemes—are compared with each other in terms of sensing margin and power consumption. Without the aid of a complex analytical approach or SPICE-based simulation, a simple numerical iteration method is developed to simulate entire current flows and node voltages within a crossbar array. Understanding such phenomena is essential in successfully evaluating the electrical specifications of selectors for suppressing intrinsic drawbacks of crossbar arrays, such as sneaky current paths and series line resistance problems. This method provides a quantitative tool for the accurate analysis of crossbar arrays and provides guidelines for developing an optimal read scheme, array configuration, and selector device specifications.

Wide frequency band assessment of 28 nm FDSOI technology platform for analogue and RF applications

Abstract: This work presents an in-depth wide-frequency band assessment of 28 nm FDSOI MOSFETs for analogue and RF applications. The focus is mainly on such figures of merit (FoM) as the transconductance gm, the output conductance gd, the intrinsic gain Av and the cut-off frequencies fT and fmax. Firstly, 28 nm FDSOI MOSFETs are compared with other advanced devices and are shown to outperform them. Secondly, gm–Av analogue metric is demonstrated to be affected by operation frequency. Small-signal parameters variation is limited and dominated by self-heating effect. This is in contrast to the first generation of ultra-thin body and BOX devices without a ground plane where coupling through the substrate has a considerable effect. Thirdly, the self-heating effect is analysed and shown to be smaller than previously predicted by simulations for such devices. Fourthly, it is shown that fT of 280 GHz and fmax of 250 GHz are reachable in the shortest devices. These values are compared to those of the first generation of UTBB devices through the effect of parasitic elements.

Investigation of the width-dependent static characteristics of graphene nanoribbon field effect transistors using non-parabolic quantum-based model

Abstract: The performance of graphene nanoribbon field effect transistor (GNR FET) is investigated from a numerical model based on self-consistent non-equilibrium Green’s Function (NEGF) formulism in mode-space with position-dependent effective mass model and tight-binding model. The model accounts for the tunneling currents on the static performance of GNR FETs in two semiconducting families of armchair GNRs (3p,0) and (3p+1,0). We conclude that increasing the GNR width in both GNR families increases the leakage current and subthreshold swing, and decreases I ON / I OFF ratio. In this scenario, GNR group (3p+1,0) leads to superior off-state performance such that GNR (7,0) has off-state current close to 2.5 × 10 − 16 A, five orders of magnitude lower than GNR (6,0) as well as 67 mV/decade subthreshold swing which is much smaller than that of 90 mV/decade in GNR (6,0).

Modeling and simulation of Double Gate Junctionless Transistor considering fringing field effects

Abstract: In the present work, the performance of DG-JL transistor has been analysed using analytical modeling scheme as well as 3D device simulation technique. Thus an advance two dimensional analytical sub-threshold drain current model for Double Gate Junctionless (DG-JL) Transistor is presented in this work by considering the impact of fringing field from the gate to source/drain region using conformal mapping technique. The results obtained from proposed model have been verified with the ATLAS 3D device simulation software results. The relevant Short Channel Effect parameters like threshold voltage roll off, Drain Induced Barrier Lowering (DIBL) and Subthreshold Slope (S) are also evaluated using modeling scheme. In addition to this, the suitability of DG-JL Transistor for low voltage digital and analog applications has been investigated through exhaustive device simulation using ATLAS 3D device simulation software only. In essence, this work provides the dependencies of the device performance on the physical device parameters of DG-JL transistor for its assessment for better digital and analog operation.

Gradual bipolar resistive switching in Ni/Si3N4/n+-Si resistive-switching memory device for high-density integration and low-power applications

Abstract: In this work, we report a gradual bipolar resistive switching memory device using Ni/Si 3 N 4 / n + -Si structure. Different reset transitions are observed depending on compliance current ( I COMP ). The reset switching becomes abrupt around I COMP = 10 mA, while gradual reset switching with fine controllability is preserved for the devices with I COMP I COMP and reset stop voltage ( V STOP ) for I COMP I COMP = 10 mA, low resistance state (LRS) shows Ohmic behavior with metallic conducting paths, while high resistance state (HRS) shows non-Ohmic behavior. Also, it is revealed that LRS and HRS conductions follow space-charge-limited current (SCLC) mechanism in low I COMP regime ( I COMP

Demonstration of radio-frequency response of amorphous IGZO thin film transistors on the glass substrate

Abstract: The relatively high-mobility metal-oxide thin-film transistors (TFTs) have the potential to realize radio-frequency (RF) circuits operating in the megahertz regime. Here, we investigate the RF performance of amorphous indium gallium zinc oxide (a-IGZO) TFTs on the glass substrate with the sputtered channel layer. The device exhibits a high current density of 22.6 mA/mm by employing thin bi-layer Al2O3/SiO2 gate dielectrics. The 1.5 μm gate length device achieves a current gain cutoff frequency fT of 384 MHz and a maximum frequency of oscillation fmax of 1.06 GHz. The record high RF response among the amorphous oxide channels makes it possible to explore new large-area electronics applications, such as low-cost radio frequency identification (RFID) tags. Furthermore, the corresponding small signal parameters were extracted and the voltage dependences of RF response were studied.

Hybrid Systems in Foil (HySiF) exploiting ultra-thin flexible chips

Abstract: Electronics embedded in foil is an enabling technology for flexible electronics and for special form factors of electronic components. In contrast to strictly printed electronics, Hybrid Systems-in-Foil (HySiF), comprising thin flexible, embedded chips and large-area thin-film electronic elements, feature a versatile and reliable technological solution for industrial applications of flexible electronics. This paper provides a comprehensive overview of HySiF technology, including aspects of thin-chip fabrication, reliability and assembly. Also presented is an industrial demonstrator utilizing such a HySiF component.

A bottom-gate silicon nanowire field-effect transistor with functionalized palladium nanoparticles for hydrogen gas sensors

Abstract: The highly sensitive operation of a bottom-gate silicon nanowire (SiNW) field-effect transistor (FET)based hydrogen (H2) sensor is demonstrated by controlling the working regime of the sensor. It is observed that the deposition of palladium (Pd) nanoparticles on the SiNW surface for the selective absorption of H2 can result in a significant enhancement of the electrostatic properties, such as the subthreshold swing and on-current, of the SiNW FET-based H2 sensor. By comparing the experimental results with the numerical simulation, we conclude that the improvement of the electrostatic properties of the sensor is due to the coupling effect between the electrostatic potentials in the Pd nanoparticle and bottom gate. Based on these results, highly sensitive detection of H2 gas could be achieved in the

In depth characterization of electron transport in 14 nm FD-SOI CMOS devices

Abstract: In this paper, carrier transport properties in highly scaled (down to 14 nm-node) FDSOI CMOS devices are presented from 77 K to 300 K. At first, we analyzed electron transport characteristics in terms of different gate-oxide stack in NMOS long devices. So, we found that SOP and RCS can be the dominant contribution of additional mobility scatterings in different temperature regions. Then, electron mobility degradation in short channel devices was deeply investigated. It can be stemmed from additional scattering mechanisms, which were attributed to process-induced defects near source and drain. Finally, we found that mobility enhancement by replacing Si to SiGe channel in PMOS devices was validated and this feature was not effective anymore in sub-100 nm devices. The critical lengths were around 50 nm and 100 nm for NMOS and PMOS devices, respectively.

Graphite/ZnO nanorods junction for ultraviolet photodetectors

Abstract: We report the fabrication of a graphite/ZnO nanorods (NRs) junction, which can act as a high-sensitivity ultraviolet (UV) photodetector, prepared by deposition of colloidal graphite on top of ZnO nanorod arrays obtained by low temperature hydrothermal growth. The photodetector is shown to be highly sensitive in a wide range of UV illumination intensities.

Hole injection and dielectric breakdown in 6H–SiC and 4H–SiC metal–oxide–semiconductor structures during substrate electron injection via Fowler–Nordheim tunneling

Abstract: Hole injection into silicon dioxide (SiO2) films (8–40 nm thick) is investigated for the first time during substrate electron injection via Fowler–Nordheim (FN) tunneling in n-type 4H- and 6H–SiC (silicon carbide) based metal–oxide–semiconductor (MOS) structures at a wide range of temperatures (T) between 298 and 598 K and oxide electric fields E ox from 6 to 10 MV/cm. Holes are generated in heavily doped n-type polycrystalline silicon ( n + -polySi) gate serving as the anode as well as in the bulk silicon dioxide (SiO2) film via hot-electron initiated band-to-band ionization (BTBI). In absence of oxide trapped charges, it is shown that at a given temperature, the hole injection rates from either of the above two mechanisms are higher in n-4H–SiC MOS devices than those in n-6H–SiC MOS structures when compared at a given E ox and SiO2 thickness ( t ox ). On the other hand, relative to n-4H–SiC devices, n-6H–SiC structures exhibit higher hole injection rates for a given t ox during substrate electron injection at a given FN current density j e , FN throughout the temperature range studied here. These two observations clearly reveal that the substrate material (n-6H–SiC and n-4H–SiC) dependencies on time-to-breakdown ( t BD ) or injected charge (electron) to breakdown ( Q BD ) of the SiO2 film depend on the mode of FN injections (constant field/voltage and current) from the substrate which is further verified from the rigorous device simulation as well.

Effect of annealing temperature and X-ray irradiation on the performance of tetraphenylporphyrin/p-type silicon hybrid solar cell

Abstract: Hybrid organic–inorganic heterojunction solar cell, Au/tetraphenylporphyrin (TPP)/p-Si/Al, was fabricated. The TPP films were deposited by thermal evaporation technique onto p-type silicon single crystal wafer. The current–voltage characteristics of the heterojunction diode have been studied at a temperature range of 298 – 390 K and the voltage applied during measurements varied from -1.5 to 2 V. The device showed a rectification behavior like a diode under different temperatures. It was found that the conduction mechanisms of the diode are controlled by the thermionic emission at forward voltage bias ⩽0.5 V and the single trap level space charge limited conduction (SCLC) mechanism at forward voltage bias >0.5 V. Dependence of the I – V characteristics on temperature, illumination and X-ray irradiation dose of 50 kGy for such a device have been studied. The dependence of photovoltaic parameters on annealing temperatures, illumination conditions and irradiation dose has been estimated. The calculated parameters are: series and shunt resistances, ideality factor, barrier potential, open-circuit voltage, short-circuit current, fill factor and efficiency.

Absorption coefficients of GeSn extracted from PIN photodetector response

Abstract: In this paper the optical absorption of the GeSn PIN photodetector was investigated. The vertical GeSn PIN photodetectors were fabricated by molecular beam epitaxy (MBE) and dry etching. By means of current density–voltage (J–V) and capacity–voltage (C–V) measurements the photodetector device was characterized. The absorption coefficients of GeSn material were finally extracted from the optical response of PIN structure. With further direct bandgap analysis the influences of device structure was proved negligible.

Short channel amorphous In–Ga–Zn–O thin-film transistor arrays for ultra-high definition active matrix liquid crystal displays: Electrical properties and stability

Abstract: The electrical properties and stability of ultra-high definition (UHD) amorphous In–Ga–Zn–O (a-IGZO) thin-film transistor (TFT) arrays with short channel (width/length = 12/3 μm) were examined. A-IGZO TFT arrays have a mobility of ∼6 cm2/V s, subthreshold swing (S.S.) of 0.34 V/decade, threshold voltage of 3.32 V, and drain current (Id) on/off ratio of

Analytical model of drain current of cylindrical surrounding gate p-n-i-n TFET

Abstract: An analytical model on the current–voltage characteristics of cylindrical surrounding gate p-n-i-n tunnel field-effect transistor (TFET) is developed. The model was derived by dividing the source, drain and channel regions into several portions so that some simple approximations for the surface potential across the tunneling junction and the channel can be achieved. Tunneling current is then calculated analytically by integrating the generation rate using the developed surface potential expressions over different regions. The results are verified with TCAD simulations. Good agreements in potential profile, transfer and output characteristics under different biasing conditions and with different device parameters are obtained. The applicability of this model for short-channel device is also discussed.

FDSOI bottom MOSFETs stability versus top transistor thermal budget featuring 3D monolithic integration

Abstract: To set up specification for 3D monolithic integration, for the first time, the thermal stability of state-of-the-art FDSOI (Fully Depleted SOI) transistors electrical performance is quantified. Post fabrication annealings are performed on FDSOI transistors to mimic the thermal budget associated to top layer processing. Degradation of the silicide for thermal treatments beyond 400 °C is identified as the main responsible for performance degradation for PMOS devices. For the NMOS transistors, arsenic (As) and phosphorus (P) dopants deactivation adds up to this effect. By optimizing both the n-type extension implantations and the bottom silicide process, thermal stability of FDSOI can be extended to allow relaxing upwards the thermal budget authorized for top transistors processing.

Effects of dielectric material properties on graphene transistor performance

Abstract: Graphene has attracted attention due to its excellent electrical properties; however, the electrical performance of graphene devices, including device hysteresis, mobility, and conductivity, tends to be limited by the supporting dielectric layer properties. In this work, the impact of a dielectric material on a graphene transistor was investigated by fabricating graphene field effect transistors integrated with four different dielectric substrates (SiO2, Al2O3, Si3N4 and hexagonal boron nitride) and by comparing the transistor performances. Results revealed that the carrier transport characteristics of the graphene transistors, including the hysteresis, Dirac point shift, and mobility, were highly correlated with the hydrophobicity-induced charge trapping and surface optical phonon energies of the dielectric materials.